Family and balance
My family keeps the work from becoming the whole story.
Beyond the work
Personal
Who I am when I’m not testing drives.
Outside the lab
Family, photographs, and projects
The habits I bring to the bench show up everywhere else too, with my family, behind a camera and in machines I still want to figure out.
Continuous learning
I read technical papers and take things apart until they make sense, then move on to the next one.
Side projects and code
I build small utilities and automations when an everyday problem deserves a better answer than a spreadsheet.
Photography and art
I ran a photography business from 2009 to 2016, shooting portraits, events and products.
Automotive aftermarket
Cars are another place where tuning and measuring meet.
The compass
Values that guide the work
In every review I repeat the measurement, question the result, follow a failure all the way through and report exactly what the device did.
- PrecisionMeasure it. Then measure it again.
- CuriosityNever stop at the first answer.
- PersistenceThe failures worth understanding take time to show up.
- AuthenticityWrite what the device actually did.
“The best engineers are also the most curious humans, always asking ‘why’ and never satisfied with surface-level answers.”
The person
Curiosity is the other instrument
The lab is only half of it. My family, my photography, side projects and the next system I don’t understand yet are the other half.
It’s the same instinct I bring to reviews. I look longer, ask why and don’t stop at the surface.
The builder’s mindset
Understand it. Then make it better
I like working out how a system works at the lowest level and then finding a way to make it work better. That goes for SSD testing and the tools I write, and for new technology, photography and cars too.
Hands-on experimenting keeps me sharp, and there’s always another system to figure out.
The professional side
Writing archive
Articles, chapters, and projects
144 published articles, chapters, and projects.
An MCP Server for the Eyes on Flash Data
Eyes on Flash now has a public, read-only MCP server: what it serves, how to connect, which sources it leaves out, and how it runs on Cloudflare's Free plan.
Storage and Memory in Practice, Part 7: Console and Handheld Storage
What the PS5, Xbox Series X|S, Steam Deck, other PC handhelds, and Switch 2 accept for added storage, and which of it plays games instead of only holding them.
Storage and Memory in Practice, Part 5: HDD Versus SSD on Cost, Power and Rebuild Time
Hard drives and SSDs compared on what a terabyte costs, what each draws at idle and under load, and how long a failed drive takes to rebuild.
Running a NAS, Part 7: Apps and Backing Up the NAS
Running apps and containers on a NAS, and backing the NAS itself up with snapshots, replication, vendor tools, rclone, restic, Borg and Kopia.
Running a NAS, Part 8: Keeping a NAS Healthy
Keeping a NAS healthy: SMART alerts, scrubs, replacing a drive and the rebuild window, UPS shutdown and updates.
Running a NAS, Part 5: Tuning the NAS Network
What 1GbE, 2.5GbE, 10GbE and 25GbE deliver from a NAS, and when SMB Multichannel, jumbo frames, link aggregation and a better network card or switch help.
Running a NAS, Part 1: NAS Operating Systems Compared
NAS operating systems compared, from Synology, QNAP, UGREEN, Asustor and TerraMaster boxes to TrueNAS, Unraid and OpenMediaVault, on cost, updates and hardware.
Running a NAS, Part 2: Pools and Filesystems on a NAS
How a NAS pools and protects its drives with ZFS, Btrfs, Unraid parity or SnapRAID and mergerfs, and how each one grows, rebuilds, scrubs and keeps snapshots.
Running a NAS, Part 9: NAS Problems Found Too Late
Hardware and setup problems NAS owners find after the build, from SMR drives and chip errata to dropping 2.5GbE ports and shared M.2 lanes, and how to check.
Running a NAS, Part 6: Sharing and Remote Access
Sharing a NAS over SMB, NFS and iSCSI, reaching it from outside the house, and locking it down against the ransomware campaigns that hit exposed NAS boxes.
Storage and Memory in Practice, Part 6: Portable SSDs and Enclosures
What USB and Thunderbolt ports carry, what a bridge chip does, why rated and real speed differ, and which port suits which portable SSD or M.2 enclosure.
Storage and Memory in Practice, Part 4: How to Read an SSD Spec Sheet
What each line on an SSD data sheet means: the conditions behind rated speeds, TBW and DWPD as one write budget, MTBF as a fleet rate, and warranty terms.
Running a NAS, Part 4: SSDs in a NAS
SSDs in a NAS as read and write cache, as ZFS special devices and as the whole pool, with what endurance, TRIM and power-loss protection mean for each job.
Running a NAS, Part 3: Drive Pooling on Windows
Turning a Windows PC into a NAS with StableBit DrivePool, Scanner and CloudDrive, Storage Spaces and SnapRAID, and what pooling does and does not protect.
Working Memory, Part 7: CXL Memory Explained
How CXL memory works: the three device types, what each release from 1.0 to 4.0 added, how the OS sees it, and the modules and controllers on sale.
How Storage Works, Part 2: How a Hard Drive Works
Heads, tracks, CMR and SMR, helium, HAMR and ePMR, and dual actuators: how a hard drive stores and finds data, and what its spec sheet labels mean.
How Storage Works, Part 4: PCIe Gen6 and Gen7 for Storage
What PCIe Gen6 changes for SSDs: the 256-byte flit and its cost, FEC and replay, L0p, OCP power and heat limits, the first Gen6 drives, and PCIe 7.0 and 8.0.
Storage and Memory in Practice, Part 3: SSDs for Builders
What an SSD box’s numbers mean, which M.2 slot gets which lanes on AMD and Intel boards, and how to set up and fix a drive in Windows and Linux.
How Storage Works, Part 3: Tape and Cold Archive
How LTO tape stores data and why it still wins on cost and power at rest, then what optical archive, glass and DNA storage are today and what is still research.
HDD Timeline
Hard drive capacity and recording method by year, from the first perpendicular drives to heat-assisted ones, each dated by the maker's release and linked.
Networking for SI, Part 5: CXL and SDXI Where They Touch Storage
Where CXL memory and SNIA’s SDXI data mover meet storage in SI clusters: checkpoint staging, the KV cache’s trip between servers, and copies between tiers.
Networking for SI, Part 3: DPUs and SmartNICs as Storage Engines
How a network card with its own processor shows the host a local NVMe drive, runs the NVMe-oF target and encrypts data, and what published tests say it costs.
Networking for SI, Part 2: The Four Networks in an SI Cluster
What the four networks in an SI cluster carry, why storage stays off the GPU fabric, and how to size it from MLPerf Storage's checkpoint test.
Networking for SI, Part 4: Ultra Ethernet Against RoCE
What Ultra Ethernet changes against RoCEv2: its own transport, packet spraying and congestion control, and which products are sampling, in market or qualifying.
SSD Benchmarking 201, Part 3: Three Enterprise SSDs on One Test Method
My Iometer runs on a Micron 9100 MAX, a Kingston DCP1000 and an Intel DC P4510, compared at matched queue depths and mixes, with latency read beside IOPS.
SSD Benchmarking 201, Part 1: Building a Repeatable Benchmark Job
How a benchmark job file pins block size, read mix, queue depth, ramp, runtime and preconditioning, in Iometer and in fio, so a run can be repeated and checked.
Flash in Phones and Tablets: One Board, Two Memories
How phone and tablet flash is packaged with LPDDR, from PoP to ePoP and uMCP, and what Android’s memory manager, F2FS and encryption do with it.
Flash in Small Devices: Routers, Cameras and Watches
What routers, cameras, smartwatches and IoT boards boot from: SPI NOR and SPI NAND, partitions, bad blocks, UBI and power-loss handling.
SSD Benchmarking 201, Part 4: Reading Published Enterprise SSD Reviews
How five enterprise SSD reviews tested their drives, where their numbers match my Iometer runs at matched settings, and how to read any review’s chart.
SSD Benchmarking 201, Part 2: Steady State and Tail Latency
When a preconditioned SSD is ready to measure under the SNIA test specification, and how to report its latency past the average with percentiles and QoS.
Automotive and Industrial Flash: Built for Heat and Wear
Why cars and factories need different flash: AEC-Q100 and AEC-Q104 grades, retention, endurance under logging, power-loss protection and the Tesla eMMC recall.
eMMC Explained: The Flash Storage Inside Cheap Devices
How eMMC works: a controller and NAND in one package on an eight-bit parallel bus, speed modes up to HS400, partitions, command queueing and real parts.
SD and microSD Cards: Classes, Bus Modes and SD Express
How SD and microSD cards work: capacity families, bus modes from Default Speed to UHS-III and SD Express, what speed classes promise, and how to test for fakes.
Networking for SI, Part 1: NVMe-oF and the Network Behind SI Storage
How NVMe over Fabrics carries NVMe commands over RDMA, TCP and Fibre Channel, what published tests say it adds in latency, and how SI storage traffic loads it.
Understanding SI, Part 2: Running Language Models Locally on Windows
How much VRAM, RAM, and disk a local language model needs on Windows, how quantization sets its size, and where Ollama, LM Studio, and WSL keep the files.
Memory and Storage for SI, Part 6: The Capacity Drives
What 122TB to 300TB QLC drives do in an SI cluster, why bigger drives write in bigger pieces, and how to read their endurance and hard drive comparisons.
Memory and Storage for SI, Part 5: Context Memory
How big a model’s KV cache gets, why inference keeps it, and the GPU, CPU memory, SSD, and shared storage tiers that hold it once HBM fills.
Memory and Storage for SI, Part 7: The Five-Minute Rule in Microseconds
Gray and Putzolu’s five-minute rule redone for flash that answers in microseconds, 512-byte reads, and GPU hosts, with every input sourced or labeled.
Storage and Memory in Practice, Part 1: DDR5 for Builders
What DDR5 speeds, timings, EXPO, XMP, and CUDIMM mean, what AM5, LGA1700, and LGA1851 officially support, and how to fix memory problems on a new build.
Why Eyes on Flash Now Writes SI
Eyes on Flash now writes SI, not AI, after Executive Order 14434: what the order says, what it leaves alone, and how the site applies it.
Understanding SI, Part 3: SI Agents Ranked, With the Computers They Keep
SI agents, long called AI agents, ranked: Grok Bot, OpenAI Dots, Muse, Tab, Gemini Spark, Claude Duet, Autopilot, local agents, and the storage they need.
Memory and Storage for SI, Part 4: Storage-Next and the 512-Byte Read
What NVIDIA’s Storage-Next initiative is, why SI inference reads storage 512 bytes at a time, and what Kioxia, Micron, and SK hynix have shown or planned.
Photolithography, Part 6: The Rest of Advanced Packaging
InFO, EMIB and Foveros, hybrid bonding and SoIC, bonded NAND and HBM, panels and glass, and co-packaged optics: how chip scaling moved into the package.
Storage and Memory in Practice, Part 2: Cloning and Backup in 2026
Clone, disk image, or file backup: which you need, what changed when Macrium Reflect Free stopped getting updates, and the free tools still doing each job.
Photolithography, Part 5: CoWoS in Full
How CoWoS gets past the reticle limit: the interposer, the S, R, and L variants, the build steps, HBM beside the GPU, and the capacity squeeze.
Photolithography, Part 3: High-NA EUV and What It Means for Memory
High-NA EUV’s anamorphic optics and half field, what comes after it, nanoimprint, and why DRAM took EUV while 3D NAND scaled by stacking instead.
Photolithography, Part 1: How a Chip Is Printed With Light
How a chip is printed with light: resist, masks, steppers and scanners, the wavelengths from mercury lamps to EUV, and how layers line up within a nanometer.
Understanding SI, Part 1: How Does SI Actually Know Anything?
What a language model’s knowledge is: tokens, weights, attention, and next-token training, what researchers see inside, and why memory bandwidth sets the speed.
A Full SSD Weighs More Than an Empty One
A full SSD is heavier or lighter than an empty one by about a billionth of a billionth of a gram per terabyte, by chip. Added electrons are not why.
Photolithography, Part 2: Resolution, From Mercury Lamps to EUV
Why chips need ever shorter light: Rayleigh’s equation, immersion lenses, k1 tricks, multi-patterning, resist limits, and how EUV makes 13.5nm light.
Memory and Storage for SI, Part 3: zNAND-O
What Samsung has said about zNAND-O, NAND packaged with a processor over UCIe for on-device SI: what is claimed, what is simulated, and what is unpublished.
Working Memory, Part 5: Current Memory ICs
A sourced guide to the DRAM chips in use now: DDR5, LPDDR5X, GDDR7 and HBM3E and HBM4, what is shipping, what is only sampling, and what is still research.
Photolithography, Part 4: How NAND Is Tested Before It Ships
How a NAND die is tested from first silicon to the field: wafer sorts, known good die, burn-in, final test, JEDEC qualification and ECC margining.
Working Memory, Part 6: CAMM2, LPCAMM2 and SOCAMM2
What CAMM2, LPCAMM2, and SOCAMM2 are, the JEDEC standards behind them, how they differ from SO-DIMMs and soldered LPDDR, and who makes them.
UFS Explained: The Flash Storage Inside Your Phone
How Universal Flash Storage works: its layers, eMMC and NVMe compared, M-PHY gears, versions 1.0 to 5.0, queueing, cards, cars and real parts.
Atlas
An interactive 3D reference that takes an M.2 NVMe SSD, an HBM stack and a DDR5 memory stick apart, from the package down to one memory cell.
How Storage Works, Part 1: The Memory and Storage Hierarchy
Nine memories from registers to tape on latency, bandwidth, capacity and cost, and the rule that decides where data lives.
Working Memory, Part 4: High Bandwidth Memory
What an HBM stack is, why its bus is wide rather than fast, why the chip edge limits bandwidth, and how a stack differs from a DIMM and from a new cell.
Beyond NAND, Part 4: Ferroelectric Memory From Polarization to Product
How polarization stores a bit, how a ferroelectric capacitor and a ferroelectric transistor differ, what wears them out, and what ships today.
Memory and Storage for SI, Part 8: Where Memory Goes Next
Places each memory family by the job it fills, sorts shipping from research, and says why DRAM is still unmatched.
Follow a Read
Follow one 4KiB read through a Samsung 990 Pro 2TB, from the host command to the NAND cell and back, with measured and published times for each stop.
Write of Passage
Follow one 4KB write through an SSD, frame by frame, from the host command to a programmed NAND cell, with a slider, a play button and a caption for each frame.
Working Memory, Part 2: DRAM From the Inside
How a DRAM cell is read and refreshed, how banks and ranks organize it, what DDR timing numbers measure, and how one cell serves three buses.
Memory and Storage for SI, Part 1: Memory as a Synapse
How a memory cell becomes an adjustable weight, how that weight is scored, why updates miss, what noise and drift cost, and what has shipped.
The Speed on the Box Is the Speed You Get
The write speed on the box, checked against 65 drives from my test bench: it holds for the first seconds, then all but one drive drops once its cache fills.
Once the Cache Fills, the Drive Stays Slow
A full SLC cache comes back after idle on drives that are not full, and almost never on full ones: 55 drives from my test bench, and 31 more agree.
DRAM-Less SSDs Are Slow
DRAM-less SSDs write small random data more slowly in my results, yet in my seven-drive set their PC workload scores overlapped the DRAM drives’ range.
A Gen5 SSD Loads Games Faster
A PCIe 5.0 drive reads far faster on paper, but my bench traces of game loading barely follow sequential speed, and press tests found small load-time gaps.
Hot NAND Is Bad for Your Data
Heat costs flash data when the data sits hot or is read cooler than it was written on worn flash, not because a drive runs warm while you use it.
Leave a Quarter to Half of the Drive Empty
Free space does lower an SSD's write amplification, but only when the drive knows it is free, and the evidence asks for far less than a quarter to half.
You Have to Run TRIM by Hand
Windows and the usual Linux setups already send TRIM and catch up on a schedule, so the real risk is a path that drops it, which a manual run does not fix.
Never Put the Pagefile on an SSD
What Windows keeps in the page file, how it reads and writes it, and what that costs an SSD in wear: Microsoft's own documents answer the pagefile myth.
A Power Cut Does Not Wipe Your SSD
Data already on an SSD mostly survives a power cut, but writes the drive acknowledged and has not yet stored can be lost, and one lab test found some lose more.
QLC Is Junk
QLC gives up endurance and sustained write speed to TLC, but on the everyday tests the first set of QLC drives I could identify sits inside the TLC range.
A Secure Erase Does Not Make an Old SSD Like New
What a block-erase secure erase gives back to a used SSD, free blocks and fresh speed, and what it cannot: the wear, retired blocks and the erase’s own cost.
A Higher Sequential Speed Means a Faster PC
Sequential read speed against the PCMark 10 Storage score of 84 drives on my bench: they rise together, but drives that read alike score up to 1.9 times apart.
Does an SSD Fail With No Warning?
Data-center studies show SSD errors repeat and the drive counts them, but the counters sit in a log few people read and the usual reliability number misses it.
Every NVMe SSD Needs a Heatsink
Whether a drive needs a heatsink depends on the drive and how long you push it; what I can back comes from the spec, the makers, a thermal model and my bench.
Do SSDs Wear Out in a Couple of Years?
My SMART data from a system drive, a test bench, new and used drives, against the ratings and field studies: a desktop SSD wears far slower than the myth says.
An Unplugged SSD Loses Its Data in Weeks
SSD retention is rated on a drive that has used up its writes, so the weeks-unplugged fear describes a worn, hot, powered-off worst case and not a normal drive.
Windows Defrags Your SSD and Wears It Out
Windows does defragment an SSD, once a month by Microsoft's account, and the Defrag Lab shows what a pass writes and what it buys.
Beyond NAND, Part 1: NOR and Memory on the Processor Die
How NOR differs from NAND, how a processor runs code in place, why embedded flash stopped fitting near 28nm, and what soldering and cars demand.
Beyond NAND, Part 2: Phase-Change Memory and Optane
How a phase-change cell stores a bit, what limits it, who built it, what 3D XPoint and Optane were and how they measured, why Optane ended, and what came after.
Working Memory, Part 3: What Could Follow DRAM
Why the DRAM cell is hard to shrink, what refresh costs, and what capacitorless, stacked and ferroelectric cells trade, with labs kept apart from roadmaps.
Reliability Math Lab
Five calculators for the math behind a spec sheet: codeword failure and UBER, AFR from MTBF, rating sample size, Arrhenius bake time and retention.
Memory and Storage for SI, Part 2: High Bandwidth Flash
What High Bandwidth Flash is, what the August 2026 OCP draft spec says, where its bandwidth comes from, and why writes and retention are its weak side.
The Memory Map: What Comes After Flash
Where NAND flash sits in the memory hierarchy, what Optane proved and why it ended, and what phase-change, MRAM, resistive and ferroelectric memory could add.
Beyond NAND, Part 3: MRAM From Tunnel Junction to Product
How a magnetic tunnel junction stores a bit, how current writes it by STT or SOT, what trades retention for speed, and what MRAM is sold as today.
Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar
How a resistive memory cell forms and switches, why cells disagree, why a crossbar needs a selector, and how the array multiplies and where that breaks.
Working Memory, Part 1: SRAM and the Processor Cache
How a six-transistor SRAM cell holds a bit, why it is fast, large and leaky, and why processor caches are built from it, some on a stacked die.
Controller Timeline
SSD controllers charted by the date of their public brief, with the fastest NAND speed each listed, its host link, and every row linked to its source.
DRAM Die Timeline
SDR, DDR, LPDDR and GDDR dies by vendor, dated by the earliest public source, with the JEDEC DDR data rate line and every value linked.
HBM Timeline
HBM stacks by vendor and the accelerators that used them, charted by the date of the earliest public source, with the JEDEC standard line and each value linked.
Crosspoint Lab
Read one cell of a crossbar memory, watch the sneak current that steals the signal, then try V/2 and V/3 biasing, a selector and a transistor.
Defrag Lab
Fragment a file on a simulated SSD, defrag it, and watch where it lands on the NAND, then try the fixes that do work.
NAND Die Timeline
Real NAND dies charted by the year of the earliest paper or announcement cited for each, with layers, bit density and interface speed, and every point sourced.
Parallelism Lab
Pick a real NAND die, a real controller and a capacity, and see which limit sets an SSD’s write speed: the dies programming, the channel buses or the PCIe link.
Secure Erase Lab
Write a secret to a simulated SSD, try delete, format, TRIM, overwrite and the drive's own erase commands, and count what is still on the chips.
Throttle Lab
Heat a simulated SSD and see how real drives throttle: stepped levels, I/O pacing, a Gen5 to Gen4 link drop, NVMe power states, a host-set limit or a shutdown.
How I Put Cloudflare's Clef in Front of My SI Chatbot
How I used Cloudflare's Clef decision model to screen off-topic and jailbreak questions for a handful of neurons before Cell's model answers.
How I Made SSD Validation Repeatable
How I turned SSD validation into a repeatable process: fixed phases, write saturation with idle recovery, power capture, and a report each run had to fill in.
AES Engine Lab
Step through every round of AES-128, AES-192 and AES-256, then the AES-XTS engine inside a self-encrypting SSD: per-LBA tweaks, key wrapping and crypto erase.
FTL & GC Sandbox
A flash translation layer and garbage-collection simulator that shows how overprovisioning, workload, TRIM and data placement change write amplification.
NAND Cell Lab
An interactive threshold-voltage simulator that shows how P/E cycling, retention, temperature and read disturb push NAND cells toward bit errors.
NVMe SMART Decoder
A browser tool that opens on a made-up example drive already decoded, then reads NVMe SMART / Health logs and Identify Controller data from nvme-cli, smartctl or raw hex, with endurance numbers.
Power Loss Lab
Cut power to a simulated SSD mid-write and see which writes come back, with and without capacitor-backed power loss protection, old capacitors and flushes.
TRIM Check
A browser checker for SSD TRIM. Run one read-only command, paste the output, and get a plain-language verdict on whether TRIM is on and what to do next.
How Cell Runs on Cloudflare's Free Plan
How I added an SI guide to my site without a paid plan: a budget that fails closed, a Durable Object for the heavy work, and an edge Worker near 1ms of CPU.
How I Built the SSD Atlas, a 3D M.2 Map
The design decisions, bugs and honesty rules behind an interactive 3D reference for an M.2 NVMe SSD, from the board down to a single NAND cell.
dtemp
A read-only Linux terminal tool for DDR5 and DDR4 DIMM temperatures, plus NVMe and SATA drives, with a synthetic simulate mode.
FindIO
A small terminal tool that finds the machine you just plugged in, or its BMC, by diffing network scans before and after.
PS-FU
A Linux hardware stress and telemetry harness that scores each run PASS, WARN or FAIL and leaves a hashed evidence bundle.
RAM BAM
An experimental protocol and script set for stress-testing ECC DDR5 on Linux with four existing tools while tracking EDAC error counters.
Blast Past
A fast top-down helicopter roguelite built with vanilla JavaScript and HTML5 Canvas.
Standards & Interfaces
Trace the standards, interfaces and form factors that limit a drive before its firmware runs.
The Future of Flash
Sort each direction in flash as on sale, in qualification or in research, and learn what to specify today.
The Physics of Flash
See how stored charge becomes data, and why reading it gets harder as cells become denser.
From Cell to Die
Follow cells into pages, blocks, and dies to understand how NAND is organized.
3D NAND Stacking
See how stacking layers raised density and created new problems for fabs and firmware.
The Controller
Meet the processor coordinating the host, NAND, and the firmware inside an SSD.
The Flash Translation Layer
Understand how firmware maps logical addresses to physical NAND locations.
Garbage Collection & Wear
Trace how an SSD reclaims space and distributes writes across its flash.
Error Correction & Integrity
Trace how an SSD controller finds and fixes NAND bit errors, and what failure looks like to the host.
Performance & Endurance
Connect workload, write amplification, and cell wear to real drive behavior.
IOSpeX
A Windows NVMe diagnostic utility with interchangeable ioctl and smartctl backends.
TriageIO
Enterprise SSD telemetry ingestion, normalization, and fleet reliability analysis for Windows.
Bit Drift Tracer
A Windows tool that plots host-visible file read speed against file timestamps, to show whether older data reads differently from newer data on your drive.
ioTraX
A lightweight Windows monitor that graphs live throughput, latency, IOPS and I/O size for every physical drive, with per-drive CSV logging.
Pong
A lightweight two-player Pong game, rebuilt for the browser and ready to play anywhere.
SSD Benchmarking 101, Part 3: Application and Trace-Based Tests
Move beyond synthetic scores with PCMark, 3DMark, Procyon, and hands-on tests that reveal how storage behaves under real applications.
SSD Benchmarking 101, Part 2: Synthetic Benchmark Tools
Use CrystalDiskMark, ATTO, AS SSD, and other synthetic tools with a clear understanding of their settings, results, and limitations.
SSD Benchmarking 101, Part 1: A Repeatable Test Method
Build a repeatable SSD test method: control the host, precondition the drive, and understand cache behavior, queue depth, and workload mix.
The Visionary of PCIe 5.0
A reflection on PCIe Gen5 validation, where cooling, sustained workloads, and controller limits complicate the promise of higher bandwidth.
From Guru to Guide
How my forum guides turned into Flash Foundations, SSD Benchmarking 101 and the tools on this site.
Full Circle
A personal essay on how lost saves, college and years at the bench shaped my care for reliability in storage.
T‑Minus 72 Hours
Inside the 72 hours before a major SSD launch: a Friday delivery, a Monday embargo, repeatable measurements, and the work behind a defensible review.
Field Practicalities
What happened when Crucial swapped the P2’s flash without changing its name, and why one review is only a snapshot of one sample.
The Lens and the Logic
How photography, a failed memory card, and the demands of creative work shaped an approach to storage testing and technical communication.
The Origin of Purpose
How a teenage repair business, competitive gaming, forum guides and years of reviewing led me to test storage the way I do.
The Quarch Chronicles
Why I measure power alongside performance, and what the numbers show about a drive that speed charts hide.
The SSD Guru’s Midnight Benchmark
A late-night account of benchmark reruns, thermal questions, and the pressure to turn a new SSD into a clear review before an embargo lifts.
The “Torture Test” Architect
How I test sustained writes, cache recovery and heat, and why a short benchmark can hide what a long one shows.
The “All-at-Once” Failure
A 24-drive RAID 0 experiment exposes a synchronized failure that individual-drive tests missed, and challenges what validation should cover.
The Wild West of Storage
A reflection on the trade shows, benchmarks, mentors, and moments that shaped a career in storage journalism.