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    Technical guide

    Beyond NAND

    The memories that keep data without power, other than NAND: how each cell stores a bit, what ships, and what each could replace.

    A series on the non-volatile memories beside NAND flash, in five parts. Part 1 covers NOR flash and the memory built onto the processor die. Part 2 covers phase-change memory and Optane, Part 3 MRAM, Part 4 ferroelectric memory, and Part 5 resistive memory and computing in the crossbar. The memory map places them in the memory hierarchy first. SRAM, DRAM and HBM are in Working Memory, and the memories built for SI in Memory and Storage for SI. Where a guide leans on the basics, it links the Flash Foundations part that teaches them.

    The series

    Read in order

    Each part builds on the one before, so start with Part 1.

    Beyond NAND, Part 1: a NOR cell with a bitline contact, a clocked flash access with wait states, and grade bars under a reflow peakA three-panel schematic. Left: a transistor with a floating gate in copper and a contact rising from the drain to a bitline. Center: a square clock wave above a row of boxes, the first four dashed as wait states and the last one solid in copper. Right: three bars of growing width for the temperature grades and a copper curve that ramps up to a peak above them.GUIDE / BEYOND NAND, PART 1Code memory that runs in placeNOR · EXECUTE IN PLACE · THE DIE01 CELLA contact per cell02 ACCESSWaits, then data03 LADDERReflow tops gradesNOR AND MEMORY ON THE PROCESSOR DIE

    Part 1

    NOR and Memory on the Processor Die

    How NOR differs from NAND, how a processor runs code in place, why embedded flash stopped fitting near 28nm, and what soldering and cars demand.

    Read Part 1
    Beyond NAND, Part 2: a phase-change cell, a cross-point stack, and an access-time scaleA three-panel schematic with no numbers. Left: a chalcogenide cell over a heater, with a tall short pulse and a long low pulse. Center: a cross-point stack of bit lines, memory elements and copper selectors. Right: a log axis with three marks from a short access to a long one.GUIDE / BEYOND NAND, PART 2Cell, stack, access timeSET · STACK · LOG AXIS01 CELLSET and RESET02 STACKMemory and selector03 ACCESSDRAM to TLC

    Part 2

    Phase-Change Memory and Optane

    How a phase-change cell stores a bit, what limits it, who built it, what 3D XPoint and Optane were and how they measured, why Optane ended, and what came after.

    Read Part 2
    A magnetic tunnel junction, two ways to write it and the energy barrier between its two statesA three-panel schematic. Left: a magnetic tunnel junction as a stack, with a free layer on top, a thin copper barrier and a reference layer below, an arrow in each magnetic layer. Center: two small stacks, one with a write current running vertically through it and one standing on a channel with a write current running sideways in the channel. Right: two energy wells separated by a barrier, the two stable states of the free layer.GUIDE / BEYOND NAND, PART 3A magnet, a barrier, a currentJUNCTION · WRITE · BARRIER01 JUNCTIONfree layerMgO barrierreferenceSAFParallel or opposed02 TWO WRITESSTTSOTThrough, or beside03 BARRIERPAPTwo states, one hill

    Part 3

    MRAM From Tunnel Junction to Product

    How a magnetic tunnel junction stores a bit, how current writes it by STT or SOT, what trades retention for speed, and what MRAM is sold as today.

    Read Part 3
    The polarization loop of a ferroelectric film with its two stable statesA schematic hysteresis loop: polarization on the vertical axis, applied field on the horizontal axis. Two curves, one teal and one copper, form the loop. At zero field each curve crosses the vertical axis at a different height, and those two points are the two stable states the memory stores.GUIDE / BEYOND NAND, PART 4A film that keeps its statePOLARIZATION AGAINST FIELD · SCHEMATICSTATE ONESTATE ZEROPOLARIZATIONFIELDTWO STABLE POINTS AT ZERO FIELD

    Part 4

    Ferroelectric Memory From Polarization to Product

    How polarization stores a bit, how a ferroelectric capacitor and a ferroelectric transistor differ, what wears them out, and what ships today.

    Read Part 4
    Beyond NAND, Part 5: a filament, a crossbar and its read marginA three-panel schematic. Left: a resistive memory cell, an oxide between two electrodes, with a conducting filament through the oxide and a small gap near the top where a reset broke it. Center: a crossbar of four word lines and four bit lines with the selected cell highlighted and a dashed sneak path running through three neighboring cells. Right: two bars of read margin, a short one for a bare array and a tall one for an array with a selector in every cell.GUIDE / BEYOND NAND, PART 5A filament, a grid, a sumFILAMENT · CROSSBAR · READ MARGIN01 FILAMENTFilament and gap02 CROSSBARSneak path, dashed03 READ MARGINBare against selectorBARESELECTORRESISTIVE MEMORY AND THE CROSSBAR

    Part 5

    Resistive Memory and Computing in the Crossbar

    How a resistive memory cell forms and switches, why cells disagree, why a crossbar needs a selector, and how the array multiplies and where that breaks.

    Read Part 5

    All 5 parts

    1. Part 1NOR and Memory on the Processor DiePublished
    2. Part 2Phase-Change Memory and OptanePublished
    3. Part 3MRAM From Tunnel Junction to ProductPublished
    4. Part 4Ferroelectric Memory From Polarization to ProductPublished
    5. Part 5Resistive Memory and Computing in the CrossbarPublished

    Short on time

    Start with your question

    Each card jumps to the section of a guide that answers it.

    Where the series sits

    The memory hierarchy

    The gap between DRAM and NAND is the reason every memory in these guides exists.

    Access time of each memory in the hierarchy, log scaleDRAM core: 16ns. Optane SSD, rated: 5µs. NAND chip page read: 25µs. NAND SSD, rated: 80µs. Hard drive rotation: 4.16ms. The shaded band marks the gap from about 100 nanoseconds to 1 millisecond that storage-class memory was meant to fill.storage-class gap10ns100ns1µs10µs100µs1ms10msDRAM core16nsOptane SSD, rated5µsNAND chip page read25µsNAND SSD, rated80µsHard drive rotation4.16msAccess time, log scale
    The rows measure different things: a die timing, two ratings, a chip page read and a spinning disk. Read the spacing, not the ranking. Between DRAM and NAND sits a gap of more than three orders of magnitude.

    Every row is a datasheet or rating figure, and the rows measure different things, so read the spacing and not a ranking. The memory map explains each memory and where the number comes from.

    Hands-on

    Explore alongside

    The guides link these tools where they explain something you can try yourself.

    Simulator

    Crosspoint Lab

    Try this: Read one cell, add the cells around it, and watch the sneak current take the signal, then add a selector.

    Open

    Continue on this site

    The memory map Working Memory Flash Foundations Labs