Silicon Real Estate

NAND: how to read it

A flash die is a rectangle of silicon cut from a wafer. Its area decides how many fit on one wafer, which is one of the things that sets a die’s cost, and bit density (gigabits per square millimeter) is how a maker fits more bits into the same silicon. The stage draws each die at one scale, so a box twice the size really is twice the area.

Most sources print a die’s area but not its width and height. Those dies are drawn as squares of the same area, so a shape can mislead even when the size is right. Planar and 3D dies sit on the same field, but they are different structures: a 3D die gets its capacity from stacked layers, not from smaller cells alone.

The full list of these dies, with every other figure, is on the NAND die timeline.

Left out, and why

The NAND die timeline holds 30 more dies that carry a die area. They stay out of the drawing until a saved copy of their source shows the same figure, because a die drawn to scale is a claim about its size. Their numbers are still on the timeline, each linked to where it came from.

• BiCS4 512Gb TLC (Toshiba Memory, 96 WL layers; product interface speed from a review, secondary source)
• XL-FLASH G1 128Gb SLC (96 WL layers)
• ISSCC 2021 1Tb TLC 170+ WL layers, CuA, 4-plane
• BiCS6 1Tb QLC (162 WL layers, WD/Kioxia)
• 96L QLC 1Tb (PUC)
• 192L FG 1.67Tb 5b/cell (PLC)
• 96L FG 1Tb QLC (CuA; product interface speed from a review, secondary source)
• 2nd-gen V-NAND 128Gb TLC (32 WL)
• 3rd-gen V-NAND 256Gb TLC (48 WL)
• 6th-gen V-NAND 512Gb TLC (product interface speed from a review, secondary source)
• X2-9060 128-layer TLC (Xtacking 2.0; die area, density and planes from a teardown, secondary source)
• X3-9070 1Tb TLC (Xtacking 3.0; layer count, die area and density from a teardown, secondary source)
• 64-stacked-WL 1Tb QLC (ISSCC 2018)
• 92-stacked-WL 1Tb QLC (ISSCC 2020 paper 13.1)
• 128-layer 512Gb TLC (die B37R; teardown, secondary source)
• 128-layer 512Gb TLC (single deck, die K9AHGD8U0B; teardown, secondary source)
• 1st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source)
• 32-layer 256Gb MLC (Micron and Intel) (die area from a teardown, secondary source)
• 90nm 2Gb planar NAND (JSSC 2003)
• 70nm 16Gb 4b/cell planar NAND (VLSI 2007)
• 56nm 16Gb TLC planar NAND (Li et al., ISSCC 2008)
• 56nm 16Gb MLC all-bitline NAND (ISSCC 2008)
• Sub-35nm 32Gb TLC planar NAND (ISSCC 2009)
• 48nm 32Gb TLC planar NAND (ISSCC 2009)
• 43nm 64Gb 4b/cell planar NAND (ISSCC 2009)
• 34nm 32Gb TLC planar NAND (Intel and Micron, ISSCC 2010)
• 19nm 128Gb TLC planar NAND (ISSCC 2012)
• Sub-20nm 64Gb MLC planar NAND (ISSCC 2012)
• 20nm 128Gb TLC planar NAND (ISSCC 2013) (die size and density from a Toshiba table, secondary source)
• 15nm 64Gb MLC planar NAND (ISSCC 2015)

What it will not tell you

Area is not cost. Wafer price, yield and the controller, packaging and test around the die are all missing here, and a large die is not a bad one: early planar parts were built for the process of their day. Different sources also measure a die differently, for example with or without the seal ring or the pad area, so a small gap between two dies is inside what the sources can tell apart.

Capacity is the headline figure each source prints, not usable space after spare blocks and error correction. A trend line drawn through these dies is a trend among them, not every die ever made. For a ranking, see the density ranking on the NAND die timeline.

DRAM: how to read it

A DRAM die stores one bit per cell as charge in a tiny capacitor, so its area is mostly the cell array plus the sense amplifiers and wiring around it. Teardown labs measure the finished die and publish its width, height or area, and from that and the capacity the page works out how many gigabits fit in each square millimeter.

Only one die here has a printed width and height, so it is drawn as a true rectangle; the rest are squares of their measured area. A mobile LPDDR die and a server DDR5 die are built for different jobs, so compare density across them with care.

The full list of these dies, with every other figure, is on the DRAM die timeline.

Left out, and why

These dies appear in industry slides or research notes, but this page could not read their area from a source saved in the library. A die stays off the stage until its figure is confirmed from a saved copy, so a missing box means unconfirmed, not small.

• SK hynix D1b DDR5
• Micron D1β LPDDR5
• CXMT G1, G3 and G4 DRAM dies
• Micron 1γ, SK hynix 1c and Samsung 1c, for which no area has been found

What it will not tell you

These are a handful of dies, not the market. Makers rarely print die areas, so every figure here is a teardown measurement of one part, and the same part can measure slightly differently depending on whether the seal ring is counted. The Micron Y52K entry carries both the die-seal measurement and the full-die figure in its source, and the page draws the sealed one.

Area also does not show speed, power or cost.