Memory and Storage for SI, Part 8: Where Memory Goes Next

Memory and Storage for SI started at the device, with an analog memory scored as a weight, flash changing its job and flash inside the processor package. Part 4, Storage-Next and the 512-Byte Read, came next, followed by Part 5, Context Memory: Where the KV Cache Goes, Part 6, The Capacity Drives and Part 7, The Five-Minute Rule in Microseconds, the latest part published before this one. The series page lists all of them. Working Memory and Beyond NAND covered the other families, and each part in the three series took one family or one question.

Which memory fills which job, and which of them can you order today? Nothing so far has replaced DRAM, and this part sets out why.

The roles a memory can fill

This is the last part of Memory and Storage for SI. It closes this series and places the families from all three memory series. It adds no new device and no new measurement, and it keeps what is for sale, qualifying and research apart. The memory map holds the hierarchy this part redraws, and the numbers stay there. The placements are as of October 2026.

Four jobs

A memory is hired for a job. On the processor die, or as a small part beside it, it holds code or a small state that has to survive soldering and power loss, which Beyond NAND, Part 1 follows. As main memory it holds the working set, which is DRAM’s job. Above DRAM sits the processor’s own cache, and Working Memory, Part 1 covers it. A roadmap that Beyond NAND, Part 3 cites puts spin-orbit-torque (SOT) MRAM for cache at an early stage of research. As storage-class memory it is asked to fill the gap the memory map describes, between DRAM and NAND. As capacity it is asked to hold the most data for the money, which is the job the memory map gives to NAND.

Six status words

Those jobs form no ranking, since a family can fill one and miss the others. Six status words appear in the grid, and no others. For sale means a part you can order, or a process the earlier parts describe as qualified inside someone else’s chip. Ended means it shipped and then stopped. Qualifying here means a published specification, a taped-out die or sampling to customers, before the sources show a part for sale. That is earlier than the industry sense of the word. Research means a paper, a test chip or a simulation. Open means the sources name the question and do not close it. Not this job means this series does not show that family doing that work.

Where each family lands

The “for sale” cells in the first column are coarse. Beyond NAND, Part 5 and Beyond NAND, Part 3 each keep a catalog part apart from a foundry process, and Beyond NAND, Part 4 keeps a catalog part apart from arrays built into logic processes. Figure 8.1 does not, and it also puts small standalone parts in that column. If you need the split, those sections are the ones to read.

Figure 8.1 reads by row, and the shading steps down from strongest evidence to weakest. NAND’s filled cell is capacity, and it is for sale. Its gap cell is open, because Part 2 finds flash working as memory behind DRAM only in a research system and on an emulator, and neither is a product. NOR, magnetoresistive RAM (MRAM), resistive memory and ferroelectric RAM each have a for-sale cell on the die, in the coarse sense above. For NOR that means embedded flash, which vendors report sampling and in production at the node where it stopped scaling, as Beyond NAND, Part 1 records.

Phase-change memoryPhase-change memory stores data in a material that switches between a crystalline, low-resistance state and an amorphous, high-resistance state when heated.’s (PCM’s) die cell is qualifying, because ST’s own releases, which Beyond NAND, Part 2 follows, describe embedded PCM in automotive microcontrollers: samples to customers, a first part announced in 2021, and a later process with production planned. None of that is a part Beyond NAND, Part 2 shows for sale. PCM’s and resistive memory’s gap cells are open. Micron’s paper, quoted in Working Memory, Part 3, says their latency limits them to storage-class memory. That is one vendor’s reading, not a product. Resistive memory’s capacity cell is research, because the large chips the memory map weighs against NAND are not a product, and Beyond NAND, Part 5 keeps its largest target a goal.

MRAM is for sale in the gap in a small form, as a persistent buffer inside a flash module, and Beyond NAND, Part 3 places that part between DRAM and NAND. MRAM’s main-memory cell is research, because the roadmap in Beyond NAND, Part 3 calls DRAM-density MRAM an open area for research. Ferroelectric memory has two research cells. Its main-memory cell is research, because the large array in Beyond NAND, Part 4 comes from a paper and has no catalog part behind it. Its capacity cell is research, because the ferroelectric NAND strings in Beyond NAND, Part 4 are papers.

DRAM is for sale as main memory. That cell is the highlighted one, because no other row takes the job. High Bandwidth Memory (HBM) is that same job done as a stack of DRAM dies beside the processor, so it is not a row of its own. Optane is the row that ended, and it ended twice. It ended in the gap as a drive, and it ended as main memory, where its modules ran in DDR4 slots with DRAM as their cache, as Beyond NAND, Part 2 describes. High Bandwidth Flash (HBF) is qualifying, and only in the capacity column, which is the point of Part 2. Sandisk’s own simulation in that part puts it in the place of HBM, and a vendor simulation does not give it a main-memory cell.

A part for sale on the die does not make a family a DRAM replacement, and a paper that aims at DRAM is not a part for sale.

Picture one humanoid robot with ferroelectric RAM at the joints and the battery controller, NOR for boot code, and DRAM and an NVMe drive for the models. Beyond NAND, Part 4 works through the joint as a test of the datasheets, and the other jobs stay with the families that already fill them.

What is for sale, qualifying and research

Beyond NAND, Part 5 and the MRAM part sort their evidence into three lanes. One is a part you can order, one is a process qualified for someone else’s chip, and one is a demonstration. Beyond NAND, Part 4 has three lanes too, but its middle one holds arrays built into logic processes, and those are demonstrations. Here the first two lanes fold into one, and two more are added that those parts did not need: qualifying for High Bandwidth Flash and embedded PCM, and ended for Optane.

What is for sale

NAND, NOR and DRAM are the memories computers already buy for capacity, code and working data. Beside them, the emerging families that have a product are the small kind, or they live inside another chip.

Resistive memory’s orderable parts are serial memories and microcontrollers, and its volume is in qualified processes on logic dies. Beyond NAND, Part 5 separates those from the conference chips. MRAM is sold as embedded code memory and as a persistent buffer, which Beyond NAND, Part 3 covers, and the fast read numbers in that part come from macros and test chips, which are not parts you can order. Ferroelectric RAM (FeRAM) is in the catalog as small serial and parallel parts and microcontrollers, which Beyond NAND, Part 4 covers.

PCM is the family that was sold once, and one vendor still announces it. Beyond NAND, Part 2 records a small parallel part and a phone memory package. It does not say either is still sold, or which job either filled, so neither has a cell in Figure 8.1, and PCM is not in the order lane of Figure 8.2. PCM lives on today as embedded PCM in ST’s automotive microcontrollers, which Beyond NAND, Part 2 follows through the 2021 first parts and the 2024 and 2025 announcements. Those are releases, and the production schedule in them is ST’s plan, so embedded PCM sits in the qualifying lane.

What is qualifying, and what ended

High Bandwidth Flash is the first qualifying row. Part 2 records a published draft specification and a die Sandisk says has taped out, and cites no statement that any sample had reached a customer.

Embedded PCM is the second. Beyond NAND, Part 2 records ST’s microcontrollers with embedded PCM, samples to alpha customers and a production plan, and none is shown on sale.

Optane is the other special case. It was sold, and it ended. Beyond NAND, Part 2 tells that story. Optane does not belong in the research lane, and it does not belong among the parts you can still order. Its ending is a fact about the product and does not rule out the physics.

What is still research

Research is the long lane, and it lists claims instead of families. A family can have a part for sale and still have a research claim beside it.

Working Memory, Part 3 finds no DRAM replacement on sale among its five candidates. They are the vertical-channel cell, stacked DRAM, the capacitorless cell, the oxide-channel cell that keeps a capacitor, and Micron’s ferroelectric nonvolatile DRAM (NVDRAM). Most of its stacking evidence is reported through the trade press or stated as a roadmap instead of coming from a paper. Beyond NAND, Part 3 leaves DRAM-density MRAM as an open research area, so the lane says DRAM-density MRAM and not MRAM. Beyond NAND, Part 5 puts the large resistive chips in the same research lane as the conference parts. Next to it sits a product line that is real and small.

Part 1 finds in-place training on analog memory only in simulations, a mixed phase-change and capacitor design, a spiking-network experiment and small arrays. Research chips built at scale run inference with weights programmed in advance. That part finds no product that holds its weights in a new memory with an independent measurement behind it. There is one commercial flash-based claim, and it is a vendor claim, as its vendor section says. Analog weights are a use rather than a tier, and they fill no cell in Figure 8.1, because no source shows them taking a job away from the memories that hold it.

Figure 8.2 puts each name in one primary lane. You can order NAND, NOR, DRAM, MRAM, resistive memory and FeRAM, in the forms the earlier parts describe, which for several of them means small or embedded. Qualifying holds HBF and embedded PCM. Ended holds Optane. Research holds DRAM-density MRAM, large resistive chips, capacitorless DRAM, stacked DRAM, NVDRAM and analog weights. PCM’s past parts sit in no lane, for the reason above.

Figure 8.2 does not collapse a family into one fate. MRAM is for sale, and DRAM-density MRAM stays research. Resistive memory is for sale in small forms, and the large chips stay research. Read each lane as the product question. Can you order it, is it qualifying, did it end, or is this particular claim still research?

Why nothing has replaced DRAM

The memory map already states the result. Nothing in its sources matched DRAM’s mix of speed, endurance and cost. Later parts leave that result standing and say what each family lost. Working Memory, Part 2 covers the cell from the inside, and Working Memory, Part 3 adds that the DRAM cell itself is hard to shrink.

Optane gave up DRAM’s speed on the memory bus, which Beyond NAND, Part 2 measures, and then it ended. Phase-change arrays, in Burr’s review that the memory map cites, fall short of what DRAM replacement would need without wear levelingWear leveling spreads erases evenly over all blocks. Dynamic leveling picks young blocks for new writes, while static leveling also moves cold data off them.. One review made that judgment, and it carries no measurement.

MRAM’s standalone parts and its embedded macros are not the same measurement. Beyond NAND, Part 3 refuses to turn that pair into a ratio, and its density section says a DRAM die still holds more. As that section cites it, the 2022 IEEE roadmap still lists DRAM-density MRAM as open research. A fast macro is not a main-memory product.

FeRAM spends a cycle on the read, because the read is destructive and has to be written back, which Beyond NAND, Part 4 explains. Its parts for sale stay the small kind. Hafnia arrays and the NVDRAM paper are demonstrations, and the arrays section says none of those sources calls one a product on sale.

Resistive memory has been held back in large arrays by switching currents, as the memory map puts it. Beyond NAND, Part 5 ends with it on the logic die, where it replaces neither NAND nor DRAM. Computing in the crossbar is further back. The arrays work, and the converters and device faults still decide the answer.

Working Memory, Part 3 is where the cells that would keep DRAM’s job are set side by side. None of them is described there as a replacement on sale. That part also quotes Micron’s IEDM 2023 NVDRAM paper, which says “none of the studied technologies can directly replace DRAM from a product standpoint.” That view belongs to one vendor and its own device, and this part does not promote it into a law.

Figure 8.3 is the memory map’s hierarchy with the access times left in that part, and with only the families that hold a place in it, or once did. Its processor cache is marked as held by SRAM, and the hard drive is drawn but not placed. DRAM is in place, and it is marked unmatched. NAND is for sale as capacity. Highlighting marks the gap row, and it is drawn dashed because it has no large resident. Optane is named beside it as ended, and the MRAM buffer is named as the small part for sale there.

Research stays off the figure. DRAM-density MRAM, capacitorless DRAM, stacked DRAM and NVDRAM are claims in the section above and get no box in this figure. A part for sale on the processor die does not put a family in the gap either. Figure 8.1 already gave that different job a column. MRAM is named beside the gap for its buffer, and its embedded macros are left out.

Where flash holds, and where it changes job

NAND’s hold is cost per bit. The memory map puts Optane, phase-change and MRAM against it and finds that each can win on speed or endurance and still lose where cost per bit decides. No dollar figure appears here, because the section on why NAND is cheap cites no primary source for one.

That same section holds the structural reasons. NAND has one transistor per cell and vertical strings that share contacts. Its stack is built in bulk, and it holds several bits per cellA cell storing n bits needs 2 to the power n voltage levels: two for SLC, four for MLC, eight for TLC and sixteen for QLC.. Any memory that wants the capacity job has to beat that, or take a job where cost per bit matters less. Families with parts for sale on the die took the second path.

Part 2 is the exception, and it is not a replacement. High Bandwidth Flash does not try to beat NAND on speed or on write endurance. It uses NAND because of how much one die holds. It accepts slow reads and answers them with width. Weak writes are accepted too, and the answer is data that is written once, read many times. Short retention is accepted as well, and the host does refresh. Capacity is changing jobs here and moving beside the accelerator, with no new cell taking NAND’s old job away.

Weaknesses stay in view on purpose. A job change that hides the write limit, the wear limit or the retention limit gives no account of the part. Part 2 is where those limits are spelled out, and Figure 8.4 keeps the write and retention limits in view.

Flash Foundations ends on the same boundary from the flash side: firmware, zoned namespacesZoned Namespaces split the drive into zones that must be written in order, which moves data placement to the host and removes most garbage collection., Compute Express LinkCXL runs over the same physical layer as PCIe but adds cache-coherent memory access, so it moves cache lines rather than blocks of storage. (CXL) and the host change how NAND is used, and none of them changes the cell. Both series meet at High Bandwidth Flash.

Figure 8.4 sets the two jobs side by side. Its left panel shows why NAND holds capacity, through cost per bit, vertical strings, shared contacts, and several bits per cell. Its right panel shows what HBF accepts from that same NAND, and its answer to each limit. That panel is highlighted because it is the one job change in this series, and it is still qualifying. Sandisk’s own simulation in Part 2 is not a sample, and that section says the equal bandwidth was an input and never a finding.

What would change the answer

Placements change only when the evidence does. Three questions cover it, and the earlier parts already ask them.

Start with whether you can buy the part and measure it. A paper, a roadmap line or a simulation is a no. DRAM-density MRAM, the capacitorless and stacked DRAM cells, NVDRAM and High Bandwidth Flash stand there today, and the thing to watch is a sample instead of a slide.

If you can buy it, the second question is whether it matches DRAM on speed, endurance and cost together. If it does, the hierarchy changes and this page is out of date.

If it does not, the last question is whether it is flash taking a new job. High Bandwidth Flash would land there once it samples. Anything else keeps a smaller job, on the die or as a buffer, where MRAM, resistive memory and FeRAM already are, and where PCM was once sold as a small parallel part and a phone memory package. A better paper does not move them into DRAM’s place.

Figure 8.5 is those three questions, with buying first. No on the first leads to “Watch samples, not slides.” Yes on the first and yes on the second is the highlighted leaf, “The hierarchy changes.” Yes, then no, then yes on the third is “Flash changes job.” Yes, then no twice is “It keeps a smaller job.”

Only a few things would count. They are DRAM-density MRAM sold as a product, a vertical-channel, stacked, capacitorless or oxide-channel DRAM you can order, NVDRAM in a catalog, or an HBF sample measured outside a simulation. Until one of those exists, the grid stands. Analog weights move this page only if they take one of the four jobs, which Part 1 does not show.

Reading the series

The map below is the order to read the evidence in, and the memory map comes first.

Figure 8.6 draws the memory map and the three series, each part with what it owns, and marks this one. The memory map is the hierarchy and a first look at each family. Working Memory follows the memory a processor works from. It starts with the SRAM cell and the cache and the DRAM cell from the inside, then covers what could follow that cell. The HBM stack sits beside the processor, and then come the DRAM parts for sale today and the CAMM2 modules. Beyond NAND follows the non-volatile memory beside flash. Its parts are NOR and execute in place and phase change and Optane, then MRAM, ferroelectric memory and the resistive cell. This series starts with an analog memory scored as a weight, flash changing its job and flash inside the processor package, then moves out to the 512-byte read, the KV cache, the capacity drives and the five-minute rule. The series page lists them, and the Memory and Storage Hierarchy sets the memories side by side on five axes.

Two things are worth watching. One is a High Bandwidth Flash sample measured outside a simulation, and the other is a DRAM-density MRAM part you can order. Either would move a placement on this page. Until one exists, the placements stand as of October 2026.