Eyes on Flash/ Driven by Insight
Contact

Search Eyes on Flash

Tip: press / or Ctrl+K on any page to open search.

Type to search.

    Learn

    Guides

    Series that teach a topic in order, the memory map that ties the memory series together, and myths checked against data.

    A series is read in order, part by part, and each part also stands on its own. The memory map shows where every kind of memory sits and which series covers it. The myths take one claim at a time and give a verdict. Posts about how I test and build things are on the blog.

    Read in order

    Series

    Each series starts at Part 1 and builds on the part before. The memory map shows which memory series covers what.

    Flash Foundations, Part 1: a host and a drive joined by per-core queues, four link generations each twice the last, and an M.2 card beside an E3.S cardA three-panel schematic. Left: a host box above a drive box, joined by five columns of queue slots, one queue per core. Center: four bars rising in doubling steps for PCIe Gen3, Gen4, Gen5 and Gen6, the last in copper. Right: an M.2 card above a larger E3.S card, drawn at one scale, each with gold contact fingers on its left edge.GUIDE / FLASH FOUNDATIONS, PART 1Limits set before the firmware runsPROTOCOL · LINK · PACKAGE01 PROTOCOLHostDrive02 LINKGen3Gen4Gen5Gen603 PACKAGEM.2E3.S

    10 parts

    Flash Foundations

    How an SSD works, from the physics of a flash cell to the controller, the translation layer and error correction.

    Start the series
    Working Memory, Part 1: a six-transistor SRAM cell, three cache levels, and a die stacked on a dieA three-panel schematic. Left: a six-transistor SRAM cell between two bitlines, with a wordline above it. Center: three horizontal bars of growing width for the cache levels, the shortest in copper. Right: a logic die with a smaller cache die stacked on top of it and a row of bonds between them.GUIDE / WORKING MEMORY, PART 1The memory inside the processorCELL · LEVELS · STACKED DIE01 CELLSix transistors02 LEVELSLarger and slower03 STACKA second die on topL1L2L3SRAM AND THE PROCESSOR CACHE

    7 parts

    Working Memory

    The memory a processor works from: SRAM and the cache, DRAM from the inside, what could follow DRAM, and the HBM stack.

    Start the series
    Beyond NAND, Part 1: a NOR cell with a bitline contact, a clocked flash access with wait states, and grade bars under a reflow peakA three-panel schematic. Left: a transistor with a floating gate in copper and a contact rising from the drain to a bitline. Center: a square clock wave above a row of boxes, the first four dashed as wait states and the last one solid in copper. Right: three bars of growing width for the temperature grades and a copper curve that ramps up to a peak above them.GUIDE / BEYOND NAND, PART 1Code memory that runs in placeNOR · EXECUTE IN PLACE · THE DIE01 CELLA contact per cell02 ACCESSWaits, then data03 LADDERReflow tops gradesNOR AND MEMORY ON THE PROCESSOR DIE

    5 parts

    Beyond NAND

    The non-volatile memories beside flash: NOR and on-die memory, phase-change memory and Optane, MRAM, ferroelectric and resistive memory.

    Start the series
    Memory and Storage for SI, Part 1: a weight as two conductances, a staircase of update steps and a spread around a targetA three-panel schematic. Left: two vertical bars of different heights with a copper bracket between their tops, a weight stored as the difference of two conductances. Center: a conductance staircase that rises in equal steps and falls in equal steps, with the pulses drawn as ticks beneath. Right: a bell-shaped spread of conductances around a dashed target line.GUIDE / MEMORY AND STORAGE FOR SI, PART 1A weight, a step, a spreadWEIGHT · UPDATE · SPREAD01 WEIGHTG+G−Two cells,one weight02 UPDATESmall steps,up and down03 SPREADtargetMisses land arounda target

    8 parts

    Memory and Storage for SI

    Memory and storage built for SI, from a memory cell used as a weight to high bandwidth flash and the drives made for inference.

    Start the series
    NVMe over Fabrics: a local SSD on a short PCIe link, the same SSD reached across a switch with capsules on the wire, and many senders converging on one receiverA three-panel schematic. Left: a host chip sits directly above an SSD, joined by one short copper link. Center: a host on the left and a storage box with SSDs on the right sit on either side of a network switch, and small teal capsules travel along the copper link between them. Right: four sender boxes on the left send copper lines into one switch, which feeds a single receiver box on the right.GUIDE / NETWORKING FOR SI, PART 1NVMe across the networkLOCAL · FABRIC · INCAST01 LOCAL02 FABRIC03 INCASTHOSTSSDHOSTcapsulesSSDsswitchmany to one

    5 parts

    Networking for SI

    The networks that carry storage traffic for SI clusters, starting with NVMe over Fabrics.

    Start the series
    The memory and storage hierarchy: bandwidth from a hard drive to one GPU’s HBM, the five-minute rule from 1987 to 2017, and one SSD’s write speed through its phasesA three-panel schematic. Left: two bars on a log scale, a hard drive at 270MB/s and one GPU’s HBM at 19.2TB/s, the HBM bar far longer. Center: a line of the DRAM to hard drive break-even interval from 400 seconds in 1987 to 4 hours in 2017 on a log scale, with a dashed line at five minutes. Right: a line of one SSD’s write speed against data written, high while the cache absorbs writes, then a slower phase, then a steady middle speed.GUIDE / HOW STORAGE WORKS, PART 1Every memory wins on one axisBANDWIDTH · FIVE-MINUTE RULE · WRITE SPEED01 BANDWIDTHHDD 270MB/sHBM 19.2TB/slog scale02 BREAK-EVEN5 min400s4h1987201703 WRITE SPEEDcache, fold, then TLC

    4 of 8 parts published

    How Storage Works

    What is inside drives and the links and protections around them, starting with the memory and storage hierarchy.

    Start the series
    Two DDR5 modules seated in slots A2 and B2 of a four-slot motherboardTop view of a motherboard's four memory slots, labeled A1 and A2 for channel A and B1 and B2 for channel B. Two DDR5 modules, each with eight memory chips, sit in A2 and B2; A1 and B1 are empty.GUIDE / STORAGE AND MEMORY IN PRACTICE, PART 1Two modules, four slotsTOP VIEW · NOT TO SCALEA1A2B1B2CH ACH B

    7 of 8 parts published

    Storage and Memory in Practice

    Choosing, setting up and keeping drives and memory in real machines, starting with DDR5 for builders.

    Start the series
    Three views of NAS operating systems: software inside a maker's box, hardware and software picked apart, and a support bar that endsThree numbered panels. First, the box: a NAS case with four drive bays and a software layer drawn inside it. Second, the build: a hardware block with a separate software block above it and a gap between them. Third, the updates: a bar that is solid while updates last and dashed where support ends.GUIDE / RUNNING A NAS, PART 1The software that runs a NASBOX · BUILD · UPDATES01 THE BOXSoftware inside02 THE BUILDYou pick both03 THE UPDATESSupport can end

    9 parts

    Running a NAS

    The software and setup side of a NAS, from the operating system and pools to the network, backup and the faults owners find too late.

    Start the series
    Tokens going through trained weights to the next tokenThree word tokens on the left feed into a large grid of shaded cells, the model's trained weights, with one row lit up as the token selects it. An arrow on the right leads to the next token the model writes.GUIDE / UNDERSTANDING SI, PART 1Tokens in, the next token outTOKENS · TRAINED WEIGHTS · NEXT TOKENTOKENSTRAINED WEIGHTSNEXT

    3 parts

    Understanding SI

    SI itself: what a language model knows, running one on Windows, and the agents built on one.

    Start the series

    7 parts

    Benchmarking

    How to test an SSD so the number holds up: a repeatable client method in 101, then enterprise drives at steady state in 201.

    Start the series

    Before a series

    Start here

    Every kind of memory on one page, with the series that covers it.

    The memory map: the access-time ladder, Optane write behavior and the four candidate memoriesA three-panel schematic. Left: access times for DRAM, Optane, NAND and a hard drive, from 16 nanoseconds to 4.16 milliseconds, as bars of schematic length. Center: an Optane drive holding a flat write rate of 6.1 gigabytes per second while a NAND drive falls to between 0.4 and 0.5. Right: the four candidate memories, phase-change, MRAM, resistive and ferroelectric, each with the property that stores its bit.GUIDE / THE MEMORY MAPFast is not enoughHIERARCHY · OPTANE · CANDIDATES01 HIERARCHYDRAM16nsOptane5µsNAND25µsHard drive4.16msBars are schematic02 OPTANE015 minOptane held6.1GB/sNAND fell to0.4GB/s to 0.5GB/s03 CANDIDATESPhase-changeresistanceMRAMmagnetizationResistivefilamentFerroelectricpolarization

    The memory map

    The Memory Map: What Comes After Flash

    Where NAND flash sits in the memory hierarchy, what Optane proved and why it ended, and what phase-change, MRAM, resistive and ferroelectric memory could add.

    Checked against data

    Myths and glossary

    Continue on this site

    Atlas Labs Timelines