A Full SSD Weighs More Than an Empty One

A full SSD holds the same number of electrons as an empty one. A YouTube short by mryeester says the drive full of photos outweighs an identical empty one by the mass of the electrons that store the data, and that reason is wrong. A full drive can still be heavier or lighter, by about a billionth of a billionth of a gram per terabyte, and which way it goes depends on the chip. Programming only moves electrons around inside the package, so the drive stays neutral and gains no electron mass. Energy stored in the cells can change the weight, and its size and sign depend on the chip.

Writing changes the energy stored in the cells, and energy has mass. How big that change is takes two numbers from patents and one line of physics. Which way it goes needs a fact makers do not publish. That fact is the threshold a cell drifts toward when it is left alone. What three papers say about the neutral level, and one retention trend, point low enough that a full drive comes out heavier. One study of Micron-supplied research chips, and one patent design, point high enough that a full drive comes out lighter.

The electrons were already in the chip

The short draws the write as channel hot-electron injection, which is how NOR flash programs. NAND programs by tunneling, which Flash Foundations Part 2 covers. With either one, programming moves electrons from the channel onto the storage node and erasing moves them back, all inside the package.

Kish and Granqvist write that the electron mass plays no part in these memories because they work with charge neutrality, so the electron count does not change with what is stored. A drive that had gained electrons would carry a net charge, and an SSD carries none.

In Figure 1 the erased and programmed panels hold the same three electrons. Energy stored in the cell is what changes. Charge held on a storage node away from the cell’s resting threshold holds electrostatic energy. By E = mc² that energy has mass, enough to make a full drive heavier or lighter depending on where the resting threshold sits.

How much would a full drive gain?

Two sourced numbers size it. In the NAND flash patent US8179720, one electron on 20nm floating-gate flash moves the threshold by about 5mV to 20mV. US6347053 gives an example window with the erased cell at 2V and the highest programmed cell at 6V. I spread eight TLC levels evenly across that 4V window, which is my model choice, so each level step is about 0.57V.

A cell whose threshold sits D volts from its resting point holds this much energy:

E = e × D² / (2v)

Here e is the electron charge in coulombs, D is in volts, and v is the volts per electron. I turn that energy into mass with E = mc².

For 1TB of user capacity at three bits per cell there are 2.67 × 10¹² cells. A full drive spreads data evenly over the levels, so on average each cell holds half the window more charge than an erased cell. That is 100 electrons per cell at 20mV per electron and 400 at 5mV. Count those moved electrons as added rest mass, using the 2022 CODATA electron mass of 9.1093837139 × 10⁻³¹kg, and you get 2.43 × 10⁻¹³g to 9.72 × 10⁻¹³g per terabyte, the number the short’s reasoning gives.

In Figure 2 the copper bars are the short’s number and the teal bars are the largest difference the stored energy allows, on a log scale. The largest the stored-energy difference can be, with the resting point anywhere in the window, is 1.22 × 10⁻¹⁸g at 20mV per electron and 4.89 × 10⁻¹⁸g at 5mV, both with the resting point at the top level. A gram is more than 10¹⁷ times that. The short overstates the effect by about five orders of magnitude.

The crossover: where full stops being heavier

Empty here means every cell is erased, as after a full erase. Micron’s NAND primer, technical note TN-29-19, says erasing a block sets all bits to 1 and every byte to FFh, and programming can only change 1s to 0s. Full means every cell holds scrambled data, so all eight TLC levels, L0 to L7, are equally common.

In my model a cell’s stored energy grows with the square of its threshold’s distance from a center point. For the charge alone, that center is the neutral threshold, where the storage node holds no net charge. A real cell adds a term that is linear in the stored charge, and a square plus a linear term is the same square around a shifted point. So the center for mass is the minimum-energy state, the threshold a cell drifts toward when left alone. That reading is mine, and it ignores entropy and assumes the drift heads for the true minimum.

With evenly spaced levels the answer turns on one number, n, the center’s height in level steps above the erased level. For N levels, a full drive minus an empty one stores this much energy per cell, in units of one level step squared:

(N − 1)(2N − 1) / 6 − (N − 1) × n

The difference is a straight line in n, and it crosses zero at n = (2N − 1) / 6. For TLC that is 2.5 steps, halfway between L2 and L3. For MLC it is 1.17 steps, just above L1. For QLC it is 5.17 steps. A center left of the crossover makes a full drive heavier, and one right of it makes a full drive lighter.

Figure 3 draws the TLC line at both ends of the sourced millivolt range. With the center at the erased level the full drive is 6.79 × 10⁻¹⁹g heavier at 20mV and 2.72 × 10⁻¹⁸g heavier at 5mV. With the center at L1 it is 4.07 × 10⁻¹⁹g and 1.63 × 10⁻¹⁸g heavier. A center in the middle of the window, the same distance from the erased level and the top level, flips the sign, because a full TLC drive then stores 3/7 of the erased drive’s energy. Uneven spacing moves the crossover, but with every level inside the window the difference cannot pass 1.90 × 10⁻¹⁸g at 20mV or 7.62 × 10⁻¹⁸g at 5mV. With any spacing, a full drive is heavier when the center sits below the average of x² divided by twice the average of x, where x is a level’s distance above the erased level.

Where the sources put the resting point

No source I hold gives the center in volts next to real level placements. Luo and colleagues say why. They show normalized voltages because the real values are proprietary to the flash vendor. Papers do give three authors’ statements about where the neutral level sits, each their reading of their own data, and one retention trend that I read myself. I use the neutral level as a stand-in for the center, and label each statement by what it is.

Four that point heavier

Luo and colleagues measured 3D charge-trap MLC flash in retention. Over time the P1, P2, and P3 cells (their names for the three programmed MLC levels) lose voltage while the erased cells gain it, because, they write, the erased cells have negative threshold voltages. My reading is that the cells settle just above the erased level and under P1, below the MLC crossover of 1.17 steps. That is a retention trend, not a measurement of the center.

Chen and colleagues irradiated an SK hynix 128Gb 3D NAND part and found the all-ones FF pattern barely sensitive. From that they infer the erased distribution may sit at or near the neutral level. An erased level at the center puts every programmed level above it, which favors a heavier full drive.

Kumar and colleagues, on a 64-layer 3D floating-gate TLC part, believe the neutral level is below L1, because irradiation shifted the L1 distribution downward. That also favors heavier.

Gerardin and colleagues describe the neutral distribution of 45nm NOR floating-gate memories as typically placed between the erased level and the lowest program level. Those parts are planar flash, where that placement favors heavier for MLC and does not decide the sign for SLC.

Each bar in Figure 4 is the span a source allows, on the TLC scale, against the dashed crossover at 2.5 steps. The four on the left sit wholly below it. The patent span and the Bagatin point sit right of it.

Two that point lighter

The first is a design rule in a patent. US6347053 sets the neutral threshold to the mean of the erased and highest programmed thresholds, and its example puts a neutral cell at 3.5V to 4.5V. On my eight-level mapping that is 2.6 to 4.4 steps, past the crossover, so a part built that way would come out lighter.

The second is a study by Bagatin and colleagues of charge-trap replacement-gate research chips, which their earlier paper says Micron supplied. Under X-rays, TLC cells at L3 kept their threshold almost unchanged while L0 to L2 rose and L4 to L7 fell, so the window closed toward L3. The authors give two readings, the neutral level at L3 or a near-perfect balance of charge loss and trapping, and say that given the cell features they expect it close to L3. It is the only source I hold that names a level for these cells, as the authors’ expectation rather than a measurement. Kumar’s comparison of the two cell types also notes the distinct neutral position in charge-trap cells.

L3 is 3 steps above the erased level, past the TLC crossover of 2.5, so a full drive of these parts would come out lighter. The neutral level would have to sit more than half a step below L3 to flip that. If the other levels keep their spacing, a wider erased-to-L1 gap doesn’t change it in my arithmetic, because it moves the crossover up by less than it moves L3. Refaldi and colleagues erased 3D NAND test cells well below their neutral state, which shows erase can overshoot, but it doesn’t place the programmed levels and doesn’t move the sign.

Luo and Chen studied charge-trap parts too, and they point heavier, so the split follows the chip and the kind of evidence more than the cell type.

What would settle it

No maker publishes where it places its levels, so the sign for any drive you can buy is unknown, and a design that centers its window, as US6347053 describes, would be lighter. The paper that would settle it measures the neutral level in volts beside the real level placements of a current charge-trap TLC or QLC part, from one maker, and says which part it is. Radiation studies like Bagatin’s come closest, because they watch each level move toward the neutral point, so the next one on another maker’s replacement-gate parts is the thing to read. QLC follows the same rule as TLC does. Its crossover at 5.17 of 15 steps sits about a third of the way up the window, as TLC’s and MLC’s do, so a centered QLC window would come out lighter too.

Figure 5 draws the three windows to one width, with each crossover dashed and the middle of the window solid.

On a real drive the neutral level matters for retention, because the drift Luo and colleagues measured, erased cells rising and programmed ones falling, is the early retention loss their paper sets out to tolerate. How full to keep a drive is a question about space and wear, which the empty-space myth covers.

I think the short’s answer could even be right for some chips, though never for its reason. If I had to bet on a drive bought today, I’d lean lighter. Bagatin and colleagues write that most 3D NAND on the market uses replacement gate, and they expect the neutral level of their Micron-supplied test cells near L3. That bet stretches one team’s expectation for their own cells to other makers’ parts, and two charge-trap papers point the other way, so I’d hold it loosely.