Beyond NAND, Part 3: MRAM From Tunnel Junction to Product

Part 2 followed phase-change memory from the Optane drive that answered a small read far faster than NAND to the heat sensitivity that decided where the cell was sold. Part 1 covered NOR and why embedded flash stopped fitting on the processor die. The memory map gave MRAMMRAM stores each bit as the magnetic state of a magnetic tunnel junction and reads it by sensing the junction’s resistance. The magnets hold their state without power. one section and a verdict. It keeps finding jobs where cost per bit matters less than speed, endurance or surviving a power cut. This part is the account behind that verdict.

The question is how a magnetic bit is stored and written, what trades retention for speed, and where MRAM is sold today. A reader who finishes it can read an MRAM datasheet line, tell toggle, spin-transfer torque and spin-orbit torque writing apart, and sort an announcement into a part you could order, a process qualified for other companies’ chips, or a research result. Every number comes from a datasheet, a vendor release, a paper’s abstract or the IEEE roadmap, and the sentence names which. Other parts are on the series page.

The tunnel junction

Two magnets and a barrier

A magnetic tunnel junction (MTJ)A magnetic tunnel junction is two thin magnets with an insulating barrier between them. One is fixed and the other can flip, and their alignment sets the junction’s resistance. is two nanomagnets separated by a thin insulating barrier. One is pinned and serves as the reference, and the other is free. Whether the two point the same way or opposite ways is the bit, and tunnel magnetoresistance (TMR) lets that be read as a resistance (Krizakova and colleagues). Parallel is the low-resistance stateThe low-resistance state is the resistive cell state that passes current easily, and it usually stores a one. and antiparallel is the high one. Their TMR ratio is the resistance change between them, as a percentage of the low value.

Typical modern stacks are a free layer, a magnesium-oxide (MgO) barrier, a reference layer and a synthetic antiferromagnet that holds the reference in place. Cobalt-iron-boron (CoFeB) layers against crystalline MgO give a TMR ratio of 100 to 250% at room temperature in standard devices, and the same review says no better material compatible with industrial requirements has been found.

Why MgO

Barrier material is the reason the numbers got useful. Junctions with an aluminum-oxide barrier reached a TMR ratio of up to 70% at room temperature, a figure from the papers’ abstracts. Single-crystal Fe/MgO/Fe junctions reached up to 180% through coherent spin-polarized tunneling (Yuasa and colleagues). Sputtered polycrystalline junctions with an oriented MgO barrier and cobalt-iron electrodes then showed about 220% at room temperature and about 300% at low temperature, stable to 400°C (Parkin and colleagues).

Two later results matter for memory. A perpendicular CoFeB and MgO junction showed a TMR ratio over 120%, high thermal stability at a diameter as low as 40nm, and a switching current of 49µA (Ikeda and colleagues). And a pseudo-spin-valve junction annealed at 525°C reached 604% at 300K, and 1,144% at 5K (Ikeda and colleagues). That 604% is a laboratory structure, not a product stack, and no memory in this guide uses it.

The stability factor

How long a bit stays is set by how tall the barrier between the two states is, measured against thermal energy. Divide the free layer’s magnetic anisotropy energy by kBT and you get the thermal stability factor Δ, and Δ above 40 is required for reliable data retention over 10 years at room temperature (Krizakova and colleagues, again).

Here is a real part. In a 64Mb DDR3 spin-torque MRAM built on 90nm CMOS, the energy barrier averaged about 70kBT, measured by time-dependent coercivity and at higher temperature. In the same chip the switching voltage varied by about 10% (one standard deviation) with a single Gaussian shape, and the switching voltage was about 0.3 of the breakdown voltage, separated from it by about 25 standard deviations (Rizzo and colleagues, abstract).

Figure 3.1 puts the two states side by side. Its stack is a schematic, and the two numbers on the right are the TMR range and the stability threshold above. At about 70kBT, the barrier in a real part is well clear of the threshold of 40. For a shorter version, see the memory map’s section on MRAM.

Writing with current

Writing with current through the junction is spin-transfer torque (STT)STT-MRAM writes a bit by passing current through the magnetic tunnel junction itself. Electrons spin-polarized by the fixed magnet flip the free one, an effect called spin-transfer torque., and the first MRAM did not write that way at all.

The idea

In STT writing, current entering the reference layer is spin-polarized, tunnels into the free layer and transfers its spin momentum, which sets the free layer to the reference layer’s direction. Because the write path is the read path, reversing the current polarity writes the opposite state (IEEE roadmap).

Spin torque is older than the memory. Berger predicted in 1996 that a direct current crossing a normal-metal and ferromagnet interface emits spin waves and, beyond a critical current density, makes the spin damping negative, so the magnetization precesses by itself (Berger, abstract). A 2015 commentary by Kent and Worledge cites Slonczewski’s 1989 and 1996 papers and Berger’s 1996 paper. It also cites Julliere’s 1975 paper. This guide reads the first three as the start of the spin-torque idea and Julliere’s as the start of tunnel magnetoresistance. Slonczewski’s and Julliere’s papers are cited here from the commentary’s reference list.

Before spin torque

First-generation MRAM in volume wrote with a magnetic field. In toggle MRAM, currents in lines outside the junction make fields that switch the bit. Spin-torque MRAM passes current directly through the junction, which lowers write currents from milliamps to microamps (NASA JPL report, 2013).

A 4Mb toggle part was built in a 0.18µm CMOS process with a 1.55µm² bit cell, using a balanced synthetic-antiferromagnet free layer and a timed write-pulse sequence so that half-selected neighbors are not disturbed (Engel and colleagues, abstract). That cell works out to about 48F², from 1.55 divided by 0.18 squared, which is large. Toggle parts are still sold. Everspin’s fiscal 2025 report says its toggle MRAM has been in production since 2008 and comes in 128kb to 32Mb densities. Its MR2A16A is a 4Mb toggle part with SRAM-compatible 35ns read and write cycles, unlimited read and write endurance, data kept more than 20 years, and a 3.3V supply. Toggling the free layer is non-destructive, which explains the endurance.

What speed costs

Switching speed in STT is limited by the efficiency of the spin torque, an incubation delay and a precession frequency near a gigahertz. Because at most 100% of the current can be polarized, there is an upper bound on write efficiency (IEEE roadmap). Writing at sub-ns speed needs a large access transistorAn access transistor is the switch that connects one memory cell to its bit line when the cell’s word line rises, so only the selected row is read or written., which lowers density, and the higher write current damages the tunnel barrier, which lowers endurance, according to the same roadmap.

Published devices show how far the trade goes. Perpendicular junctions down to 16nm across switched with sub-3ns pulses below 100µA, with a TMR ratio above 150% and a resistance that was stable after 10¹² write events (Saida and colleagues, abstract). A 33nm quadruple-interface junction wrote in 10ns with more than twice the write efficiency of a double-interface one and an endurance of at least 10¹¹ (Miura and colleagues, abstract). And 30nm junctions showed error rates below 10⁻⁹ at 0.25V and 50µA with 10ns pulses (Jan and colleagues, abstract). That result is 0.12pJ for a 10ns write, per the IEEE roadmap.

Per Everspin, its STT-MRAM uses a perpendicular junction with high perpendicular anisotropy, the current direction through the junction sets the free layer, and switching energy is much lower than in its toggle MRAM. A 2013 review puts the STT cell at 6F² and potentially smaller, built as an extra metal layer on top of ordinary CMOS access transistors (Apalkov and colleagues, abstract).

Figure 3.2 shows the two write polarities and what two published devices paid. Since the fast device and the low-energy device are different junctions, no one junction in this guide wrote in under 3ns at 0.12pJ.

Writing beside the junction

Spin-orbit torque (SOT) takes the write current out of the junction, at the cost of a third terminal.

A third terminal

In SOT-MRAMSOT-MRAM writes a bit with current through a layer beside the magnetic tunnel junction instead of through its barrier. The separate read and write paths spare the barrier from wear. the free layer sits on a strip of a heavy metal or another material with strong spin-orbit coupling. Current along the strip produces a spin current into the free layer. Because the write path is separate from the read path, a larger read voltage can be used for faster reading (IEEE roadmap).

In 2011 a perpendicularly magnetized cobalt dot between platinum and AlOx layers was switched at room temperature by current injected in the plane of the layer, with the effect attributed to the Rashba interaction and possibly the spin Hall effect in platinum (Miron and colleagues, abstract). A year later, a measurement put the spin Hall angle of tantalum at 0.12 to 0.15, larger than platinum’s about 0.07 and of opposite sign, and demonstrated a three-terminal device read out by an MTJ (Liu and colleagues). A 2014 paper switched platinum, cobalt and AlOx dots 90nm across deterministically by in-plane current pulses from 180ps to milliseconds, with a negligible incubation time (Garello and colleagues).

What it buys

One device made the comparison that matters. In a three-terminal MTJ, SOT switched with 100% probability for pulses down to 0.27ns, while STT in the same device switched with a probability below one for pulses shorter than 10ns (Grimaldi and colleagues). At 0.27ns the minimum SOT switching energy was 0.4pJ, which STT could not reach. For long pulses it reverses. Above 5ns, the SOT critical energy was about an order of magnitude larger than STT’s.

Other devices agree on the direction. A spin-Hall-assisted in-plane junction switched reliably with 2ns pulses at write error rates down to 10⁻⁵ (Aradhya and colleagues). A field-free SOT cell on 55nm CMOS wrote in 0.35ns with no external field, with a Δ of 70, a TMR ratio of 167% and a 400°C thermal tolerance (Honjo and colleagues, abstract). On a 300mm wafer, a field-free concept was shown with reliable sub-ns switching across it (Garello and colleagues, abstract). On current density, the IEEE roadmap puts sub-ns SOT writing at 20 to 40 MA/cm², against 3 to 10ns STT switching at 7 MA/cm².

What it charges

Two of the three SOT cell types need a symmetry-breaking field or structure for deterministic switching. Only the type whose easy axis is orthogonal to the current is field-free, and it needs an initial perturbation for fast switching, so field-free switching and writing speed trade against each other (IEEE roadmap). Three terminals mean a large cell, and the fixes, a two-terminal perpendicular cell or several junctions sharing one write line, only partly relieve it. An array-level benchmark found SOT-MRAM fast and low in energy but with a cell area 25% larger than STT-MRAM (Liao and colleagues).

Its layouts show where the area goes. Read and write are separate paths, so an SOT cell needs two access transistors to avoid sneak currents and grows to 20F² with one write transistor, against 12F² for an STT cell with one access transistor, with F set at 30nm.

Those two figures are different comparisons. The 20F² against 12F² sets the one-write-transistor SOT layout against the smallest STT layout, while the 25% is the benchmark’s summary result, and that summary does not name the STT layout it is measured against. In that model, SOT is faster to write and lower in energy but slower to read, and both the longer read delay and the larger layout come from the device having three terminals.

A review summarizes the bargain. SOT offers cache-compatible speed and better endurance at the cost of larger write currents and a larger footprint, and stand-alone operation needs an applied magnetic field (Dieny and colleagues). Process adds its own cost. SOT shares the STT process platform and its 400°C back-end budget, but the free layer is at the bottom of the stack instead of the top, which forces new growth recipes. Etching has to stop on a channel under 5nm thick, and sidewall re-deposition risks shorts at pitches below 100nm (Krizakova and colleagues).

Figure 3.3 draws the two paths separately, with the read current in teal and the write current in copper. Its inset is the one device above, with 0.27ns for SOT against about 10ns for STT. This guide describes no SOT-MRAM product, and the IEEE roadmap describes SOT-MRAM for cache use as at a rather early stage of research.

Retention against speed

Retention and write speed look like a single trade in the physics, and the datasheets show they are chosen per product.

The energy barrier

Whatever barrier holds a bit in place is also the one a write has to push the free layer across. So the papers track Δ together with Δ divided by Ic0, the intrinsic critical current, as an efficiency ratio. A quad-interface free layer, two ferromagnetic layers with MgO below, between and above them, raised both Δ and Δ/Ic0 by a factor of 1.5 to 2 over a conventional double-interface junction, aimed at STT-MRAM beyond 20nm (Nishioka and colleagues, abstract).

Below 20nm across, the stability requirement calls for higher interfacial anisotropy. Double-MgO junctions have shown a factor of 2 improvement for diameters above 10nm, and shape-anisotropy pillars may extend STT-MRAM scaling below 10nm (IEEE roadmap).

One vendor, two retention specs

Specs are the clearest evidence. Everspin’s 1Gb ST-DDR4 datasheet gives a bit error rate of 1×10⁻¹¹, retention of 3 months at 70°C, endurance of 1×10¹⁰ cycles, and operation from 0 to 85°C (datasheet). In November 2025 the same company announced AEC-Q100 Grade 1 xSPI parts that keep data 10 years at 125°C with unlimited read and write endurance for 10 years, according to the release. One part is sold with months of retention at 70°C and the other with years at 125°C, both by the same vendor.

Embedded macros state their own terms. Intel’s embedded MRAM for 22FFL reported 10-year retention at 200°C with endurance above 10⁶ cycles on 7.2Mbit arrays (Golonzka and colleagues, abstract). A 37nm, 128Mb embedded STT-MRAM showed a 14ns write at 1.2V, endurance above 10¹⁰ and 10-year retention at 85°C (Sato and colleagues, title). An embedded STT-MRAM on 28nm FD-SOI operated from -40 to 125°C with endurance above 10⁶ and retention over 10 years (Lee and colleagues, abstract). TSMC reported one million cycles for its 16nm process in 2022, and NXP quotes 20-year retention at 150°C for the same technology.

Figure 3.4 sets those specs on one axis, with the retention printed under each name. Its right panel is a ladder of published specs. It is not a curve of speed against retention for one design: the rows are different cells, nodes and customers. It does show that most embedded macros state 10⁶ cycles, the 128Mb macro and the 1Gb part state 10¹⁰, and the two parts at the top state no limit. Toggle parts have the opposite profile to a spin-torque cell, with no wear to speak of, because toggling the free layer is non-destructive.

Scaling and arrays

The cell

A 2013 review puts the STT cell at 6F² or smaller, where F is the smallest feature a process can draw (the memory map has the unit explained). Figure 3.5 below sets the toggle cell, the review’s 6F² and the benchmark’s two layouts side by side. Both STT numbers come from different sources and this guide doesn’t reconcile them: the review states a figure for the cell, and the benchmark draws the whole layout. Junctions sit in an extra metal layer above the access transistor, and writing fast needs a larger transistor, which lowers density.

Smaller junctions

Working junctions in the sources run from 16nm to 40nm across, and no single trend runs through them. At 40nm, the perpendicular junction switched at 49µA. A 33nm quad-interface junction wrote in 10ns, the 30nm junction wrote in 10ns at 50µA, the 37nm macro held 128Mb, and the 16nm junctions switched with sub-3ns pulses. Different pulses, materials and goals sit behind those dots, and a current-against-diameter curve cannot be drawn from them honestly. Newer free-layer designs above are aimed at the smaller end, where stability gets harder to keep.

Figure 3.5 shows the cell areas on the left, with the source of each bar under it. Its right panel lists the junction sizes in the sources, one dot each. Products in the next section are described by process node (28nm FD-SOI, 22nm, 16nm FinFET), not by junction size.

Where MRAM is sold

MRAM reaches buyers in three ways: as parts you could order, as processes qualified for other companies’ chips, and as demonstrations.

A buffer inside a flash module

Everspin said on April 30, 2024 that IBM chose its PERSYST EMD4E001G 1Gb STT-MRAM for its FlashCore Module 4. The part has a DDR4 interface and delivers 2.7GB/s of both read and write bandwidth (Everspin). That links back to flash, with an MRAM part inside a flash module. The part runs only at the 667MHz speed bin, and its datasheet specifies a minimum row-to-column delay of 135ns where JEDEC DDR4 specifies 12.5ns. Everspin’s annual report says its STT-MRAM for DRAM replacement started production in 2017, is sold at 1Gb with DDR3- and DDR4-derived interfaces, and serves SSDs, persistent memory cards and fabric accelerators (fiscal 2025 report).

Code memory in microcontrollers

Part 1 covers what embedded flash was and why it stopped fitting. Foundry processes are where embedded MRAM is built into other companies’ chips. Samsung said on March 6, 2019 that it had begun mass production of its first embedded MRAM on a 28nm FD-SOI process, and that writing is roughly 1,000 times faster than embedded flash because MRAM needs no erase cycle (Samsung). Samsung’s figure is a vendor claim against embedded flash, and it adds that its eMRAM uses lower voltages than eFlash and uses no electric power in power-off mode.

A paper on STT-MRAM embedded in a 28nm FD-SOI logic platform showed an 8Mb array passing 1,000 hours of high-temperature operating life and an endurance test of 10⁶ cycles, and called a 128Mb array feasible (Song and colleagues, abstract).

GlobalFoundries announced embedded MRAM on its 22FDX platform in September 2016, with retention through 260°C solder reflow and claims of 1,000x faster writes and 1,000x more endurance than other non-volatile memory (GlobalFoundries). It planned customer prototyping in 2017 and volume in 2018. TSMC reported that its 16nm embedded MRAM completed reliability qualification in 2022 with one million cycles of endurance and reflow capability, and expected AEC-Q100 Grade 1 in 2023 (TSMC). NXP said on May 16, 2023 that its automotive MRAM in that process can update 20MB of code in about 3 seconds against about a minute for flash, with up to a million update cycles (NXP).

Standalone, small and fast

Standalone parts began with toggle MRAM. By 2012 Everspin had advanced from a 4Mb part on 180nm CMOS with a 35ns read cycle to a 16Mb part on 130nm, and its first commercial ST-MRAM appeared in November 2012, according to the JPL report. Everspin’s annual report says it started production of 4Mb to 128Mb STT-MRAM on a 28nm node in 2022 and sells 16Mb to 256Mb parts with SPI, xSPI, QSPI and Octal SPI interfaces. The Grade 1 parts above come in 64Mb and 128Mb densities that read and write at 90MB/s, per Everspin.

Per the IEEE roadmap’s summary, STT-MRAM has entered commercial production for embedded and standalone flash-like uses, with embedded MRAM ready at TSMC, GlobalFoundries and Samsung, standalone parts from megabit to gigabit densities from Avalanche and Everspin, and fewer masks than embedded flash. Avalanche’s Ava-MRAM is sold as space-grade memory with claimed radiation immunity, unlimited endurance and nanosecond writes; its page gives no density or figures, so this guide has nothing to compare.

Where the speed numbers come from

Fast numbers come from macros and test chips, not parts. Renesas reported at VLSI 2022 a 22nm embedded STT-MRAM test chip with a 32Mbit array, 5.9ns random read access at a maximum junction temperature of 150°C and 5.8MB/s of write throughput (Renesas). At ISSCC 2024 it reported a 10.8Mbit macro with random reads above 200MHz and 10.4MB/s of write throughput (Renesas). An 8Mb macro in 16nm FinFET read in 9ns from -40 to 125°C at 0.8V and used a 50ns write pulse (Shih and colleagues, abstract). The two Renesas chips write at 5.8MB/s and 10.4MB/s, against the 90MB/s Everspin gives for its Grade 1 parts, which you could order.

A 22nm FD-SOI macro showed a median-die bit error rate below 1ppm after five solder reflows and a standby magnetic immunity of 1.4 kOe, about 140mT, at a 1ppm error criterion after one hour at 25°C (Lee and colleagues, abstract). Reflow survival is the test an embedded memory has to pass to hold firmware, and Part 1 covers it.

Figure 3.6 sorts the dated parts, processes and papers in this guide by year and by lane. Parts you could order run from the first spin-torque part to a 1Gb module component and a Grade 1 xSPI family. Fast numbers like the 5.9ns Renesas read sit in the research lane.

Why DRAM density is still open

Harder still is whether MRAM can replace DRAM. It can’t yet. The standalone part holds a sixteenth of a DRAM die, and its row-to-column delay is far above DDR4’s.

Density

Micron’s DDR5 die is 16Gb. Everspin’s densest standalone STT-MRAM is 1Gb, so one DRAM die holds sixteen times as much. STT-MRAM at DRAM density is an open area for research in the IEEE roadmap, which names two high-potential approaches: die stacking with through-silicon vias, and selector-MTJ crossbar 3D integration. A review adds that DRAM replacement needs the junction patterned at very narrow pitch, through improved etching chemistries or by depositing the MTJ on pre-patterned pillars (Dieny and colleagues).

Speed on the memory pins

Embedded macros above read in 5.9ns to 9ns. Against that, the standalone DDR4 part specifies 135ns from row to column where DDR4 specifies 12.5ns. These aren’t the same measurement, a macro read against a command-timing parameter, so the comparison is a warning and not a ratio. A fast array does not make a fast DRAM replacement. Working Memory, Part 2 explains what row-to-column delay measures and why its value depends on the speed bin.

Figure 3.7 puts those numbers on a log axis next to two values from the memory map’s hierarchy: the first byte of a NAND page read at 25µs and a TLC data-center SSD’s 4KiB read at 80µs. That 25µs value comes from Micron’s note on an SLC chip. Both embedded macros sit next to DDR4, the standalone part sits about an order of magnitude to the right, and the NAND reads about two more.

Magnets near magnets

MRAM has a hazard that DRAM does not. Current STT-MRAM chips withstand magnetic fields up to a few hundred mT in standby, and operate without error from a few tens of mT to about 100mT depending on the chip, with a write at the lowest operating temperature the critical case (Dieny and colleagues, 2024). Magnetic screwdriver tips can reach up to 100mT, above the immunity threshold of most standalone chips, and the field falls below 25mT at 1mm. The authors conclude that the care needed is mainly at chip handling and installation, and that shielding may be needed in extreme environments.

What is still research

Some writing methods are still a long way from products. Voltage-controlled magnetic anisotropy (VCMA) writing reached 6fJ per bit at 0.5ns and 1.96V in research devices. The VCMA coefficient is about 100fJ/V-m. That is too small, since the roadmap says more than 300 is needed for advanced nodes. The same roadmap calls precessional writing non-deterministic (IEEE roadmap).

What to watch

MRAM is sold where speed, endurance or surviving a power cut beat cost per bit: a buffer in a flash module, code memory in a microcontroller, small fast standalone parts. Replacing DRAM is a different problem, and it comes down to density. The roadmap’s two routes to it are stacked dies and crossbar arrays, and the sign to watch is a standalone part denser than 1Gb.

Next is ferroelectric memory, in Part 4, where the bit is a polarization instead of a magnetization. More are listed on the series page.