Reference
Concepts
35 concepts from flash and SSD engineering, each with the sourced facts behind it and the source each comes from.
Each concept page lists the facts the site relies on for one idea, with the source named beside every fact. The pages are compiled from the site’s fact ledger, and a fact appears here only when its figures are found in the source’s own words. More concepts join as their facts are checked.
3D structure and process
- Cell Footprint: 4F Squared vs 3D Cell Area 4 facts
- Charge Trap Adoption Across Vendors 25 facts
- CMOS Under Array (CuA/PUC) 3 facts
- Layer Counts 7 facts
- Process Variation in Tall Stacks 8 facts
- Replacement Gate Process 3 facts
- The Planar Scaling Wall 13 facts
- The Staircase Contact 10 facts
- Why Layer Counts Are Not Comparable 4 facts
- Wordline Metal in 3D NAND 7 facts
Array organization
- Planes and Multi-Plane Operation 4 facts
- Sensing and Sense Amplifiers 5 facts
- The NAND String (Series Connection) 3 facts
Cell physics
- Coulomb Blockade 4 facts
- Fowler-Nordheim Tunneling 4 facts
- Nanocrystal, SONOS and MONOS History 3 facts
Controller hardware
- Interleaving 4 facts
- PMIC and Power Rails 5 facts
- Read-Reference Voltage Calibration 5 facts
Endurance and qualification
FTL mapping
- Flexible Data Placement (FDP) 3 facts
- FUA and Flush Semantics 3 facts
Host interfaces and protocols
- ASPM and NVMe Power Features 3 facts
- CXL Generations, Adoption and Switching 4 facts
- CXL.io, CXL.mem and CXL.cache 4 facts
- PCIe Generations, Transfer Rates and x4 Bandwidth 6 facts
- SR-IOV 3 facts
NAND interface
- ONFI and Toggle NAND Interfaces 7 facts
Performance and QoS
- Preconditioning and Steady State 4 facts
- Thermal Throttling 3 facts
Reclamation
- Background Refresh 3 facts
Reliability mechanisms
Security and sanitization
- Cryptographic Erase 5 facts