Eyes on Flash/ Driven by Insight
Contact

Search Eyes on Flash

Tip: press / or Ctrl+K on any page to open search.

Type to search.

    A stop-motion film Flash, Frame by Frame

    Flash memory from the 1967 floating gate to stacks of more than 400 layers, in 5:03 of stop motion. One steel ball plays the stored charge in every shot.

    Now showing · 5:03

    Watch the film The 41 steps Explore the timelines

    The film

    Six acts, 41 steps, 5:03. Pick a step below to jump to it.

    6 acts · 41 steps · 5:03 · 3,636 frames at 12 frames a secondMusic: Fretless by Kevin MacLeod (incompetech.com), licensed under Creative Commons: By Attribution 4.0.

    One ball, one long table, every frame drawn

    The film is a long tabletop running through the years, with a brass year rail along its front. Each milestone is a station on it, and the ball, the stored charge, rolls from one to the next and gets stored, erased or stacked the way that era did it. The camera moves in close to each idea, a paper slate gives the date, and three brass gauges show the NAND die record for that year. Every frame is drawn and held for two, so it moves like stop motion.

    Frame rate
    12fps
    Running time
    5:03
    Frames
    3,636
    Steps
    41

    Six acts, one ball

    Each step is one milestone in how flash got here. The line under each slate is what the step shows, and every date and number in it comes from the sources at the bottom of the page or from the sourced die records on the timelines.

    1. The idea

      1. A floating gate

        1967 · Kahng and Sze: a floating gate

        Dawon Kahng and Simon Sze of Bell Labs publish a floating gate in the Bell System Technical Journal in 1967: a gate wrapped in oxide, so charge put on it stays. Every flash cell since holds its bit this way.

      2. Erased by a lamp

        1971 · Intel 1702: 2048 bits, erased by UV light

        Intel announced the 1702 in 1971, a 2048-bit EPROM designed by Dov Frohman. Shine ultraviolet light on the chip and the stored charge drains away, so the chip can be written again.

      3. Erased by a wire

        1976 to 1977 · Eli Harari: erase by electricity

        Eli Harari’s 1976 to 1977 floating-gate EEPROM writes and erases with a voltage alone: charge tunnels in and out through a thin oxide around 100 angstroms thick. The lamp is no longer needed.

      4. Flash

        1984 · Masuoka, Toshiba: flash

        Fujio Masuoka shows Toshiba’s flash cell at IEDM in 1984: one transistor per bit, written like an EPROM and erased through a third layer of polysilicon, an erase gate.

    2. Two kinds of flash

      1. NAND

        1987 · NAND: cells in series

        In 1987 Masuoka’s team puts the cells in series, sharing contacts, in a NAND string. The cell takes 30% less area per bit than a conventional EPROM.

      2. NOR

        1988 · Intel NOR flash: 256 kilobits

        Intel introduces NOR flash in 1988 as a 256-kilobit chip: every cell on its own contact, so it reads fast, while NAND packs tight.

      3. NAND on sale

        1989 · Toshiba’s first NAND on sale

        Toshiba’s first NAND flash reaches the market in 1989.

    3. Flash replaces things

      1. The first flash SSD

        1978 · 45MB, $400,000 / 1991 · 20MB, about $1,000

        Before flash, an SSD was RAM with a battery behind it: StorageTek’s 1978 STC 4305 held 45MB for $400,000. In 1991 SunDisk, now SanDisk, built a 20MB flash SSD for IBM laptops, about $1,000, with a controller that found and fixed bad cells.

      2. CompactFlash

        1994 · CompactFlash

        SanDisk specified CompactFlash and made the first cards in 1994.

      3. A map for the flash

        1995 · M-Systems: a flash file system

        Amir Ban’s flash file system patent for M-Systems is published in 1995: it maps data to unwritten places in the flash, an early flash translation layer. The same year M-Systems builds the DiskOnChip.

      4. SD

        1999 · SD: SanDisk, Panasonic and Toshiba

        SanDisk, Panasonic and Toshiba bring out the SD card in August 1999.

      5. The thumb drive

        2000 · USB drives: 8MB on a keyring

        In 2000 IBM sells M-Systems’ 8MB USB drive as the DiskOnKey, and Trek shows its 8MB ThumbDrive.

      6. Two bits in a cell

        2001 · 1Gb NAND, 2 bits per cell

        Toshiba and SanDisk bring out the first commercial 1Gb NAND chip in November 2001, storing 2 bits in each cell.

      7. The die record begins

        2002 · 1Gb dies at 130nm and 120nm

        The die record on the timelines starts in 2002 with 1Gb planar NAND dies: Toshiba’s at 130nm and Samsung’s at 120nm. See the dies on the timeline

      8. The disk comes out

        2005 · iPod nano: flash, not a disk

        Apple’s iPod nano, introduced in September 2005 in 2GB and 4GB models, has flash memory instead of a hard drive.

      9. Notebooks and a shared plug

        2006 · SSD notebooks; ONFI 1.0 at 50 MT/s

        In 2006 Samsung brings out the first high-volume notebook with an SSD, and ONFI 1.0 gives NAND a shared interface, asynchronous, at up to 50 MT/s.

      10. Flash goes into phones

        2007 · iPhone; e.MMC: flash and controller in one chip

        Apple introduces the first iPhone in January 2007, in 4GB and 8GB models, and it stores its data in flash. JEDEC’s e.MMC standard of December 2007 puts flash memory and a flash memory controller in one soldered package.

      11. More bits, a faster lane

        2007 · 4 bits per cell shown / 2008 · 3 bits; 200 MT/s; an 80GB SSD

        A 16Gb die storing 4 bits per cell is shown in 2007. In 2008 a 3-bit die follows, the first DDR NAND die moves data at 200 MT/s per pin, and Intel ships the 80GB X25-M. See the dies on the timeline

      12. A wider lane

        2011 · NVMe 1.0

        The NVM Express 1.0 specification, dated March 2011, gives SSDs a command set built for flash on PCI Express.

      13. A faster link for phones

        2013 · UFS 2.0; in phones from 2015

        JEDEC publishes Universal Flash Storage 2.0 in September 2013, with higher link bandwidth for mobile storage, and the Galaxy S6 ships it first, in 2015.

    4. The wall

      1. Stronger error correction

        2014 to 2015 · LDPC error correction

        Shrinking cells and the move from 2 bits to 3 per cell blur the levels a read has to tell apart. In 2014 Marvell’s 88SS1074 uses LDPC error correction to make 15nm TLC usable, and in 2015 Silicon Motion pairs it with 16nm TLC.

      2. Flat flash hits a wall

        2014 to 2016 · The last flat cells: 16nm to 14nm

        From 2014 the last planar generations were 15nm and 16nm parts, and a 14nm die shown in 2016 is the last planar one in the record. By 16nm a 100mV shift in a cell was 2.8 electrons, down from 40 at 90nm. See the dies on the timeline

    5. Going up

      1. Vertical NAND

        2013 · Samsung V-NAND: 24 layers

        Samsung’s first V-NAND, in 2013, stands the string on end: 24 layers on a 128Gbit die. See the dies on the timeline

      2. A 3D drive

        2014 · Samsung 850 PRO: a drive on V-NAND

        Samsung launches the 850 PRO in July 2014, an SSD built on its 3D V-NAND.

      3. A second tower

        2015 · Intel and Micron: 32 layers

        Micron and Intel answer in 2015 with 32 layers of floating-gate 3D NAND.

      4. The drive becomes a stick

        2015 · M.2 NVMe: the SM951

        In April 2015 Samsung starts mass production of the SM951, the industry’s first NVMe PCIe SSD in the M.2 form factor for PCs: a board 22mm wide.

      5. Logic under the array

        2016 · CMOS under the array

        Intel and Micron’s 768Gb 3-bit die, shown in 2016, tucks the control logic under the cell array.

      6. 64 layers

        2017 · 64 layers

        Toshiba and SanDisk describe a 512Gb 3-bit die on 64 word-line layers at ISSCC 2017.

      7. Four bits per cell

        2018 · QLC: 4 bits per cell

        Micron’s 5210 ION, in 2018, is the first QLC SATA SSD: 4 bits per cell, so one cell tells 16 charge levels apart.

      8. Two plates, bonded

        2019 · 128 layers; Xtacking

        SK hynix puts a 128-layer 1Tb die into mass production in 2019, and YMTC builds its 64-layer die with Xtacking, logic made on a second wafer and bonded on. See the dies on the timeline

      9. 176 layers

        2020 · 176 layers

        Micron ships 176-layer TLC in 2020.

      10. New names

        2019 to 2021 · Kioxia, Solidigm, YMTC

        Toshiba Memory becomes Kioxia on October 1, 2019. In October 2020 SK hynix agrees to buy Intel’s NAND business for US$9 billion, and by December 2021 its SSD business is branded Solidigm. YMTC becomes China’s first mass producer of 3D NAND.

      11. 232 layers

        2022 · 232 layers; 5 bits per cell

        Micron’s 232-layer NAND is in volume production from July 2022, and Solidigm shows a working SSD storing 5 bits per cell the same year.

      12. PCIe Gen5

        2023 · PCIe Gen5 drives

        The first wave of PCIe 5.0 SSDs reaches the market in 2023, nearly all on Phison’s E26, the first consumer Gen5 controller: 8 channels at up to 2,400 MT/s.

      13. Past 300

        2023 · 300 layers shown

        SK hynix shows a die with 300 layers at ISSCC 2023, the first in the record to reach that mark. See the dies on the timeline

      14. 321 layers

        2024 · 321 layers in mass production; 218 layers, bonded

        SK hynix puts 321 layers into mass production in November 2024, the first 300-plus-layer NAND in mass production. Kioxia builds its 218-layer die with CBA: the CMOS logic made on its own wafer and bonded to the array.

      15. Drives bigger than the ball

        2023 · 61.44TB / 2024 · 122.88TB / 2026 · 256TB; 300TB modules

        Solidigm’s QLC D5-P5336 holds up to 61.44TB in July 2023, and a 122.88TB version follows in November 2024. In 2026 Micron ships a 245TB drive, Sandisk’s 256TB UltraQLC comes in U.2, and Everpure’s DirectFlash modules reach up to 300TB.

      16. 2Tb on one die

        2025 · 2Tb dies; 5,600 MT/s shown

        In 2025 single dies reach 2Tb, and a bonded Samsung die is shown moving 5,600 MT/s per pin. See the dies on the timeline

      17. High bandwidth flash

        2025 · High bandwidth flash

        Sandisk shows High Bandwidth Flash in February 2025: NAND sized like HBM stacks, 512GB in a 16-die stack. In August 2025 it signs with SK hynix to set the specification.

      18. Out of frame

        2026 · 332 layers; 400+

        Kioxia and Sandisk sample 332 layers in July 2026. Samsung shows a design with more than 400 layers, and Micron states 400+ for its G11. Marvell’s Bravera SC6 is a PCIe Gen6 controller with 16 channels.

    6. In your hand

      1. The drive in your hand

        Since 1967, the same trick: trap a little charge, and keep it.

        The tower goes into a package, onto an M.2 board beside its controller, and the ball from the first shot rolls on. Since 1967 the trick has stayed the same: trap a little charge, and keep it.

    Go deeper than a film can

    The timelines chart NAND dies, controllers, DRAM dies and HBM stacks by date, each point with its source. The Atlas takes an SSD apart down to a single cell.

    Explore the timelines Open the Atlas page

    Sources

    Primary is the original paper, standard or datasheet. Secondary is a review, a vendor summary or a news report. Measured is my own test data.

    Show all 56 sources, 39 primary