Photolithography, Part 6: The Rest of Advanced Packaging

Part 5 showed how CoWoS gets past the reticle limit by laying dies side by side on a slab of silicon. CoWoS is one tool among several, and this part of the Photolithography series covers the rest. Phone processors can use a package with no organic substrate at all. Intel connects dies with small silicon bridges instead of a slab. The newest products stack dies face to face with no solder between them. The same bonding now builds 3D NAND, and HBM5 and later generations are expected to use it. Packages have grown so large that round wafers waste too much area, so the industry is looking at square panels and glass, and light itself is moving into the package.

Beside or on top

Every advanced package joins dies in one of two directions. Side by side, often called 2.5D, the dies sit next to each other on a shared layer of fine wiring. That layer is a silicon interposer, a silicon bridge or a layer of redistribution wiring (RDL). Stacked, called 3D, one die sits on another and they connect straight through their faces. Intel’s Data Center GPU Max and Clearwater Forest and AMD’s MI300 all use both.

TSMC’s 3DFabric family includes SoIC for stacking dies face to face, and CoWoS and InFO mainly for placing them side by side (InFO-PoP also stacks a memory package on top). In TSMC’s description, the family consists of both wafer-level front-end and back-end technologies, built on wafer processes. An SoIC stack can then go into a CoWoS or InFO package.

Intel’s packaging line starts with EMIB, a silicon bridge embedded in the package substrate. Foveros-S uses a silicon interposer of four reticle sizes. It has been in mass production since 2019 with an active base die. Foveros-R uses an RDL interposer instead. Intel’s timeline has it production ready in 2027. Foveros Direct stacks dies with a copper-to-copper hybrid bonding interface. EMIB 3.5D puts bridges and Foveros stacks in one package. Built that way, its Data Center GPU Max has more than 100 billion transistors in 47 active tiles from five process nodes.

Samsung Foundry’s packaging page splits its offer in two. Its horizontal integration places chips side by side. Samsung credits its through-silicon via and back-end-of-line technologies as the foundation for it. Its vertical integration stacks components to shorten the wires between them. Samsung announced its X-Cube 3D IC packaging in August 2020. Its 7nm test chip used through-silicon vias to stack SRAM on a logic die.

Samsung’s own animation shows X-Cube stacking SRAM on a logic die:

InFO: wiring built on the die

In an ordinary flip-chip package, the bumps on a die land on an organic substrate. This small circuit board spreads the connections out to the larger pitch of the motherboard. A fan-out package moves the fine wiring onto the die itself. The die is embedded in mold compound, and redistribution wiring is built directly across the face of the die and the mold around it, so the wiring fans out past the die’s edges to reach the outer connections.

TSMC’s version is Integrated Fan-Out, InFO. It uses high-density RDL plus through-InFO vias (TIVs), which are copper posts that run through the mold to carry signals from top to bottom. TSMC calls its InFO-PoP the industry’s first 3D wafer-level fan-out package. It stacks DRAM over a mobile application processor. TSMC claims it is thinner and performs better electrically and thermally than a flip-chip package-on-package because it has no organic substrate or C4 solder bumps. Versions for larger chips, such as InFO_oS, keep a substrate underneath but still build the fine wiring as RDL on the dies.

The fan-out wiring is made with lithography, on wafers, with the packaging tools described in Part 5, so the same line widths come up again. In its 2021 Hot Chips tutorial, TSMC listed InFO_oS down to 2µm lines and spaces in five RDL layers, with copper bumps on a 130µm pitch. InFO_oS at 1.5 reticle sizes had been in mass production since 2018. A version of 2.5 reticle sizes, 51mm by 42mm on a 110mm-square substrate, came in 2021. An InFO_LSI version adds local silicon bridges for the densest links. It has chip pads on a 25µm pitch instead of 40µm, and lines of 0.4µm instead of 2µm.

The largest InFO is a whole wafer. TSMC’s InFO_SoW is a system on wafer. It uses the wafer itself as the package, with power and thermal modules attached. Against a flip-chip multi-chip module, TSMC claimed 5µm lines instead of 10µm, twice the bandwidth density, and power delivery impedance about 3% of the module’s.

Bridges instead of a slab

A silicon interposer gives every connection fine wiring, but the finest wiring is needed mainly in the strip where two dies face each other. Intel’s Embedded Multi-die Interconnect Bridge, EMIB, uses silicon only there. Standard EMIB has been in volume production since 2017. It embeds small silicon bridge dies in cavities in an organic substrate, which route signals sideways between neighboring chiplets and avoid the cost and reticle limits of a full silicon interposer. Intel’s own page calls it a shoreline-to-shoreline connection.

The first EMIB bridges had no through-silicon vias, which kept them simple and cheap. Power for the dies above had to route around the bridge through the substrate, in long paths with more resistance. That was fine for Intel’s Sapphire Rapids and Ponte Vecchio, but not for accelerators with HBM4-class power demands. Intel now lists EMIB-M, with metal-insulator-metal capacitors in the bridge, and EMIB-T, which adds TSVs to the bridge. Those TSVs let power rise straight through the bridge, according to Tom’s Hardware.

At the Electronic Components and Technology Conference in 2025, Intel gave these EMIB-T figures. Bumps sit on a 45µm pitch, with 35µm and 25µm on the roadmap, and about 0.25pJ/bit. EMIB-T supports HBM3 through HBM5 and scales to packages of 120mm by 180mm with more than 38 bridges and more than 12 reticle-sized dies. Intel also claims about 90% wafer utilization for bridge dies against about 60% for large interposers, which is the round-wafer problem at the end of this part. As of Tom’s Hardware’s April 2026 report, EMIB-T was not yet in a commercial product. Mark Gardner is Intel Foundry’s vice president of packaging, and he expected external customer designs in production in the next year or two.

Bridges and stacks combine. Intel’s Clearwater Forest server processor, launched in the first half of 2026, combines standard EMIB with Foveros Direct hybrid bonding across 17 tiles, according to Tom’s Hardware. They are 12 compute tiles on Intel 18A, three base tiles on Intel 3, and two I/O tiles on Intel 7, connected by 12 EMIB bridges. The idea is the same one that runs through Part 5: spend fine silicon wiring only where the signals need it, and coarser wiring everywhere else.

Face to face: hybrid bonding

Most of the joints so far are solder. They are tiny copper pillars capped with solder, melted together, then the gap between the dies filled with underfill. HBM4 keeps that kind of joint. Microbump pitch has historically been about 40µm and, with HBM4, is moving closer to 10µm, according to Semiconductor Engineering. The solder, the gap, and the filler still take room, and hybrid bonding removes them. Both surfaces are polished flat, with copper pads set flush into silicon oxide, and the two dies are placed face to face.

SK hynix described the steps at Hot Chips 2026, as ServeTheHome reported. The dies are picked and placed at room temperature, then an anneal above 200°C forms oxide-to-oxide and copper-to-copper bonds at once, which is why it is called hybrid. There are no bumps and no gap to fill.

TSMC’s SoIC is a wafer-level platform for stacking chips in 3D. Its bond pitch starts below 10µm. Its 3nm chip stacking entered volume production in 2025. A finished SoIC stack can go into a CoWoS or InFO package and, from the outside, looks like an ordinary system-on-chip. It offers two forms. Chip on wafer places known-good dies onto a wafer, and wafer on wafer bonds two whole wafers. Wafer on wafer suits high-yielding processes and dies of the same size. Whole wafers go in at once, so the dies cannot be sorted first, and the IRDS ties wafer-to-wafer stacking to a very high yielding process on each wafer, because of testing and wafer-sorting challenges. Intel’s Foveros Direct is the same kind of copper-to-copper bond.

AMD’s MI300 accelerators show how far this has gone. AMD hybrid-bonded its compute dies onto active base dies with the first generation of SoIC at a 9µm pitch. It backed off from the 6µm second generation because that was not yet mature. The stacks were then packaged on a passive interposer. In SemiAnalysis’s account, that interposer is TSMC’s CoWoS-S. By the same count, that one product uses flip-chip reflow, thermocompression bonding, and chip-on-wafer, wafer-on-wafer, and reconstituted wafer-on-wafer hybrid bonding.

Hybrid bonding brings a testing problem. The bonding surface must be spotless, and a test probe can scratch a pad or leave a particle. Pax Wang is director for advanced packages at UMC, and he put it to Semiconductor Engineering bluntly: “Testing is a particle source.” That makes it harder to confirm each die is good before it is bonded. UMC’s flow tests the layers first and then planarizes the surface again to repair it before bonding.

How fine the joints get

The pitch of chip connections spans more than two orders of magnitude, from 130µm package bumps to die-to-die bonds below 1µm. A finer pitch means more connections in the same area. The number per square millimeter rises with the square of the pitch ratio, so going from a 40µm microbump to a 9µm hybrid bond gives about 20 times as many connections in the same area.

TSMC’s 2021 roadmap ran SoIC from 9µm to 6µm, then 3µm. It showed a stack bonded at a 0.9µm pitch. TSMC’s slide calls it highly reliable after 1,000 cycles (it labels the test TCB without defining it). At that pitch, TSMC said, bonding starts to merge with the on-chip wiring itself. The lower rows of the chart are lithography territory again, with pads a few microns apart, on surfaces flat enough to touch everywhere, aligned across a whole die or wafer. Vikas Gupta, director of engineering and technical promotion at ASE Group, told Semiconductor Engineering that hybrid bonding gives an order of magnitude lower energy per bit than microbumps.

Building an HBM stack

An HBM stack begins as ordinary DRAM wafers, with extra steps inside the front-end fab and after it. SK hynix showed its flow at Hot Chips 2026, in slides ServeTheHome photographed. In the fab, holes are etched into the silicon, lined with an insulator and a barrier metal, filled with copper and polished flat before the usual wiring goes on top. Next, the bumping line forms bumps on the front, bonds the wafer face down to a temporary carrier, and thins it from the back until the copper in each hole is exposed. Each copper column is now a through-silicon via (TSV). Bumps go on the back, the dies are stacked and molded, and the stacked wafer is tested so that only known-good stacked dies are cut out and sent to the customer’s package.

Each hole is a lithography and etch job like any other layer. Resist defines where the holes go, and SK hynix lists the steps that follow as a via etch, a liner and barrier deposition, and a high-aspect-ratio copper fill. The etch is deep and narrow. Lam Research’s annual report says its Syndion etch product family is optimized for deep silicon etch, which may include TSVs for packaging. One such deep etch is the cycle Robert Bosch GmbH patented. Short etch steps in a fluorine gas such as sulfur hexafluoride alternate with steps that coat the hole in a thin polymer. Repeating the pair until the hole reaches its depth drives it straight down instead of letting it spread sideways.

MR-MUF against TC-NCF

Once thinned, every die rests on its microbumps alone, so the space between dies has to be filled before the stack can take any force. HBM makers split on how. Samsung and Micron bond with thermocompression and a non-conductive film (TC-NCF), according to Semiconductor Engineering. A film goes between each pair of dies, and heat and pressure melt it, join the bumps and set the film, one layer at a time. SK hynix used the same method through HBM2. Since HBM2E in 2019 it has used mass reflow molded underfill (MR-MUF), soldering the whole stack in one pass and then flowing a liquid epoxy molding compound into every gap. It says it is the only maker that does. A slide from its Hot Chips 2026 talk sets the two methods side by side.

Source: SK hynix, Hot Chips 2026 slide “HBM Package Technologies” (photographed by ServeTheHome) and newsroom; Semiconductor Engineering, “HBM Leads The Way To Defect-Free Bumps.”

SK hynix also supplies the firmest heat numbers. In its IEDM 2023 paper, MR-MUF stacks of an 8-high HBM2E cube had 0.5 to 0.64 of the thermal resistance of TC-NCF stacks, or lower. The paper’s Figure 6 shows more than three times the thermal bumps and a stack running about 14°C cooler on average at a 2.0Gbps data rate. That is one maker measuring its process against its rivals’ kind, so it reads as SK hynix’s result. By Samsung’s own figures, its advanced TC-NCF leaves a 7µm gap between dies and fits 12 dies in the height of 8, and bumps sized for signal or for heat gave its HBM3E an 11% better thermal resistance than the generation before.

Warpage is where MR-MUF pays. For 12-high HBM3, SK hynix’s dies had to be 40% thinner than in its 8-high part, and they warped, so Advanced MR-MUF tacks each die with a quick burst of heat as it is placed. TC-NCF keeps its edge on thin dies but bonds one die at a time. Semiconductor Engineering also notes that mass reflow is the most mature and least expensive solder flow there is.

Counterpoint estimates SK hynix’s HBM share at 50% in Q2 2026, with Samsung at 33% and Micron at 18%, against 64%, 15% and 21% a year earlier. Samsung’s 12-high HBM3E reportedly cleared NVIDIA’s tests in September 2025 after about a year and a half of setbacks, with a redesign aimed at heat, TrendForce reported, citing Korean press, though Samsung had not yet received NVIDIA’s formal approval. Micron sells on power. It claims its HBM3E uses 30% less than competing parts, a figure from simulation.

Memory is bonded too

Memory makers apply the same bonding to whole wafers. Part 3 showed Kioxia’s CMOS directly Bonded to Array (CBA) process, which builds the control circuits and the 3D NAND array on separate wafers and bonds them face to face with copper pads. Kioxia applied CBA to its eighth-generation BiCS FLASH. In an interview reprinted from EE Times, Kioxia puts that generation at 50% higher gigabyte density than the one before. Flash Foundations Part 4 covers the same step and YMTC’s similar Xtacking.

This is wafer-on-wafer hybrid bonding at full scale, every die on two 300mm wafers joined at once. Kioxia’s Atsushi Inoue put the alignment this way. If a wafer were 1km across, the bond would have to line up to the order of 1mm or less. That is one part in a million. On a 300mm wafer it works out to a scale of about 0.3µm, an overlay problem like the ones scanners face in Part 1. Kioxia says the bonding pitch is just a few microns. Each wafer’s surface must be very flat for the two to bond smoothly.

HBM is heading the same way, more slowly. SK hynix told Hot Chips 2026, as ServeTheHome reported, that hybrid bonding is its path to stacks of 20 or more dies. At the same total height, it allows thicker core dies and pushes the bump pitch below 18µm, which MR-MUF cannot manage. HBM4 stays on microbumps because JEDEC raised the stack height limit, as Part 5 explains, and HBM5 and its successors are expected to use hybrid bonding, according to Semiconductor Engineering.

The package is also changing what a memory maker sells. SK hynix said that in advanced packaging for AI, HBM is now assembled first instead of last, which puts its stacks under much stronger reliability pressure before the rest of the package is built. Part 5 covers the custom base dies expected with HBM4. SK hynix told Hot Chips that it leans on an optimized logic foundry process to improve power delivery. Samsung pairs its 1c DRAM dies with a 4nm base die from its own foundry. This guide reads that as HBM becoming a part designed alongside the processor and the package that holds them both.

Round wafers, square packages

Packages are rectangles, and wafers are round. Small dies tile a wafer well, with little lost at the curved edge, but large packages do not. The 2025 lithography chapter of the International Roadmap for Devices and Systems (IRDS) says that as package sizes grow, the usable share of a round wafer becomes a critical issue, and that many companies have started exploring rectangular panels instead.

In this guide’s model, squares the size of one reticle field fill about 85% of a 300mm wafer. Squares the size of a nine-reticle interposer, the size TrendForce reported in November 2024 as TSMC’s largest planned CoWoS, fill about 65%, six to a wafer, before any edge is set aside. Intel claims about 60% wafer utilization for large interposers, close to that, and argues for small bridges instead.

A panel avoids the curved edge. Lam Research describes fan-out panel-level packaging as cutting chips or chiplets from a large-format sheet several times the size of a silicon wafer, which raises yield and cuts waste. Packaging houses are building for it. Powertech Technology broke ground on a fan-out panel-level packaging plant in Taiwan in 2018. In November 2025 it bought a factory in the Hsinchu Science Park as a base for future expansion of that capacity.

Panels bring lithography problems of their own. The IRDS names two panel approaches. One is a miniaturized organic package substrate and the other is an RDL interposer built on a glass carrier, and both use silicon bridges for the finest links. A carrier is removed once the wiring is built, so it supports the work but does not stay in the package. The roadmap names panel flatness as the key challenge for fine patterning. Silicon and glass wafers are flat enough, but glass or organic panels may not be, which eats into the depth of focus from Part 2. Steppers with 4x reduction are a main option for panel packages larger than four reticle fields. Maskless laser direct writing can resolve below 2µm with no masks to change, but its throughput and quality assurance are still challenges. Multibeam electron beam and magnifying projection steppers have also been proposed.

Glass can also become a permanent part of the package, replacing its organic core. In 2023 Intel announced glass core substrates, planned for the latter part of the decade. It said glass has 50% less pattern distortion, is flat enough to improve depth of focus for lithography, and is stable enough for very tight layer-to-layer overlay. As a result, Intel said, a tenfold increase in interconnect density is possible on glass.

Light in the package

The newest thing to move into the package is the optical link. In a network switch today, the switch chip drives electrical signals across the circuit board to pluggable optical modules at the front panel, which turn them into light. Co-packaged optics put the optical engines in the same package as the switch chip, so the electrical signal no longer crosses the board. Broadcom says this reduces the need for signal conditioning and cuts trace loss and reflections.

Broadcom announced its third-generation co-packaged switch, Tomahawk 6 Davisson, in October 2025: 102.4Tbps from 16 optical engines of 6.4Tbps each, at 200Gbps per channel, with the lasers in field-replaceable modules. Its optical engines use TSMC’s Compact Universal Photonic Engine (COUPE), part of TSMC’s SoIC family, and by Broadcom’s figures the design cuts optical interconnect power by 70% against pluggable modules. NVIDIA bills its Spectrum-X Photonics switches at 1.6Tbps per port. It claims they use four times fewer lasers to deliver 3.5 times the power efficiency. C. C. Wei, chairman and CEO of TSMC, said TSMC’s silicon photonics solution for them combines its chip manufacturing with SoIC 3D stacking.

The dates to watch are EMIB-T customer designs within a year or two, hybrid bonding in HBM5, glass core substrates late in this decade, and qualification of the 9-reticle CoWoS from Part 5 in 2027.

In this guide’s reading, the front-end scanner still sets the finest lines on any chip, but the package now decides how many chips work together and how much memory sits beside them. That ends this series. Part 1 starts it with one layer of a chip, and the series index lists all six parts.