Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar

Resistive memory has reached products, mostly small ones, and the grid of wires around its cells can do arithmetic that so far only laboratory chips do. Part 4 covered ferroelectric memory, after NOR, phase-change memory and MRAM in the Beyond NAND series.

The memory map gave resistive memory one section with a cell that switches, a grid of wires, and a problem with sneak currents. This part opens each of those up. I want to know why a cell this simple has been so hard to turn into dense memory, and what the same array can do instead. You can run the same circuits in a browser in the Crosspoint Lab, and this guide links its chapters where they match.

Forming a filament

Two electrodes and an oxide

A resistive memory cell is an insulating layer between a top and a bottom electrode, and it is often called RRAM or ReRAM. In Ielmini’s review, that insulator is usually a metal oxide. Each cell stores a bit as a resistance. A low-resistance stateThe low-resistance state is the resistive cell state that passes current easily, and it usually stores a one. reads as one value and a high-resistance stateThe high-resistance state is the resistive cell state that passes little current, and it stores the opposite value to the low-resistance state. as the other. Moving from high to low is a set, and moving back is a reset. Tantalum oxide and hafnium oxide are named as the leading oxides in the IEEE roadmap.

Cells also differ in how they are driven. In unipolar switchingA unipolar cell sets and resets with the same polarity, told apart by the height and length of the pulse, as phase-change cells are., set and reset use the same polarity. In bipolar switchingA bipolar resistive cell sets with one voltage polarity and resets with the opposite one, as most oxide resistive cells do. they alternate. A unipolar cell is simpler to drive, but it typically shows lower uniformity and shorter cycling endurance than a bipolar one, according to Ielmini’s review.

The first breakdown

A new cell does not switch yet. It needs a one-time step called forming, which creates a conductive filamentA conductive filament is a thin path that forms through the insulating layer of a resistive cell when it sets and breaks when it resets. through the oxide by dielectric breakdown. Current is limited during forming. Ielmini’s review says that limit sets the size of the filament and keeps the breakdown from destroying the cell. The IEEE roadmap puts set and reset at much lower voltages after forming.

Reset does not remove the whole filament. It opens a small gap in it, so the high-resistance state after a reset still conducts better than the fresh cell did before forming. A set closes the gap again. Every switching event after forming works on that small gap, not on the whole oxide.

Figure 5.1 follows one cell through those three steps, with the voltages one published array uses for each.

Forming has costs of its own. Lanza and colleagues report that smaller cells need higher forming voltages, and that the spread in forming voltage spreads the size of the filaments that result. Two changes to the stack lower the voltage. A reactive metal cap layer pulls oxygen out of the oxide and leaves vacancies behind, which makes forming easier, Ielmini explains. Thinning the oxide helps too. According to Dittmann and colleagues, stacks with 2nm of hafnium oxide under a hafnium cap can skip forming entirely, but they leak more and their resistance window shrinks.

Two kinds of filament

Resistive memory comes in two families, set by what the filament is made of. Waser and Aono drew the line in a 2007 review. One family is cells in which metal cations migrate and grow metal filaments, and the other is cells in which anions migrate and leave conducting paths of sub-oxide.

Valence-change memoryValence-change memory is a resistive memory in which oxygen vacancies move under the electric field and change how well an oxide layer conducts. is the second kind. Its moving ions belong to the oxide itself, and Dittmann and colleagues describe them as usually oxygen vacancies. Electrochemical-metallization memory is also called conductive-bridge RAM (CBRAM). In it one electrode is an active metal such as silver, copper or nickel and the other is inert, such as tungsten, tantalum, ruthenium or platinum. The IEEE roadmap says that active metal supplies the ions that build a metal bridge across the switching layer.

Both families reached products. Tantalum oxide is a valence-change system, and per Dittmann and colleagues Panasonic released the first commercial tantalum-oxide filamentary product in 2013, a microcontroller with embedded resistive memory (listed under parts you could order). CBRAM parts later in this guide are electrochemical. Results on variation and noise in the next section come from both.

The current limit sets the state

During a set the resistance drops abruptly, so the current has to be capped at a compliance level. That cap decides how thick the filament grows and so how low the resistance goes, as Ielmini explains. Balatti and colleagues found that in silicon-doped hafnium-oxide cells the low-resistance value is set mainly by the compliance currentCompliance current is a cap on the current a resistive cell may pass while it sets, which stops the filament growing and helps fix how low the resistance ends up. of the set.

That gives a way to store more than one bit per cell. One tantalum-oxide example in Ielmini’s review used seven compliance currents between 30µA and 300µA to produce seven low-resistance states. With the high-resistance state that makes eight levels, or 3 bits per cellA cell storing n bits needs 2 to the power n voltage levels: two for SLC, four for MLC, eight for TLC and sixteen for QLC..

Real voltages depend on the stack, so one array has to stand for the rest. Hirtzlin and colleagues built a kilobit hafnium-oxide array on 130nm CMOS. Forming there is a single ramp from 0V to 3.3V at 1,000V/s with a 200µA limit. Set uses 2V with a limit between 20µA and 200µA, reset uses 1.5V to 2.5V, and pulses last 0.1µs to 100µs. Other stacks use other numbers, and no single range covers them all.

Why two identical cells disagree

Flash stores a bit as charge, and the cell’s structure largely stays the same from one write to the next. A resistive cell rebuilds part of its structure every time. Each set reconnects the filament and each reset breaks it, so every cycle leaves a different number and arrangement of defects in the gap, Ielmini explains. Lanza and colleagues add that forming and rupturing a filament is a random process, and large cycle-to-cycle variation is built into the device physics.

There are two kinds of spread. Cycle-to-cycle variation is one cell landing somewhere different each time it is written. Device-to-device variation is the fixed difference from one cell to the next. Variation grows as the write gets gentler. In hafnium-oxide cells, parameter variations grow markedly when the compliance current falls from 80µA to 8µA, according to Ielmini’s review. Relative spread also grows with resistance, so the high-resistance state is the wider of the two. Low states are often reported as normal distributions and high states as log-normal, according to Dittmann and colleagues.

Figure 5.2’s left panel shows why the median is a poor guide. Lanza and colleagues describe one published example with a median on/off ratioThe on/off ratio is how many times more current a low-resistance cell passes than a high-resistance one at the same voltage. A bigger ratio makes reads easier. of about 100x that still left no window between the tails of the two distributions. Its right panel shows what that costs in a real array. After 100 writes of the whole array, the kilobit hafnium-oxide array of Hirtzlin and colleagues had two distributions that overlapped at three standard deviations. With one transistor and one resistive cell per bit (1T1R), that spread would give a bit error rate of 1.2%. Storing each bit as a set cell and a reset cell and comparing them (2T2R) would cut it to 0.2%. That second cell doubles the area to buy the reliability.

Read noise

A cell that holds its state is still noisy when read. Random telegraph noise makes the read current jump between two levels at random, the same noise flash meets as a worn cell that flickers. Ambrogio and colleagues attribute the noise in a resistive cell to a single trap at or near the surface of the filament that charges and discharges. In hafnium-oxide, nickel-oxide and copper-based cells, the relative size of the jumps grows with resistance up to about 100kΩ and then levels off near half the resistance in high-resistance states.

Noise is harder to fix than variation. A program-verify loop can place a cell inside a target range, but the same authors’ paper on noise-induced resistance broadening finds that read noise can hardly be predicted or corrected that way. One hafnium-oxide study reviewed by Dittmann and colleagues found that cells verified below 20kΩ and above 200kΩ relaxed within 1s, and the two distributions overlapped again.

The low-power trap

The obvious way to save power and area is a gentler write, and it backfires. Filaments formed and switched at low power give lower on/off ratios, are more sensitive to small variations and hold their state worse, Dittmann and colleagues report. The same trade shows from the embedded side. In Ielmini’s review, the size of the conductive filament sets how low the write current can go, and the same size controls retention, noise and variability, a trade-off between reliability and low-current operation. Cutting the write current to shrink the access transistorAn access transistor is the switch that connects one memory cell to its bit line when the cell’s word line rises, so only the selected row is read or written. costs retention.

Noise as a feature

Variation is usually something a memory designer fights. For some resistive memories the same randomness is the product. Both kinds of spread above are useful. Cycle-to-cycle variation makes random numbers. Device-to-device variation makes an identity, because no two arrays come out alike.

Both work when programming is noisier than reading. Program a cell again and again and it gives a wide spread, which is a coin flip. Program it once and read it again and again and it gives a narrow one, so a pattern set once reads back the same way every time.

Two random-number schemes show the idea. Balatti and colleagues program an oxide cell to high resistance, then apply a set pulse chosen so the cell switches about half the time, and read the outcome as the bit. A second scheme uses a silver-in-oxide diffusive memristor that switches to low resistance after a random delay once a pulse starts, and relaxes back on its own. A counter running during the delay gives the bit, and the bits from Jiang and colleagues’ device passed all 15 NIST randomness tests with no post-processing.

Fingerprints use the fixed differences. A physical unclonable function maps a challenge to a response that only one physical chip produces. Sneak-path currents in a resistive crossbar differ from chip to chip, and Gao and colleagues build the response from them. In their design the way the sneak paths entangle raises the entropy and widens the set of challenge and response pairs. A different design from Nili and colleagues does not rely on sneak paths. It builds the function from the analogue tuning and nonlinear conductance variations of the memristors. Sneak paths are a read error in the next section, but in the first design they are the signature.

Noise can also help a computation. A Hopfield network settles by lowering an energy function, and without noise it can settle on a poor answer. In work from Hewlett Packard Labs and collaborators, a memristor Hopfield network solved max-cut problems in a crossbar by harnessing the intrinsic hardware noise, with a feedback algorithm that amplifies or dampens that noise. All of this is laboratory work, and none of it is a product.

The sneak path and the selector

A crossbar puts a cell at every crossing of a grid of word lines and bit lines, with nothing else in the cell. Having nothing else in the cell keeps the grid dense and also causes the problem. To read one cell, a voltage goes across its word line and its bit line. Current also finds other routes: through a neighbor on the same word line, along that neighbor’s bit line through a second cell onto another word line, and back through a third cell onto the selected bit line. Those sneak paths add current to the read, and a selector exists, the IEEE roadmap says, to minimize exactly that leakage through unselected paths.

The Crosspoint Lab solves that circuit exactly, using teaching values: cells of 10kΩ and 1MΩ and a 2V read. It reads each state against the background that hurts it most. With bare cells and the idle lines left floating, the read marginRead margin is how far apart a low-resistance read and a high-resistance read stay once the worst-case neighbors are counted. When it reaches zero the two cannot be told apart. is 99% for one cell, 66% for a 2x2 array and 20% for 3x3. From 4x4 on it is 0%, and the array can no longer tell the two states apart. These values are illustrative and measure no device. They show the steep drop the lab’s model gives for a bare floating array.

Holding the idle lines

One response is to drive the unselected lines instead of leaving them floating. Two common schemes were described for writes, and the lab applies them to reads too. Under V/2 biasing the idle lines sit at half the voltage, so any cell sharing a line with the target (a half-selected cellA half-selected cell sits on the selected row or column but is not the cell being accessed, so it sees part of the applied voltage.) sees half of it. Under V/3, unselected word lines sit at a third of the voltage and unselected bit lines at two thirds, so every half-selected cell sees only a third. But every fully unselected cell also sees a third, in reverse, where V/2 leaves it near zero, so V/3 pays off only with a highly nonlinear selector, as Ciprut and Friedman show.

Figure 5.4 shows that biasing alone does not rescue a bare array. At 3x3, V/2 reads 0% and V/3 reads 33%. At 16x16 both read 0%. Only the arrays with a selector or a transistor in every cell hold 99% at both sizes. Chapters in the lab on growing the array, holding the idle lines and making idle cells block step through each case.

What goes in the cell

One-transistor one-resistor (1T1R) cells put a transistor in every cell and remove sneak paths outright. The cost is area. With a planar transistor the cell takes 6F² to 8F² and a transistor selector is generally unsuitable for 3D memory architectures. A two-terminal selector keeps the cell at 4F² and lets decks of crossings stack, per the roadmap.

Roadmap targets show how narrow that job is. A selector should pass about 1µA when selected, so the read is fast, and block well enough for an on/off ratio of 10⁷ to 10⁸ across a block of 10³ to 10⁴ lines. Leakage during a write is just as tight. Say a tile of 2,000 by 2,000 cells, about 4 million, is programmed at 100µA. During a program the whole tile leaks at once. If every unselected cell leaks the same amount and the total must stay below the programming current, each cell may leak only about 25pA, which is 100µA divided by 4 million. That figure illustrates the scaling and is not a spec for any product.

The roadmap sorts selectors into several families: transistors, diodes, threshold switches, and nonlinear devices such as tunnel barriers, mixed ionic-electronic conductors and complementary structures. A diode blocks in one direction, so it suits only unipolar cells. A bipolar cell needs a selector that conducts both ways. A threshold switch collapses to low resistance above a threshold voltage and recovers once the voltage falls below a hold voltage. Since 3D XPoint was announced in 2015, threshold switches have been among the most researched selectors, though they face limits in cycling endurance and in balancing voltage between the switch and the memory element, according to the 2022 roadmap. A teardown later found one at each Optane crossing, as Part 2 describes.

Two designs drop the separate selector. A complementary resistive switchA complementary resistive switch puts two cells back to back so the idle pair always reads high resistance. Reading destroys the stored value, which must then be written back. puts two bipolar cells back to back, so both stored states read as high resistance and sneak current stays low. Linn and colleagues proposed it for large passive crossbars in 2010. Reading carries the price. Reading a stored 1 switches the cell, so that read must be followed by a write back, though non-destructive read schemes have been proposed, the roadmap notes. Other cells select themselves through their own nonlinearity or self-rectification, according to the same roadmap.

A crossbar as a multiplier

Sneak paths exist because the array is a circuit of resistors. Read on purpose, that circuit does arithmetic. Store a weight in each cell as a conductance and put a voltage on each row. Each cell passes a current equal to its conductance times the voltage across it, which is Ohm’s law, and with each column held at 0V by its readout circuit that voltage is the row voltage. Currents on each column add, which is Kirchhoff’s current law. Current out of each column is a weighted sumA weighted sum multiplies each input by its own weight and adds the products. Most of the work in a neural network layer is weighted sums. of the inputs, and one read of the array gives a whole matrix-vector multiply, as Li and colleagues described in 2018.

A conductance cannot be negative, so a signed weight takes two cells, and the weight is the difference between their conductances.

Figure 5.5 works one array through. The first column’s 15µA is 100mV times 10µS, plus 200mV times 40µS, plus 300mV times 20µS. All nine multiplications and all six additions happen at once, in the time a single read takes. These values are illustrative. Run the same sum on a solved circuit in the Crosspoint Lab’s “Rows in, columns out” chapter.

The converters around the array

The array works in analog while the processor around it does not. Inputs pass through digital-to-analog converters and outputs through analog-to-digital converters (ADCs), and those take more power and area than the array. Shafiee and colleagues’ ISAAC was a simulated accelerator design. It fed inputs one bit at a time through 1-bit converters, stored 2 bits per cell in 128x128 arrays and read the columns with 8-bit ADCs. Even so, the ADCs took 58% of tile power and 31% of tile area.

Hewlett Packard Labs’ Dot-Product Engine study, by Hu and colleagues, reached the same conclusion from the other side. In simulation it matched software accuracy on handwritten digits, 99%, with only 4-bit converters. With 8-bit converters at 10MHz and 100µW per channel, the converters and amplifiers took over 90% of the power and over 95% of the area.

What has been built

Demonstrations have grown from a handful of cells to millions. Prezioso and colleagues built an integrated 12x12 metal-oxide crossbar with no transistors and trained it to sort 3x3-pixel black-and-white images into three classes, with two memristors per weight. Li and colleagues in 2017 ran analog matrix-vector products on hafnium-oxide 1T1R arrays of up to 128x64 cells, with 5 to 8 bits of output precision and 99.8% device yield. On a 128x64 array, a two-layer network trained in place by Li and colleagues in 2018 reached 91.71% on handwritten digits shrunk to 8x8 pixels, with 11% of its devices not responding to updates. Yao and colleagues built a five-layer convolutional network from eight 2,048-cell arrays that scored over 96% on the same digits.

Wan and colleagues’ NeuRRAM is the largest so far. It has 48 cores, each with a 256x256 resistive array and 256 neuron circuits that double as ADCs, for 3 million resistive devices built on CMOS. Measured entirely on the chip, it scored 99.0% on handwritten digits and 85.7% on CIFAR-10 images, comparable to software models with 4-bit weights.

Not every analog result uses a resistive cell. IBM’s mixed hardware-software training experiment, run by Ambrogio and colleagues, combined phase-change memoryPhase-change memory stores data in a material that switches between a crystalline, low-resistance state and an amorphous, high-resistance state when heated. with capacitors across up to 204,900 synapses and matched software accuracy, and its efficiency of 28,065 billion operations per second per watt is a calculated figure, not a measured one. Most of these results are small image-classification tasks, and none is a product.

What spoils the answer

Each column current in Figure 5.5 is exact only in an ideal circuit. The wires, the devices and time all pull a real array away from it. Studies at the end of this section measure them together.

Wires

Every segment of wire between crossings has resistance, so the voltage a far cell sees is lower than the voltage at the driver. A 2020 simulation by Joksas and colleagues, built from a measured 128x64 tantalum and hafnium-oxide crossbar, found that line resistanceLine resistance is the resistance of the word and bit lines themselves, which drops voltage along the line and weakens cells far from the driver. lowered output currents by about 12% at the outputs nearest the drivers and about 16% at the farthest bit lines.

Bigger arrays make it worse. Gokmen and Vlasov proposed a 4,096x4,096 training array that allowed at most a 10% voltage drop along a line and needed devices of about 24MΩ to keep the currents small. Its 4,096 ADCs would take 104mm² and 1W, against 2.68mm² for the array itself. Sharing each ADC across 64 columns cuts that area to 1.64mm² at the same 1W, and all of these numbers are calculated.

Devices

Real cells are not perfect resistors. In Hu and colleagues’ Dot-Product Engine simulation the nonlinearity of the cells’ current against voltage contributed about 80% of the total noise, shot noise about 15% and thermal noise about 5%, with telegraph noise left out. Weight updates are lopsided too. In Prezioso and colleagues’ crossbar, a set pulse at 20µS raised the conductance by about 60µS while a reset pulse lowered it by only about 5µS, and at 65µS the steps were about +24µS and -55µS. Memory and Storage for SI, Part 1 follows those lopsided steps into training.

Some cells stop moving at all. In a measured 128x64 tantalum and hafnium-oxide array, a 2022 paper by Joksas and colleagues classed 10.1% of devices as stuck, with a switching range under half the median. Training in place can work around stuck cells. In Li and colleagues’ 2018 simulation, a network trained on the array still reached over 60% accuracy with half its devices stuck at low conductance, while weights trained offline and then loaded lost accuracy quickly as defects rose.

Time

A programmed conductance does not stay put. Phase-change conductance drifts, for the reason Part 2 explains, as a power of time, with an average drift exponent of about 0.06 in IBM’s devices. Joshi and colleagues report that with a network’s weights programmed on phase-change devices and no compensation, accuracy on CIFAR-10 fell from 93.75% to 10%, random guessing, within about 1,000s. With global drift compensation it stayed above 92.6% for a day. The cell itself can be changed instead. A projected phase-change cell from Koelmans and colleagues cut the drift exponent about 22-fold, from about 0.067 to about 0.003.

Resistive cells relax instead of drifting. On Wan and colleagues’ NeuRRAM chip, conductance spread after programming averaged about 2.8µS, and three write-verifyWrite-verify writes a cell, reads it back and writes again until the value is close enough to the target, spending time and energy for a tighter result. passes cut it to about 2µS, a 29% reduction. Write-verify into a window of ±1µS placed 99% of cells, at an average of 8.52 set or reset pulses per cell. Every one of those pulses is time and energy spent before the array computes anything.

All at once

Three studies measured the effects together. Each then tried to win the accuracy back.

Figure 5.6 puts three studies side by side. With faulty devices, device variationDevice variation is the spread between cells meant to hold the same value, both from cell to cell on one chip and from chip to chip. and line resistance together, median accuracy on handwritten digits fell from about 95.9% to about 91.0%. A committee of five networks brought it back to about 95.7%, in the 2020 Joksas study. On NeuRRAM, voltage drop that grew with many cores running at once left a CIFAR-10 network at 83.67%, 3.36 points below its 4-bit software model at 87.03%. Fine-tuning part of the network with the chip in the loop improved the result by 1.99%, to the 85.7% quoted above, the NeuRRAM paper reports.

That pattern holds across all three. Each study recovers most of the loss, and each fix costs something. The costs are five networks instead of one, a compensation step, write-verify pulses, or training that knows the hardware’s faults. The 2022 Joksas paper built simulations from measured silicon-oxide devices. With highly nonlinear, high-resistance devices, ordinary training gave a median error of 41.6%. Training that modeled those faults cut it to 9.1%, and to 7.1% with regularization, against a median error of 4.6% for a digital network of the same size. Lab chapters on what spoils the sum and working around the damage show each effect on one array.

Where it stands

Three kinds of product matter here. One is a part you could order, one is a foundry process qualified for customers’ chips, and one is research.

Parts you could order

The 2020 IEEE roadmap says a CBRAM-based serial memory product became commercially available in 2012. Adesto’s CBRAM products (the Mavriq and Moneta families) were made on 130nm wafers by Altis Semiconductor, per its 10-K annual report. Panasonic said in February 2017 that it began resistive memory mass production on a 180nm process in 2013 and was supplying the 8-bit MN101LR microcontroller series with it.

Fujitsu’s 4Mbit MB85AS4MT is the densest standalone part covered in this guide, and Fujitsu called it the largest-density mass-produced resistive memory when launching it in October 2016, co-developed with Panasonic. Its datasheet lists a 524,288 by 8-bit memory on a 5MHz serial (SPISPI is a simple serial bus of a clock, a chip select and data lines. Serial NOR and NAND flash chips use it, often in dual or quad data modes.) bus, 1.2 million rewrites per byte, and 10-year retention at 85°C. It is a small serial memory, nowhere near drive scale.

Processes qualified for customers’ chips

As of October 2026, resistive memory is also offered to chip designers as a foundry process. TSMC says it led in mass-producing embedded resistive memory on its 22nm ultra-low-leakage process. Its 2022 annual report says several customers qualified products on its 22nm and 28nm resistive memory and started volume production that year, though TSMC does not name the customers’ products. The 2025 report says its 40nm, 28nm and 22nm nodes entered volume production and a 12nm generation passed consumer-grade qualification.

In November 2022, Infineon and TSMC announced resistive memory for Infineon’s AURIX TC4x automotive microcontrollers, with first 28nm samples promised to customers by the end of 2023. Infineon’s knowledge-base article of September 9, 2026 lists the TC48x and TC45x devices as RRAM-based, and Beyond NAND, Part 1 uses it for their retention and endurance targets. Weebit Nano licenses resistive memory as IP. In June 2023 it announced that its module in SkyWater’s S130 process was qualified with a 256Kb array, 10,000 cycles, 10-year retention at industrial temperatures and three solder reflows. It later reported qualification in DB HiTek’s 130nm process, and as of January 2026 it expected its first customer product tape-out that year. These are processes and IP that you can’t buy as parts on their own.

Research

Large chips stayed at conferences. The memory map covers the 32Gb and 16Gb resistive chips shown at the International Solid-State Circuits Conference (ISSCC) in 2013 and 2014. Crossbar Inc. came out of stealth in 2013 with a working array made at a commercial fab and a target of up to 1TB on a 200mm² chip, a goal and not a product. Intel showed a 3.6Mb embedded macro at 10.1Mb/mm² in its 22nm FinFET process at ISSCC 2019. NeuRRAM is the compute chip above, and it was built in a 130nm foundry process.

Figure 5.7 sorts every item in this section by year and by lane. Parts you could order sit in a short lane that stops at a few megabits. Activity is in the qualified-process lane, at 130nm down to 12nm, inside microcontrollers and other logic chips.

Resistive memory found its work on the logic die, where a cell built in the wiring layers is an alternative to the embedded flash that stopped fitting. It did not replace NAND as storage. Computing in the crossbar is further back, and it continues in Memory and Storage for SI, Part 1, which follows the lopsided weight updates from this array into training.