Photolithography, Part 3: High-NA EUV and What It Means for Memory

Part 2 followed the resolution equation to extreme ultraviolet (EUV) light, which reached volume production in 2019 with a numerical aperture (NA) of 0.33. High-NA EUV takes the NA to 0.55 and charges for the step with a lens that shrinks the image more one way than the other and an exposure field half the old size. In memory, DRAM makers moved to EUV to cut multi-patterningMulti-patterning splits one complex layer pattern into simpler patterns exposed separately. Litho-etch-litho-etch (LELE) prints and etches in turn, while self-aligned double and quadruple patterning (SADP, SAQP) build sidewall spacers by deposition and etch from a pre-pattern of lines. steps and get more chips from each wafer, while 3D NAND scaled by stacking and stopped needing the finest resolution. Fab Tracker holds the dated history of each tool.

A wider cone and an anamorphic lens

High-NA EUV raises the numerical aperture from 0.33 to 0.55. In ASML’s account, that takes the critical dimensionThe critical dimension is the size of the smallest feature a lithography system can print. The two main ways to reduce it are a shorter wavelength of light and a higher numerical aperture. (CD) from 13nm on its NXE scannersA scanner is a lithography tool that moves the mask through a narrow slit of light while the wafer moves the opposite way in step, so only a small part of the pattern is exposed at a time. ArF immersion and EUV tools are scanners. to 8nm on the new EXE platform, so transistors can be 1.7 times smaller and packed 2.9 times more densely.

A higher NA needs bigger mirrors, and bigger mirrors send light onto the maskA photomask, also called a reticle, is the template that carries the circuit pattern for one layer, and light is projected through it to transfer that pattern onto the wafer. An EUV mask works by selectively reflecting or blocking light. at steeper angles. At the larger angle the multilayer mask loses its reflectivity, and the pattern no longer transfers. Shrinking the image 8x instead of 4x would have eased the angle, but at 8x in both directions a standard mask would cover only a quarter of today’s field (13 × 16.5mm by the arithmetic), and chipmakers would have needed larger masks. ASML’s answer was anamorphic optics, which demagnify by 4x in one direction and 8x in the other. The angle at the mask comes down, and the mask stays the size the industry already makes.

High-NA pays for this with the field. A standard scanner prints a 26mm by 33mm field on the wafer, while High-NA with today’s masks prints 26mm by 16.5mm, which is half the area, by the figures in the 2025 lithography chapter of the IEEE International Roadmap for Devices and Systems (IRDS). Every wafer needs twice as many exposures. The higher NA also leaves little depth of focusDepth of focus is the range of focus error a lithography process can tolerate and still give acceptable results. In high-NA EUV it shrinks as numerical aperture rises, which makes the process more sensitive to focus errors. and makes edge placement error harder to control, and the roadmap sets High-NA targets of roughness below 1nm and overlay of 1.6nm or better.

Half a field

Twice the exposures could have meant half the wafers an hour. ASML answered with faster stages. The EXE wafer stage accelerates at 8g and the reticle stage at 32g, which are twice and four times the NXE’s, by ASML’s figures. The EXE:5000 prints more than 185 wafers an hour, on a roadmap to 220. Intel got the first EXE:5000 and quotes the second-generation EXE:5200B at more than 200, and ASML’s July 2026 release says Intel was the first to install the 5200B and pass its acceptance tests.

Big chips feel the half field most, though in the roadmap’s count very large dies are only a small share of advanced logic. A die larger than a half field has to be printed in two exposures stitched togetherStitching prints a chip too large for one exposure field as separate exposures that meet at a boundary, which needs tight overlay and size control where they join., with tight control of overlayOverlay is how well one printed layer is aligned with the layer before it, and an important measure of lithography performance. and CD where they meet, unless an exclusion area is left between them. Swapping two masks for each wafer also costs throughput.

Early results are good. In a 2024 imec and ASML report cited by the IRDS, stitching needed black border placement below 30nm on the mask, and the measured accuracy was 8 to 12nm, about a third of the budget. Customers can use High-NA with the current 6-inch mask by floor-planning chips to fit the half field or with Intel’s stitching tools, Intel and ASML say.

A bigger mask is the longer fix. A proposed format of 152.4mm by 284.4mm (about 6 by 11.2 inches) would restore the full 26mm by 33mm field at 8x and the roadmap says it would also enable higher throughput on both High-NA and standard EUV tools. Every route to bigger chips is expensive in the roadmap, from stitching and larger masks to chiplet packaging. The roadmap says making a larger mask needs no fundamental change in mask-making technology, only new tools and infrastructure, but some key parts still lack committed support from at least one company, and 2028 is the earliest it could arrive. Intel has spent more than three years pushing the industry toward it, the two companies say.

A 12-inch mask industry initiative has since formed to work on the larger format. NY CREATES said in a release that it joined, and that industry leaders are exploring a 6-by-12-inch mask format so larger areas of a chip print in a single exposure without stitching. That is a different figure from the roadmap’s proposal of about 6 by 11.2 inches, and neither source says the two are the same format. TheElec reported that Samsung is joining an ASML-led consortium to move photomasks to 300mm. Electronics Weekly, describing an ASML and TSMC announcement, reported that High-NA will be adopted for production on the current 6-inch masks.

A third option is not to make big dies at all, but to build systems from smaller chips joined in a package, which is where Part 5 begins.

Bigger in every direction

High-NA grew most in its optics, and ZEISS, which makes them, puts the illumination system at about 6 metric tons, four times its NXE counterpart, and the projection optics at about 12 metric tons in more than 40,000 parts, seven times the volume and weight. Each mirror still carries more than a hundred layers, is about twice the size and ten times the weight of an NXE mirror, and takes about a year to make. Measuring the mirrors needed a new instrument of about 150 metric tons in a vacuum chamber 5 meters across.

ASML shipped the first modules of the first High-NA system, an EXE:5000, to Intel in December 2023, after about a decade of development. Intel completed installing it at its D1X fab in Hillsboro, Oregon, in April 2024. It came in more than 250 crates in 43 freight containers and weighs more than 150 metric tons. ASML printed the first 10nm dense lines on High-NA that year.

Intel points to one benefit beyond resolution. A higher NA adds image contrast for the same feature, so a layer can need less light and print faster.

Intel said in April 2024 that it expected to use both 0.33 NA and 0.55 NA EUV alongside other lithography processes, the same mix of generations Part 1 described for DUV. Production followed in 2026. In July, ASML said that Intel had entered high-volume manufacturing of some Core Ultra Series 3 processors (code-named Panther Lake), with specific Intel 18A layers dual-qualified on High-NA at yieldsYield is the share of chips on a wafer that work. Chipmakers raise it by measuring each step and catching defects early. matched to the NXE platform. By September 2026 more than one million wafers had gone through High-NA tools across certification, development, and production, Intel and ASML said. Also in September 2026, imec described lines and spaces down to 22nm pitch and vias at 28nm center-to-center distance after a single exposure of a chemically amplified resist on a High-NA tool. The work was for logic. Commercial Times reports that TSMC plans to use High-NA in volume production of advanced processes from 2030.

After High-NA

Beyond 0.55, the IRDS looks in two directions. One is hyper-NA at 0.75 or more. It would reuse much of the existing source, mask, and optics infrastructure, but needs even larger mirrors, an even smaller depth of focus, and polarized light that today’s tin sources do not make. Polarizing today’s light would cut the light reaching the wafer by more than half.

A shorter wavelength is the other path, around 6 to 7nm, sometimes called beyond EUV. That would need new plasma fuels or a free-electron laser, new mirror coatings, and new resistsPhotoresist is the light-sensitive coating on the wafer. Exposure changes how easily it dissolves in the developer, so the develop step washes away the exposed or the unexposed part and leaves a mask for later etching.. It would give more depth of focus than hyper-NA at the same resolution, but would need about twice the energy delivered to the wafer to keep the same photon shot noise. Large accelerator facilities (free-electron lasers or synchrotrons) are the only alternative sources the IRDS sees as still pursued in earnest, and the roadmap adds that one free-electron laser could power multiple scanners at once.

By the roadmap’s estimate, 0.55 NA reaches about a 16nm minimum pitch in a single exposure. The roadmap sets early manufacturing use of High-NA for 2027, while the July 2026 ASML release above describes Intel already in high-volume manufacturing of some products with High-NA layers.

IRDS authors expect the industry to choose between the paths within a few years, on the economics of the source and the patterning gains each offers, and the choice must keep edge placement error and throughput at least as good. Multiple patterning and High-NA together already meet the roadmap’s resolution needs through 2029 and should extend to 2033. The pressure is shifting from resolution to the stochastic defectsA stochastic defect is a random, isolated printing failure, such as a missing or merged feature. At EUV wavelengths only a few photons create the pattern, and the molecular nature of the resist and chance in how light and resist interact add to the randomness. and edge placement that Part 2 described.

Printing without light

Not every path runs through optics. In Canon’s description, nanoimprint lithography (NIL) presses the pattern into the resist like a stamp. A low-viscosity resist is jetted onto the wafer field by field, the patterned mask is lowered into it and the liquid flows into the mask’s relief by capillary action, ultraviolet light cures the resist, and the mask is lifted away. Canon says the technique reproduces the mask’s patterns faithfully and reaches circuits as small as 10nm at lower cost than photolithography, which projects its patterns through lenses.

Canon has worked on NIL since 2004 and bought Molecular Imprints in 2014. In July 2017 it supplied an FPA-1200NZ2C tool to Toshiba Memory’s Yokkaichi NAND plant, toward what it called the first memory mass production with the technique. Canon launched the FPA-1200NZ2C commercially in October 2023, rating it for a minimum linewidth of 14nm and expecting 10nm with better masks, and said in September 2024 it would ship one to the Texas Institute for Electronics. In the roadmap, NIL is being evaluated as an alternative patterning method, with defects and overlay as the key parameters.

Directed self-assembly also appears in the roadmap. Block copolymers separate into regular lines or holes on their own, guided by a template etched from a fast, low-dose EUV resist pattern. The polymer sets the pitch and smooths the edges, so it cleans up an EUV print rather than replacing it, with reported 18nm-pitch lines and roughness as low as 1nm at 24nm pitch. Maskless direct-write electron beam lithography belongs to packaging in the IRDS, where Part 5 picks it up.

DRAM: the capacitor and the EUV turn

A DRAM cell is a transistor and a capacitor, and the capacitor is the problem. In modern DRAM it has almost no room left to shrink in area, by the IRDS reading. That constrains every other way of shrinking the cell. Samsung’s release on its first 10nm-class DRAM in 2016 describes very narrow cylinder-shaped capacitors stacked on top of transistors a few dozen nanometers wide, more than eight billion cells on one die. Samsung made that node without EUV, using ArF immersion with quadruple patterning, and claimed more than 30% better wafer productivity than its 20nm DRAM.

EUV entered DRAM in 2020. In March, Samsung said it had shipped one million DDR4 modules built on its first 10nm-class (D1x) node with EUV. Samsung called it the industry’s first EUV DRAM and said that EUV cuts the repeated steps of multi-patterning and improves patterning accuracy. Its 14nm node followed in 2021 with five EUV layers, raising wafer productivity by about 20%. SK hynix began mass production of its 1a DRAM with EUV in July 2021, after partial use on its 1y node, and expected 25% more chips per wafer than its 1z node. Micron’s 1γ node sampled in February 2025. It uses EUV and delivers more than 30% more bits per wafer than 1β.

This guide’s reading of these releases is that EUV mostly made DRAM cheaper by replacing long multi-patterning flows. Part 2 described the same pattern for logic. Every maker frames its EUV node by output per wafer, with gains from 20% to more than 30%, though Samsung adds that its 14nm node was not possible with ArF alone.

High-NA is now headed for DRAM too. TheElec reported that Samsung plans to be the first in the industry to bring ASML’s High-NA EUV tools into advanced DRAM manufacturing by 2028. StorageReview wrote that Samsung and ASML announced the plan on September 8, 2026, for high-volume DRAM manufacturing by 2028, and that the two companies call it the first such deployment in the industry. TheElec and StorageReview are secondary reports, the ASML release is the primary one, and 2028 is the target year. Both firsts are the companies’ own words. SK hynix said in September 2025 that it had assembled the industry’s first High NA EUV system for mass production. The system is an EXE:5200B at its M16 fab.

Micron put High-NA on its own DRAM roadmap at its October 2026 technology webinar, marked directional, with no dates implied and node names and phases subject to change. Micron targets its next node, 1δ, to ramp in the second half of 2027 in the US, with a bit density improvement in the mid-20s percent over 1γ. High-NA sits two nodes later, on the node after 1ε, which Micron’s slide shows in early development. Those slides also list a 5 to 10 year investment in an advanced lithography partnership with Albany NanoTech and NY CREATES, which they say will accelerate Micron’s High-NA EUV and lithography roadmap.

What comes next may lean on lithography less. The IRDS roadmap shows three routes. One moves the complementary metal-oxide-semiconductor (CMOS) circuits above or below the cell array, one uses vertical transistors that shrink the cell from 6F² to 4F², and one is 3D DRAM that turns the capacitor on its side and stacks cells in tall layers, much as NAND did. None of them mainly needs finer resolution. Micron has already set one aside. It says it will stay with 6F² cells and not pursue 4F², citing increased complexity and cost after more than two decades of investigation with no viable scaling path, and it is developing 3D DRAM instead. Overlay is likely to be the bigger challenge, in the IRDS view, especially in HBM, where wafers are thinned and bonded before later layers are printed on them and bonding distortion eats into the overlay budget.

3D NAND: scaling by stacking

Planar NAND was the clearest case of lithography setting density. In planar NAND, Lam Research wrote in 2017, lithography determined how many cells fit on a die, and scaling beyond about 15nm ran into cell-to-cell interference, dielectrics that would not scale, and leakage. 3D NAND changed the axis. Instead of shrinking cells across the wafer, it stacks them, and as Lam puts it, 3D NAND is enabled by deposition and etch rather than lithography.

From the lithography side, the roadmap reaches the same point that Part 1 noted. Flash now scales with 3D structures that have relatively large critical dimensions, and it does not need higher-resolution patterning to make progress. In a 2016 interview, Lam’s Harmeet Singh described 3D NAND as 40nm devices and said one customer had reported hole diameters were not shrinking, and would not until stacking reached some limit. Layer count grew instead. Lam wrote in 2017 that production ran from 32 to 48 pairs, with more than 60 pairs beginning to ramp. Lam’s July 2024 article refers to the move to 232-layer 3D NAND and sets a goal of 1,000 layers by the end of the decade. The NAND layer race tracks each maker’s count.

Etch took over the hard steps. Lam called the channel hole etch the most critical step in 3D NAND. Each wafer gets more than a trillion holes etched at once, each with an aspect ratio over 40:1, where the deepest etch in planar NAND was under 15:1. Each hole must keep the same diameter from top to bottom without bowing or twisting. Lam’s newer memory-hole etch runs at cryogenic temperatures, which it calls essential for scaling to higher layer counts. Flash Foundations covers the cells those holes become.

Stairs, holes, and bonded wafers

Lithography still matters in 3D NAND, but in different places. Each word line in the stack needs its own contact, so the edge of the stack is etched into a staircase with one step per layer. Doing that with one mask per step would take numerous exposures. Instead, fabs etch down one layer, trim the resist back sideways, and etch again, so one exposure makes many steps. In Lam’s 2016 account, one exposure of thick KrF resist at 248nm made 8 steps, and Lam was working toward 16. The ratio of lateral to vertical etch rate sets how many steps one mask can make.

Precision lives in the trim. A small error in pad width carries through every step made from the same exposure, and Lam’s process held stair width to 1% (3-sigma) through more than five trim cycles. Where masks do matter in 3D NAND, they fight the stack itself. The hole pattern sits on a carbon hardmask more than 3µm thick, and wafer bow and local film stress from the deposited stack directly affect overlay, Lam wrote in 2017. ASML offers options for its dry scanners aimed at high-topography stacks and wafer warpage. As Part 1 noted, 3D NAND also leans on the scanner’s own metrology, because many metrology tools cannot see inside the stack.

Wafer bonding takes on part of the problem in the newest step. Kioxia’s CMOS directly Bonded to Array (CBA) process builds the CMOS circuits and the cell array on separate wafers, puts copper pads on each surface, and bonds them face to face. Kioxia used it on its 218-layer BiCS FLASH generation 8, where it says the cell current rose 35% and the interface reached 3.2Gbps, and it lists alignment and wafer warpage control among the things it had to develop. That alignment is a form of overlay between two whole wafers. It belongs to the same family as the copper direct bonding Kioxia cites in processors and image sensors, and the bonded stacks the IRDS flags for future HBM.

One date is worth watching. The larger mask format, which would bring back the full field, could arrive in 2028 at the earliest, and Samsung’s plan to bring High-NA into DRAM manufacturing is dated 2028 as well. Until then, a big chip is either stitched across two exposures or built from smaller ones joined in a package. Before any die is joined to another, it is tested. Part 4 follows a NAND die from wafer sort to qualification, and Part 5 then takes the second road, starting with CoWoS and the reticle limit that made it necessary.