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DRAM Die Timeline

DRAM dies from SDR and DDR main memory to LPDDR mobile and GDDR graphics memory, placed at the date of the earliest release, paper or datasheet cited for each. Every point links to its source.

20002005201020152020202532Gb12nm-class 32Gb DDR5 (development), 9/2023

Chart of DRAM dies by year

Die density climbed from 0.063Gb in 1998 to 32Gb in 2023

Data rate climbed from 100MT/s in 1998 to 40000MT/s in 2024

Bit density climbed from 0.22Gb/mm2 in 2022 to 0.44Gb/mm2 in 2024

Measure
Type and maker
Type
Maker

Die density runs from 0.063Gb (1998) to 32Gb (2023) across 79 dies.
0.050.10.20.5125102050Die density, Gb, log scale1998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202664Mb SDRAM for PC100 (mass production; the release names the maker Hyundai Electronics): 0.063Gb, 2/19980.20-micron 256Mb SDRAM (samples from 8/1998 in Japan): 0.25Gb, 7/19980.22 micron 128Mb DDR (samples; release names the maker HEI): 0.13Gb, 6/19990.18-micron 256Mb PC133 SDRAM (samples from 8/1999 in Japan): 0.25Gb, 6/1999128Mb DDR333 (volume production): 0.13Gb, 11/2001256Mb DDR333 (volume production): 0.25Gb, 11/20010.10-micron 512Mb DDR (development announced): 0.5Gb, 10/20020.14u 256Mb DDR400 (announced): 0.25Gb, 2/2003256Mb DDR400 (sample and mass production quantities): 0.25Gb, 2/20030.11-micron 1Gb DDR2 (development completed): 1Gb, 8/20030.11-micron 512Mb DDR2 (samples to Intel): 0.5Gb, 9/200380nm 2Gb DDR2 (announced): 2Gb, 9/200475nm 512Mb DDR2 (qualified, Qimonda joint development): 0.5Gb, 9/200680nm 1Gb DDR2 (mass production; secondary source): 1Gb, 9/200660nm 1Gb DDR2 (introduced; Intel validated): 1Gb, 12/200660nm-class 1Gb DDR2 (mass production): 1Gb, 3/200778nm 1Gb DDR3 (evaluation samples): 1Gb, 5/200780nm 1Gb DDR3 (first Intel validation): 1Gb, 5/2007512Mb GDDR4 (supply for AMD Radeon HD 2900XT cards): 0.5Gb, 6/200760nm-class 2Gb DDR2 (announced): 2Gb, 9/200778nm 2Gb DDR3 (sampling modules): 2Gb, 10/200750nm-class 1Gb DDR2 (Intel validation): 1Gb, 11/200750nm 1Gb DDR2 (mass production): 1Gb, 4/200866nm 1Gb DDR3 (SO-DIMM validation; component validated 10/2007 per the release): 1Gb, 4/200850nm 2Gb DDR3 (mass production): 2Gb, 9/200854nm 1Gb DDR3 second generation (mass production): 1Gb, 10/200940nm-class 2Gb DDR3 (Intel validation, mass production begun): 2Gb, 11/200942nm 2Gb DDR3 (joint Micron and Nanya): 2Gb, 2/201050nm 2Gb DDR2 (announced, sampling planned 9/2010): 2Gb, 7/201030nm-class 4Gb LPDDR2 (mass production): 4Gb, 3/201130nm-class 2Gb DDR4 (developed): 2Gb, 4/201120nm-class 4Gb DDR3 (shown at MWC, volume production planned 1H 2012): 4Gb, 2/201230nm 4Gb DDR4 (sampling): 4Gb, 5/201230nm 4Gb DDR4 (sampling): 4Gb, 7/201220nm-class 4Gb LPDDR3 (mass production): 4Gb, 4/201320nm 4Gb DDR3 (mass production): 4Gb, 3/201420nm-class 8Gb DDR4 (128GB TSV module announced): 8Gb, 4/201430nm 4Gb DDR3 (sampling): 4Gb, 5/201425nm 8Gb monolithic DDR3 (announced): 8Gb, 7/201420nm-class 4Gb DDR4 (16GB NVDIMM announced): 4Gb, 10/201420nm 8Gb DDR4 (mass production): 8Gb, 10/201420nm 8Gb LPDDR4 (mass production): 8Gb, 12/201420nm 8Gb GDDR5 (mass production): 8Gb, 1/201510nm-class (1x) 8Gb DDR4 (mass production): 8Gb, 4/201620nm 4Gb DDR3 (volume shipment): 4Gb, 10/20172nd-generation 10nm-class (1y) 8Gb DDR4 (mass production): 8Gb, 12/201720nm 8Gb DDR4 (mass production): 8Gb, 1/201810nm-class 16Gb GDDR6 (mass production): 16Gb, 1/201810nm-class 8Gb LPDDR5 (development): 8Gb, 7/20181Ynm 8Gb DDR4 (developed): 8Gb, 11/20181Ynm 16Gb DDR5 (developed; RDIMM and UDIMM supplied to a chipset maker): 16Gb, 11/20183rd-generation 10nm-class (1z) 8Gb DDR4 (development): 8Gb, 3/201910nm-class 12Gb LPDDR5 (mass production): 12Gb, 7/20191z nm 16Gb DDR4 (mass production): 16Gb, 8/20198Gb DDR4 (mass production announced): 8Gb, 9/20191Znm 16Gb DDR4 (developed): 16Gb, 10/20198Gb GDDR6X (available; in GeForce RTX 3080 and 3090): 8Gb, 9/20201anm 24Gb DDR5 (samples shipped): 24Gb, 12/202116Gb GDDR6X (volume production; in GeForce RTX 3090 Ti): 16Gb, 4/202216Gb DDR5 (D1z, die Y32A, in a retail module; secondary source): 16Gb, 202216Gb DDR5 (D1y, die K4RAH046VB, in a retail module; secondary source): 16Gb, 202216Gb DDR5 (D1y, die H5CNAG8NM, in a retail module; secondary source): 16Gb, 202212nm-class 16Gb DDR5 (development): 16Gb, 12/202216Gb DDR5 die Rev A (datasheet Rev C): 16Gb, 1/202312nm-class 16Gb DDR5 (mass production): 16Gb, 5/202316Gb GDDR7 (development): 16Gb, 7/202312nm-class 32Gb DDR5 (development): 32Gb, 9/20231β 16Gb DDR5 (shipping): 16Gb, 10/20231β 32Gb monolithic DDR5 (announced, in 128GB RDIMM): 32Gb, 11/20231β 32Gb monolithic DDR5 (validated and shipping in 128GB RDIMM): 32Gb, 5/20241c 16Gb DDR5 (developed; mass production planned 2024): 16Gb, 8/202424Gb GDDR7 (development; commercial supply planned early 2025): 24Gb, 10/202416Gb LPDDR5X (D1b, found in a Vivo X200 Pro Satellite; secondary source): 16Gb, 11/20241γ 16Gb DDR5 (samples shipped): 16Gb, 2/20251B (10nm-class) 16Gb DDR5-5600 (delivered): 16Gb, 4/20251B (10nm-class) 8Gb DDR4 (volume production): 8Gb, 7/202524Gb DDR5 (shown at IC China): 24Gb, 11/202532Gb DDR5 (1b, in a 256GB server RDIMM): 32Gb, 12/20251c 16Gb LPDDR6 (development; supply planned for 2H 2026): 16Gb, 3/2026
Data rate runs from 100MT/s (1998) to 40000MT/s (2024) across 58 dies. A hollow marker is a lower limit the source prints.
100200500100020005000100002000050000Data rate the shipping part was specified at, MT/s, log scale1998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202664Mb SDRAM for PC100 (mass production; the release names the maker Hyundai Electronics): 100MT/s, 2/19980.20-micron 256Mb SDRAM (samples from 8/1998 in Japan): 100MT/s, 7/19980.18-micron 256Mb PC133 SDRAM (samples from 8/1999 in Japan): 133MT/s, 6/19990.22 micron 128Mb DDR (samples; release names the maker HEI): 266MT/s, 6/1999128Mb DDR333 (volume production): 333MT/s, 11/2001256Mb DDR333 (volume production): 333MT/s, 11/20010.10-micron 512Mb DDR (development announced): 400MT/s, 10/20020.14u 256Mb DDR400 (announced): 400MT/s, 2/2003256Mb DDR400 (sample and mass production quantities): 400MT/s, 2/20030.11-micron 512Mb DDR2 (samples to Intel): 667MT/s, 9/200360nm 1Gb DDR2 (introduced; Intel validated): 800MT/s, 12/200678nm 1Gb DDR3 (evaluation samples): 1066MT/s, 5/200780nm 1Gb DDR3 (first Intel validation): 1066MT/s, 5/2007512Mb GDDR4 (supply for AMD Radeon HD 2900XT cards): 3200MT/s, 6/200778nm 2Gb DDR3 (sampling modules): 1333MT/s, 10/200766nm 1Gb DDR3 (SO-DIMM validation; component validated 10/2007 per the release): 1066MT/s, 4/200840nm-class 2Gb DDR3 (Intel validation, mass production begun): 1333MT/s, 11/200942nm 2Gb DDR3 (joint Micron and Nanya): 1866MT/s, 2/201030nm-class 4Gb LPDDR2 (mass production): 1066MT/s, 3/201130nm-class 2Gb DDR4 (developed): 2400MT/s, 4/201120nm-class 4Gb DDR3 (shown at MWC, volume production planned 1H 2012): 2133MT/s, 2/201230nm 4Gb DDR4 (sampling): 2400MT/s, 5/201220nm-class 4Gb LPDDR3 (mass production): 2133MT/s, 4/201320nm-class 8Gb DDR4 (128GB TSV module announced): 2133MT/s, 4/201420nm-class 4Gb DDR4 (16GB NVDIMM announced): 2133MT/s, 10/201420nm 8Gb DDR4 (mass production): 2400MT/s, 10/201420nm 8Gb LPDDR4 (mass production): 3200MT/s, 12/201420nm 8Gb GDDR5 (mass production): 8000MT/s, 1/201510nm-class (1x) 8Gb DDR4 (mass production): 3200MT/s, 4/20162nd-generation 10nm-class (1y) 8Gb DDR4 (mass production): 3600MT/s, 12/201710nm-class 16Gb GDDR6 (mass production): 18000MT/s, 1/201810nm-class 8Gb LPDDR5 (development): 6400MT/s, 7/20181Ynm 8Gb DDR4 (developed): 3200MT/s, 11/20181Ynm 16Gb DDR5 (developed; RDIMM and UDIMM supplied to a chipset maker): 5200MT/s, 11/201810nm-class 12Gb LPDDR5 (mass production): 5500MT/s, 7/20191Znm 16Gb DDR4 (developed): 3200MT/s, 10/20198Gb GDDR6X (available; in GeForce RTX 3080 and 3090): 21000MT/s, 9/202014nm EUV DDR5 (mass production): 7200MT/s, 10/202116Gb GDDR6X (volume production; in GeForce RTX 3090 Ti): 21000MT/s, 4/202212nm-class 16Gb DDR5 (development): 7200MT/s, 12/202216Gb DDR5 die Rev A (datasheet Rev C): 4800MT/s, 1/2023LPDDR5T (samples in 16GB multi-chip packages): 9600MT/s, 1/202312nm-class 16Gb DDR5 (mass production): 7200MT/s, 5/202316Gb GDDR7 (development): 32000MT/s, 7/20231β 16Gb DDR5 (shipping): 7200MT/s, 10/20231β 32Gb monolithic DDR5 (announced, in 128GB RDIMM): 8000MT/s, 11/202312nm-class 10.7Gbps LPDDR5X (development): 10700MT/s, 4/20241β 32Gb monolithic DDR5 (validated and shipping in 128GB RDIMM): 5600MT/s, 5/20241β GDDR7 (sampling; available 2H 2024): 32000MT/s, 6/2024GDDR7 (introduced; mass production planned 3Q 2024): 32000MT/s, 7/20241c 16Gb DDR5 (developed; mass production planned 2024): 8000MT/s, 8/202424Gb GDDR7 (development; commercial supply planned early 2025): 40000MT/s, 10/20241γ 16Gb DDR5 (samples shipped): 9200MT/s, 2/20251B (10nm-class) 16Gb DDR5-5600 (delivered): 5600MT/s, 4/20251γ LPDDR5X (qualification samples): 10700MT/s, 6/202524Gb DDR5 (shown at IC China): 8000MT/s, 11/20251c 16Gb LPDDR6 (development; supply planned for 2H 2026): ≥10700MT/s, 3/202616GB LPDDR6 (sampled and validated on a Qualcomm Snapdragon platform): 10700MT/s, 9/2026
Bit density runs from 0.21Gb/mm2 (2022) to 0.44Gb/mm2 (2024) across 4 dies.
  • Record: the best any die had reached by then
  • Samsung
  • SK hynix
  • Micron
  • Others
  • Fastest data rate a JEDEC DDR revision defined

10 records, oldest first. Each die beat every earlier die on die density.

  1. 0.063Gb

    64Mb SDRAM for PC100 (mass production; the release names the maker Hyundai Electronics)

    Maker
    SK hynix
    Type
    SDR
  2. 0.25Gb

    0.20-micron 256Mb SDRAM (samples from 8/1998 in Japan)

    Maker
    Others
    Type
    SDR
  3. 0.5Gb

    0.10-micron 512Mb DDR (development announced)

    Maker
    SK hynix
    Type
    DDR
  4. 1Gb

    0.11-micron 1Gb DDR2 (development completed)

    Maker
    SK hynix
    Type
    DDR
  5. 2Gb

    80nm 2Gb DDR2 (announced)

    Maker
    Samsung
    Type
    DDR
  6. 4Gb

    30nm-class 4Gb LPDDR2 (mass production)

    Maker
    Samsung
    Type
    LPDDR
  7. 8Gb

    20nm-class 8Gb DDR4 (128GB TSV module announced)

    Maker
    SK hynix
    Type
    DDR
  8. 16Gb

    10nm-class 16Gb GDDR6 (mass production)

    Maker
    Samsung
    Type
    GDDR
  9. 24Gb

    1anm 24Gb DDR5 (samples shipped)

    Maker
    SK hynix
    Type
    DDR
  10. 32Gb

    12nm-class 32Gb DDR5 (development)

    Maker
    Samsung
    Type
    DDR

12 records, oldest first. Each die beat every earlier die on data rate.

  1. 100MT/s

    64Mb SDRAM for PC100 (mass production; the release names the maker Hyundai Electronics)

    Maker
    SK hynix
    Type
    SDR
  2. 266MT/s

    0.22 micron 128Mb DDR (samples; release names the maker HEI)

    Maker
    SK hynix
    Type
    DDR
  3. 333MT/s

    128Mb DDR333 (volume production)

    Maker
    Others
    Type
    DDR
  4. 400MT/s

    0.10-micron 512Mb DDR (development announced)

    Maker
    SK hynix
    Type
    DDR
  5. 667MT/s

    0.11-micron 512Mb DDR2 (samples to Intel)

    Maker
    SK hynix
    Type
    DDR
  6. 800MT/s

    60nm 1Gb DDR2 (introduced; Intel validated)

    Maker
    SK hynix
    Type
    DDR
  7. 3200MT/s

    512Mb GDDR4 (supply for AMD Radeon HD 2900XT cards)

    Maker
    Samsung
    Type
    GDDR
  8. 8000MT/s

    20nm 8Gb GDDR5 (mass production)

    Maker
    Samsung
    Type
    GDDR
  9. 18000MT/s

    10nm-class 16Gb GDDR6 (mass production)

    Maker
    Samsung
    Type
    GDDR
  10. 21000MT/s

    8Gb GDDR6X (available; in GeForce RTX 3080 and 3090)

    Maker
    Micron
    Type
    GDDR
  11. 32000MT/s

    16Gb GDDR7 (development)

    Maker
    Samsung
    Type
    GDDR
  12. 40000MT/s

    24Gb GDDR7 (development; commercial supply planned early 2025)

    Maker
    Samsung
    Type
    GDDR

3 records, oldest first. Each die beat every earlier die on bit density.

  1. 0.22Gb/mm2

    16Gb DDR5 (D1y, die K4RAH046VB, in a retail module; secondary source)

    Maker
    Samsung
    Type
    DDR
  2. 0.24Gb/mm2

    16Gb DDR5 (D1z, die Y32A, in a retail module; secondary source)

    Maker
    Micron
    Type
    DDR
  3. 0.44Gb/mm2

    16Gb LPDDR5X (D1b, found in a Vivo X200 Pro Satellite; secondary source)

    Maker
    Samsung
    Type
    LPDDR

How to read it

Each point is one DRAM die that a vendor release, datasheet or paper describes. It sits at the date of the earliest public source cited for that die, which is the date of the announcement or production news and not the date the die reached modules on shelves. The chart shows 88 dies from 87 public sources, and the JEDEC revisions cite 5 more. It is not every die ever made, and a die with no stated value for the chosen measure is left off. It runs from 1998 to 2026. The Type and Maker chips filter the chart and the tables below. Stacked HBM has its own timeline.

Data rate is the speed the shipping part was specified at, from a datasheet or a vendor release, in MT/s: a GDDR7 die at 32Gb/s per pin is 32,000MT/s. A paper's test chip can run faster than anything sold, so a rate printed only for a test chip is not shown. Data rate uses a log scale, because a graphics die runs several times faster than a DDR die of the same year. The dashed line is the fastest data rate any JEDEC DDR revision had defined by each date, so it applies to DDR main memory and not to LPDDR or GDDR.

Density is in gigabits per die and uses a log scale, where each gridline step multiplies the value rather than adding to it. Vendors name their process nodes differently, so the node class is in the tables as the vendor prints it and is not charted. A rate marked as up to is the top speed the vendor states for the part.

Every die and its source

One table per family, newest generation first, with a line between generations and the newest die first within each.

  • means the maker hasn't published this figure.
  • Derived: worked out from two figures in the source, not stated by it.

SDR 3 dies

Single data rate dies, the main memory before DDR.

DieVendorGenerationNode classStatusDateDensityData rateSourceNote
0.18-micron 256Mb PC133 SDRAM (samples from 8/1999 in Japan)HitachiSDR0.18 micronAnnounced6/19990.25Gb133MT/sHitachi 1999 release
0.20-micron 256Mb SDRAM (samples from 8/1998 in Japan)HitachiSDR0.20 micronAnnounced7/19980.25Gb100MT/sHitachi 1998 release
64Mb SDRAM for PC100 (mass production; the release names the maker Hyundai Electronics)SK hynixSDRnot publishedMass production2/19980.063Gb100MT/sSK hynix 1998 releaseHyundai Electronics, now SK hynix. The release stresses CAS latency 2 at PC100 and a 6ns access time.

DDR main memory 64 dies

DDR through DDR5, the dies on desktop, laptop and server memory modules.

DieVendorGenerationNode classStatusDateDensityData rateSourceNote
32Gb DDR5 (1b, in a 256GB server RDIMM)SK hynixDDR51b (fifth-generation 10nm-class)Announced12/202532Gbnot publishedSK hynix 2025 releaseThe release announces Intel Xeon 6 certification of the module; it gives no data rate. The page header says December 17 and the dateline December 18, 2025.
24Gb DDR5 (shown at IC China)CXMTDDR5not publishedAnnounced11/202524Gb8000MT/sCXMT 2025 release
1B (10nm-class) 16Gb DDR5-5600 (delivered)NanyaDDR510nm-class (1B)Mass production4/202516Gb5600MT/sNanya Technology 2025 release
1γ 16Gb DDR5 (samples shipped)MicronDDR51γ (1-gamma)Sampling2/202516Gb9200MT/sMicron 2025 release
1c 16Gb DDR5 (developed; mass production planned 2024)SK hynixDDR51cAnnounced8/202416Gb8000MT/sSK hynix 2024 release
1β 32Gb monolithic DDR5 (validated and shipping in 128GB RDIMM)MicronDDR51β (1-beta)Mass production5/202432Gb5600MT/sMicron 2024 release
1β 32Gb monolithic DDR5 (announced, in 128GB RDIMM)MicronDDR51β (1-beta)Announced11/202332Gb8000MT/sMicron 2023 release
1β 16Gb DDR5 (shipping)MicronDDR51β (1-beta)Mass production10/202316Gb7200MT/sMicron 2023 release
12nm-class 32Gb DDR5 (development)SamsungDDR512nm-classAnnounced9/202332Gbnot publishedSamsung 2023 release
12nm-class 16Gb DDR5 (mass production)SamsungDDR512nm-classMass production5/202316Gb7200MT/sSamsung 2023 release
16Gb DDR5 die Rev A (datasheet Rev C)MicronDDR5not publishedAnnounced1/202316Gb4800MT/sMicron 2023 product page
12nm-class 16Gb DDR5 (development)SamsungDDR512nm-classAnnounced12/202216Gb7200MT/sSamsung 2022 release
16Gb DDR5 (D1y, die H5CNAG8NM, in a retail module; secondary source)SK hynixDDR5not publishedMass production202216Gbnot publishedTechInsights 2022 teardownDated by the teardown, not a vendor release. A first-generation DDR5 die in a retail module.
16Gb DDR5 (D1y, die K4RAH046VB, in a retail module; secondary source)SamsungDDR5not publishedMass production202216Gbnot publishedTechInsights 2022 teardownDated by the teardown, not a vendor release. A first-generation DDR5 die in a retail module.
16Gb DDR5 (D1z, die Y32A, in a retail module; secondary source)MicronDDR5not publishedMass production202216Gbnot publishedTechInsights 2022 teardownDated by the teardown, not a vendor release. A first-generation DDR5 die in a retail module.
1anm 24Gb DDR5 (samples shipped)SK hynixDDR51anmSampling12/202124Gbnot publishedSK hynix 2021 release
14nm EUV DDR5 (mass production)SamsungDDR514nmMass production10/2021not published7200MT/sSamsung 2021 release
1Ynm 16Gb DDR5 (developed; RDIMM and UDIMM supplied to a chipset maker)SK hynixDDR51YnmAnnounced11/201816Gb5200MT/sSK hynix 2018 release
1B (10nm-class) 8Gb DDR4 (volume production)NanyaDDR41BMass production7/20258Gbnot publishedNanya Technology 2025 release
1α DDR4 (volume production; to 16Gb range; die area from a secondary source)MicronDDR41α (1-alpha)Mass production2021not publishednot publishedMicron 2021 releaseTechInsights 2021 teardown
1Znm 16Gb DDR4 (developed)SK hynixDDR41ZnmAnnounced10/201916Gb3200MT/sSK hynix 2019 release
8Gb DDR4 (mass production announced)CXMTDDR4not publishedMass production9/20198Gbnot publishedCXMT 2019 release
1z nm 16Gb DDR4 (mass production)MicronDDR41z nmMass production8/201916Gbnot publishedMicron 2019 release
3rd-generation 10nm-class (1z) 8Gb DDR4 (development)SamsungDDR43rd-generation 10nm-class (1z-nm)Announced3/20198Gbnot publishedSamsung 2019 release
1Ynm 8Gb DDR4 (developed)SK hynixDDR41YnmAnnounced11/20188Gb3200MT/sSK hynix 2018 release
20nm 8Gb DDR4 (mass production)NanyaDDR420nmMass production1/20188Gbnot publishedNanya Technology 2018 release
2nd-generation 10nm-class (1y) 8Gb DDR4 (mass production)SamsungDDR42nd-generation 10nm-class (1y-nm)Mass production12/20178Gb3600MT/sSamsung 2017 release
10nm-class (1x) 8Gb DDR4 (mass production)SamsungDDR410nm-class (1x)Mass production4/20168Gb3200MT/sSamsung 2016 release
20nm 8Gb DDR4 (mass production)SamsungDDR420nmMass production10/20148Gb2400MT/sSamsung 2014 release
20nm-class 4Gb DDR4 (16GB NVDIMM announced)SK hynixDDR420nm classAnnounced10/20144Gb2133MT/sSK hynix 2014 release
20nm-class 8Gb DDR4 (128GB TSV module announced)SK hynixDDR420nm classAnnounced4/20148Gb2133MT/sSK hynix 2014 release
30nm 4Gb DDR4 (sampling)NanyaDDR430nmSampling7/20124Gbnot publishedNanya Technology 2012 release
30nm 4Gb DDR4 (sampling)MicronDDR430nmSampling5/20124Gb2400MT/sMicron 2012 release
30nm-class 2Gb DDR4 (developed)SK hynixDDR430nm classAnnounced4/20112Gb2400MT/sSK hynix 2011 release
20nm 4Gb DDR3 (volume shipment)NanyaDDR320nmMass production10/20174Gbnot publishedNanya Technology 2017 release
25nm 8Gb monolithic DDR3 (announced)MicronDDR325nmAnnounced7/20148Gbnot publishedMicron 2014 release
30nm 4Gb DDR3 (sampling)NanyaDDR330nmSampling5/20144Gbnot publishedNanya Technology 2014 release
20nm 4Gb DDR3 (mass production)SamsungDDR320nmMass production3/20144Gbnot publishedSamsung 2014 release
20nm-class 4Gb DDR3 (shown at MWC, volume production planned 1H 2012)SK hynixDDR320nm classAnnounced2/20124Gb2133MT/sSK hynix 2012 release
42nm 2Gb DDR3 (joint Micron and Nanya)NanyaDDR342nmAnnounced2/20102Gb1866MT/sMicron 2010 release
40nm-class 2Gb DDR3 (Intel validation, mass production begun)SK hynixDDR340nm classMass production11/20092Gb1333MT/sSK hynix 2009 release
54nm 1Gb DDR3 second generation (mass production)SK hynixDDR354nmMass production10/20091Gbnot publishedSK hynix 2009 release
50nm 2Gb DDR3 (mass production)SamsungDDR350nmMass production9/20082Gbnot publishedSamsung 2008 release
66nm 1Gb DDR3 (SO-DIMM validation; component validated 10/2007 per the release)SK hynixDDR366nmAnnounced4/20081Gb1066MT/sSK hynix 2008 release
78nm 2Gb DDR3 (sampling modules)MicronDDR378nmSampling10/20072Gb1333MT/sMicron 2007 release
78nm 1Gb DDR3 (evaluation samples)MicronDDR378nmSampling5/20071Gb1066MT/sMicron 2007 release
80nm 1Gb DDR3 (first Intel validation)SK hynixDDR380nmAnnounced5/20071Gb1066MT/sSK hynix 2007 release
50nm 2Gb DDR2 (announced, sampling planned 9/2010)MicronDDR250nmAnnounced7/20102Gbnot publishedMicron 2010 release
50nm 1Gb DDR2 (mass production)SamsungDDR250nmMass production4/20081Gbnot publishedSamsung 2008 release
50nm-class 1Gb DDR2 (Intel validation)SK hynixDDR250nm-classAnnounced11/20071Gbnot publishedSK hynix 2007 release
60nm-class 2Gb DDR2 (announced)SamsungDDR260nm-classAnnounced9/20072Gbnot publishedSamsung 2007 release
60nm-class 1Gb DDR2 (mass production)SamsungDDR260nm-classMass production3/20071Gbnot publishedSamsung 2007 release
60nm 1Gb DDR2 (introduced; Intel validated)SK hynixDDR260nmAnnounced12/20061Gb800MT/sSK hynix 2006 release
75nm 512Mb DDR2 (qualified, Qimonda joint development)NanyaDDR275nmMass production9/20060.5Gbnot publishedNanya Technology and Qimonda 2006 release
80nm 1Gb DDR2 (mass production; secondary source)SamsungDDR280nmMass production9/20061Gbnot publishedEE Times 2006 release
80nm 2Gb DDR2 (announced)SamsungDDR280nmAnnounced9/20042Gbnot publishedSamsung 2004 release
0.11-micron 512Mb DDR2 (samples to Intel)SK hynixDDR2.11-micronSampling9/20030.5Gb667MT/sSK hynix 2003 release
0.11-micron 1Gb DDR2 (development completed)SK hynixDDR20.11-micronAnnounced8/20031Gbnot publishedSK hynix 2003 release
0.14u 256Mb DDR400 (announced)NanyaDDR0.14uAnnounced2/20030.25Gb400MT/sNanya Technology 2003 release
256Mb DDR400 (sample and mass production quantities)SK hynixDDRnot publishedMass production2/20030.25Gb400MT/sSK hynix 2003 release
0.10-micron 512Mb DDR (development announced)SK hynixDDR0.10-micronAnnounced10/20020.5Gb400MT/sSK hynix 2002 release
128Mb DDR333 (volume production)NanyaDDRnot publishedMass production11/20010.13Gb333MT/sNanya Technology 2001 release
256Mb DDR333 (volume production)NanyaDDRnot publishedMass production11/20010.25Gb333MT/sNanya Technology 2001 release
0.22 micron 128Mb DDR (samples; release names the maker HEI)SK hynixDDR0.22 micronSampling6/19990.13Gb266MT/sSK hynix 1999 release

JEDEC DDR revisions behind the dashed line

The dashed line on the data rate chart steps up at each revision. Each revision is dated by JEDEC's own first publication of it, from its public page or press release.

LPDDR mobile memory 12 dies

Low-power dies for phones, tablets and thin laptops, usually soldered next to the processor.

DieVendorGenerationNode classStatusDateDensityData rateSourceNote
16GB LPDDR6 (sampled and validated on a Qualcomm Snapdragon platform)SamsungLPDDR6not publishedSampling9/2026not published10700MT/sSamsung 2026 releaseSamsung gives up to 114GB/s and up to 21% better power efficiency than LPDDR5X for its LPDDR6.
1c 16Gb LPDDR6 (development; supply planned for 2H 2026)SK hynixLPDDR61cAnnounced3/202616Gb≥10700MT/sSK hynix 2026 release
LPDDR5T (samples in 16GB multi-chip packages)SK hynixLPDDR5T1anmSampling1/2023not published9600MT/sSK hynix 2023 releaseT for Turbo is SK hynix's own name. The release calls it an upgraded LPDDR5X, not a new JEDEC generation.
1cnm LPDDR5X (in a 192GB SOCAMM2 module, mass production)SK hynixLPDDR5X1cnm (sixth-generation 10nm-class)Mass production4/2026not publishednot publishedSK hynix 2026 releaseDated by the module release. It gives no die density or data rate for the LPDDR5X die.
1γ LPDDR5X (qualification samples)MicronLPDDR5X1γ (1-gamma)Sampling6/2025not published10700MT/sMicron 2025 releaseMicron calls it the first LPDDR5X on its 1γ node; the release does not give the die density.
16Gb LPDDR5X (D1b, found in a Vivo X200 Pro Satellite; secondary source)SamsungLPDDR5XD1b (mid-12nm class)Mass production11/202416Gbnot publishedTechInsights 2024 teardownDated by the teardown, not a Samsung release. The die was in a shipping phone, die marking K4K6E165YE.
12nm-class 10.7Gbps LPDDR5X (development)SamsungLPDDR5X12nm-classAnnounced4/2024not published10700MT/sSamsung 2024 release
10nm-class 12Gb LPDDR5 (mass production)SamsungLPDDR510nm-classMass production7/201912Gb5500MT/sSamsung 2019 release
10nm-class 8Gb LPDDR5 (development)SamsungLPDDR510nm-classAnnounced7/20188Gb6400MT/sSamsung 2018 release
20nm 8Gb LPDDR4 (mass production)SamsungLPDDR420nmMass production12/20148Gb3200MT/sSamsung 2014 release
20nm-class 4Gb LPDDR3 (mass production)SamsungLPDDR320nm-classMass production4/20134Gb2133MT/sSamsung 2013 release
30nm-class 4Gb LPDDR2 (mass production)SamsungLPDDR230nm-classMass production3/20114Gb1066MT/sSamsung 2011 release

GDDR graphics memory 9 dies

Graphics dies, soldered around a GPU and run at the highest data rates on this page.

DieVendorGenerationNode classStatusDateDensityData rateSourceNote
24Gb GDDR7 (development; commercial supply planned early 2025)SamsungGDDR75th-generation 10nm-classAnnounced10/202424Gb40000MT/sSamsung 2024 release
GDDR7 (introduced; mass production planned 3Q 2024)SK hynixGDDR7not publishedAnnounced7/2024not published32000MT/sSK hynix 2024 releaseThe release gives no die density or node name.
1β GDDR7 (sampling; available 2H 2024)MicronGDDR71βSampling6/2024not published32000MT/sMicron 2024 release
16Gb GDDR7 (development)SamsungGDDR7not publishedAnnounced7/202316Gb32000MT/sSamsung 2023 releaseUses PAM3 signaling, three levels, in place of the two-level NRZ of earlier GDDR.
16Gb GDDR6X (volume production; in GeForce RTX 3090 Ti)MicronGDDR6Xnot publishedMass production4/202216Gb21000MT/sMicron 2022 releaseTwice the capacity of the 8Gb GDDR6X and up to 15% higher performance, per Micron.
8Gb GDDR6X (available; in GeForce RTX 3080 and 3090)MicronGDDR6Xnot publishedMass production9/20208Gb21000MT/sMicron 2020 releaseThe first memory to use PAM4 signaling, four levels carrying two bits per transfer, per Micron.
10nm-class 16Gb GDDR6 (mass production)SamsungGDDR610nm-classMass production1/201816Gb18000MT/sSamsung 2018 release
20nm 8Gb GDDR5 (mass production)SamsungGDDR520nmMass production1/20158Gb8000MT/sSamsung 2015 release
512Mb GDDR4 (supply for AMD Radeon HD 2900XT cards)SamsungGDDR4not publishedMass production6/20070.5Gb3200MT/sSamsung 2007 releaseThe release says Samsung was the only maker of GDDR4 in production, and that a 1GB Radeon HD 2900XT card carried 16 of these dies.

DDR5, LPDDR5X, GDDR7 and HBM side by side, from JEDEC only

StandardJEDEC documentData rate JEDEC statesOrganisationSupply voltage
DDR5JESD79-54.8Gb/s per pin expected at launch JEDEC 2020 releaseBurst length 16, 32 banks; a DIMM has two 40-bit independent sub-channels JEDEC 2020 releaseVdd 1.1V JEDEC 2020 release
DDR5JESD79-5CTiming parameters defined up to 8,800Mb/s JEDEC 2024 releasenot publishednot published
LPDDR5XJESD209-5BNot stated for LPDDR5X itself; the same revision lifts LPDDR5 to up to 8,533Mb/s from 6,400Mb/s JEDEC 2021 standardnot publishednot published
GDDR7JESD239FUp to 192GB/s per device; the standard's clocking example is 28Gb/s per pin, 14 gigabaud PAM3 JEDEC 2024 standardJEDEC 2026 standardFour independent channels, 16 banks per channel, 32n prefetch of 256 bits, PAM3 signalling JEDEC 2026 standardVDD and VDDQ 1.2V JEDEC 2026 standard
HBM3JESD238B.01Up to 6.4Gb/s per pin, 819GB/s per device JEDEC 2022 standardUp to 16 channels per stack, 64 data pins per channel, 256-bit prefetch, burst length 8 JEDEC 2025 standardI/O 1.1V, transmit driver 0.4V JEDEC 2025 standard
HBM4JESD270-4Up to 8Gb/s per pin over a 2,048-bit interface JEDEC 2025 standardnot publishednot published

Every cell is a figure from a JEDEC standard, its public page or its press release, and links to that source. The standards are written differently, so a dash means the JEDEC pages saved here do not state the figure; it does not mean the standard lacks it. Vendor figures for shipping dies sit in the tables above and are not mixed in.

Each value links to the source it was read from. A figure a paper reports for a test chip is not the same as a shipping part's. The Note column is a short remark on an unusual part, from the sources in its row. On a phone, swipe a table sideways to see every column.

Download the dies and their sources: CSV or JSON. Each row is one sourced value with the source it was read from, and the D and T marks as columns.

Research papers and makers’ speeds

What the newest research chips reached on a bench, and the most each maker lists for a part it sells. Neither is a measured product, so neither is drawn on the chart above.

8 ISSCC papers, 2023 to 20268 rows

Newest first. Each speed is the one printed in the paper’s title, because the full papers are behind a paywall, and a title does not say what the speed was measured on. The bar compares a paper only with others in the same unit.

Makers’ listed speeds7 rows

Quoted from each maker’s product page, with the generation the page names. An “up to” speed is a ceiling the maker chose, not what a part delivers in a computer, and the pages carry no date, so none is shown. SK hynix’s product pages could not be read, so no SK hynix speed is listed.

What it will not tell you

A die sits at the date of its release, not the date modules with it shipped in volume. Vendors do not all publish the same numbers, so a die with no stated speed is not on the data rate chart even when its density is known. Die area is published for few of these parts: it comes from TechInsights teardowns of shipping dies, and the bit density chart draws only dies with both a density and an area. For stacked DRAM on accelerators, see the HBM Timeline, and for the flash side, the NAND Die Timeline. ISSCC, IEDM and the VLSI Symposium, where device papers on these dies are published, are on the events calendar.

The guides behind this data

The other timelines