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DRAM Die Timeline
DRAM dies from SDR and DDR main memory to LPDDR mobile and GDDR graphics memory, placed at the date of the earliest release, paper or datasheet cited for each. Every point links to its source.
Chart of DRAM dies by year
Die density climbed from 0.063Gb in 1998 to 32Gb in 2023
Data rate climbed from 100MT/s in 1998 to 40000MT/s in 2024
Bit density climbed from 0.22Gb/mm2 in 2022 to 0.44Gb/mm2 in 2024
- Record: the best any die had reached by then
- Samsung
- SK hynix
- Micron
- Others
- Fastest data rate a JEDEC DDR revision defined
10 records, oldest first. Each die beat every earlier die on die density.
2/1998
0.063Gb
64Mb SDRAM for PC100 (mass production; the release names the maker Hyundai Electronics)
- Maker
- SK hynix
- Type
- SDR
7/1998
0.25Gb
0.20-micron 256Mb SDRAM (samples from 8/1998 in Japan)
- Maker
- Others
- Type
- SDR
10/2002
0.5Gb
0.10-micron 512Mb DDR (development announced)
- Maker
- SK hynix
- Type
- DDR
8/2003
1Gb
0.11-micron 1Gb DDR2 (development completed)
- Maker
- SK hynix
- Type
- DDR
9/2004
2Gb
- Maker
- Samsung
- Type
- DDR
3/2011
4Gb
30nm-class 4Gb LPDDR2 (mass production)
- Maker
- Samsung
- Type
- LPDDR
4/2014
8Gb
20nm-class 8Gb DDR4 (128GB TSV module announced)
- Maker
- SK hynix
- Type
- DDR
1/2018
16Gb
10nm-class 16Gb GDDR6 (mass production)
- Maker
- Samsung
- Type
- GDDR
12/2021
24Gb
1anm 24Gb DDR5 (samples shipped)
- Maker
- SK hynix
- Type
- DDR
9/2023
32Gb
12nm-class 32Gb DDR5 (development)
- Maker
- Samsung
- Type
- DDR
12 records, oldest first. Each die beat every earlier die on data rate.
2/1998
100MT/s
64Mb SDRAM for PC100 (mass production; the release names the maker Hyundai Electronics)
- Maker
- SK hynix
- Type
- SDR
6/1999
266MT/s
0.22 micron 128Mb DDR (samples; release names the maker HEI)
- Maker
- SK hynix
- Type
- DDR
11/2001
333MT/s
128Mb DDR333 (volume production)
- Maker
- Others
- Type
- DDR
10/2002
400MT/s
0.10-micron 512Mb DDR (development announced)
- Maker
- SK hynix
- Type
- DDR
9/2003
667MT/s
0.11-micron 512Mb DDR2 (samples to Intel)
- Maker
- SK hynix
- Type
- DDR
12/2006
800MT/s
60nm 1Gb DDR2 (introduced; Intel validated)
- Maker
- SK hynix
- Type
- DDR
6/2007
3200MT/s
512Mb GDDR4 (supply for AMD Radeon HD 2900XT cards)
- Maker
- Samsung
- Type
- GDDR
1/2015
8000MT/s
20nm 8Gb GDDR5 (mass production)
- Maker
- Samsung
- Type
- GDDR
1/2018
18000MT/s
10nm-class 16Gb GDDR6 (mass production)
- Maker
- Samsung
- Type
- GDDR
9/2020
21000MT/s
8Gb GDDR6X (available; in GeForce RTX 3080 and 3090)
- Maker
- Micron
- Type
- GDDR
7/2023
32000MT/s
- Maker
- Samsung
- Type
- GDDR
10/2024
40000MT/s
24Gb GDDR7 (development; commercial supply planned early 2025)
- Maker
- Samsung
- Type
- GDDR
3 records, oldest first. Each die beat every earlier die on bit density.
2022
0.22Gb/mm2
16Gb DDR5 (D1y, die K4RAH046VB, in a retail module; secondary source)
- Maker
- Samsung
- Type
- DDR
2022
0.24Gb/mm2
16Gb DDR5 (D1z, die Y32A, in a retail module; secondary source)
- Maker
- Micron
- Type
- DDR
11/2024
0.44Gb/mm2
16Gb LPDDR5X (D1b, found in a Vivo X200 Pro Satellite; secondary source)
- Maker
- Samsung
- Type
- LPDDR
How to read it
Each point is one DRAM die that a vendor release, datasheet or paper describes. It sits at the date of the earliest public source cited for that die, which is the date of the announcement or production news and not the date the die reached modules on shelves. The chart shows 88 dies from 87 public sources, and the JEDEC revisions cite 5 more. It is not every die ever made, and a die with no stated value for the chosen measure is left off. It runs from 1998 to 2026. The Type and Maker chips filter the chart and the tables below. Stacked HBM has its own timeline.
Data rate is the speed the shipping part was specified at, from a datasheet or a vendor release, in MT/s: a GDDR7 die at 32Gb/s per pin is 32,000MT/s. A paper's test chip can run faster than anything sold, so a rate printed only for a test chip is not shown. Data rate uses a log scale, because a graphics die runs several times faster than a DDR die of the same year. The dashed line is the fastest data rate any JEDEC DDR revision had defined by each date, so it applies to DDR main memory and not to LPDDR or GDDR.
Density is in gigabits per die and uses a log scale, where each gridline step multiplies the value rather than adding to it. Vendors name their process nodes differently, so the node class is in the tables as the vendor prints it and is not charted. A rate marked as up to is the top speed the vendor states for the part.
Every die and its source
One table per family, newest generation first, with a line between generations and the newest die first within each.
- means the maker hasn't published this figure.
- D Derived: worked out from two figures in the source, not stated by it.
Tap any column heading to sort that table by it. Tap it again to reverse the order.
SDR 3 dies
Single data rate dies, the main memory before DDR.
| Die | Vendor | Generation | Node class | Status | Date | Density | Data rate | Source | Note |
|---|---|---|---|---|---|---|---|---|---|
| 0.18-micron 256Mb PC133 SDRAM (samples from 8/1999 in Japan) | Hitachi | SDR | 0.18 micron | Announced | 6/1999 | 0.25Gb | 133MT/s | Hitachi 1999 release | |
| 0.20-micron 256Mb SDRAM (samples from 8/1998 in Japan) | Hitachi | SDR | 0.20 micron | Announced | 7/1998 | 0.25Gb | 100MT/s | Hitachi 1998 release | |
| 64Mb SDRAM for PC100 (mass production; the release names the maker Hyundai Electronics) | SK hynix | SDR | not published | Mass production | 2/1998 | 0.063Gb | 100MT/s | SK hynix 1998 release | Hyundai Electronics, now SK hynix. The release stresses CAS latency 2 at PC100 and a 6ns access time. |
DDR main memory 64 dies
DDR through DDR5, the dies on desktop, laptop and server memory modules.
| Die | Vendor | Generation | Node class | Status | Date | Density | Data rate | Source | Note |
|---|---|---|---|---|---|---|---|---|---|
| 32Gb DDR5 (1b, in a 256GB server RDIMM) | SK hynix | DDR5 | 1b (fifth-generation 10nm-class) | Announced | 12/2025 | 32Gb | not published | SK hynix 2025 release | The release announces Intel Xeon 6 certification of the module; it gives no data rate. The page header says December 17 and the dateline December 18, 2025. |
| 24Gb DDR5 (shown at IC China) | CXMT | DDR5 | not published | Announced | 11/2025 | 24Gb | 8000MT/s | CXMT 2025 release | |
| 1B (10nm-class) 16Gb DDR5-5600 (delivered) | Nanya | DDR5 | 10nm-class (1B) | Mass production | 4/2025 | 16Gb | 5600MT/s | Nanya Technology 2025 release | |
| 1γ 16Gb DDR5 (samples shipped) | Micron | DDR5 | 1γ (1-gamma) | Sampling | 2/2025 | 16Gb | 9200MT/s | Micron 2025 release | |
| 1c 16Gb DDR5 (developed; mass production planned 2024) | SK hynix | DDR5 | 1c | Announced | 8/2024 | 16Gb | 8000MT/s | SK hynix 2024 release | |
| 1β 32Gb monolithic DDR5 (validated and shipping in 128GB RDIMM) | Micron | DDR5 | 1β (1-beta) | Mass production | 5/2024 | 32Gb | 5600MT/s | Micron 2024 release | |
| 1β 32Gb monolithic DDR5 (announced, in 128GB RDIMM) | Micron | DDR5 | 1β (1-beta) | Announced | 11/2023 | 32Gb | 8000MT/s | Micron 2023 release | |
| 1β 16Gb DDR5 (shipping) | Micron | DDR5 | 1β (1-beta) | Mass production | 10/2023 | 16Gb | 7200MT/s | Micron 2023 release | |
| 12nm-class 32Gb DDR5 (development) | Samsung | DDR5 | 12nm-class | Announced | 9/2023 | 32Gb | not published | Samsung 2023 release | |
| 12nm-class 16Gb DDR5 (mass production) | Samsung | DDR5 | 12nm-class | Mass production | 5/2023 | 16Gb | 7200MT/s | Samsung 2023 release | |
| 16Gb DDR5 die Rev A (datasheet Rev C) | Micron | DDR5 | not published | Announced | 1/2023 | 16Gb | 4800MT/s | Micron 2023 product page | |
| 12nm-class 16Gb DDR5 (development) | Samsung | DDR5 | 12nm-class | Announced | 12/2022 | 16Gb | 7200MT/s | Samsung 2022 release | |
| 16Gb DDR5 (D1y, die H5CNAG8NM, in a retail module; secondary source) | SK hynix | DDR5 | not published | Mass production | 2022 | 16Gb | not published | TechInsights 2022 teardown | Dated by the teardown, not a vendor release. A first-generation DDR5 die in a retail module. |
| 16Gb DDR5 (D1y, die K4RAH046VB, in a retail module; secondary source) | Samsung | DDR5 | not published | Mass production | 2022 | 16Gb | not published | TechInsights 2022 teardown | Dated by the teardown, not a vendor release. A first-generation DDR5 die in a retail module. |
| 16Gb DDR5 (D1z, die Y32A, in a retail module; secondary source) | Micron | DDR5 | not published | Mass production | 2022 | 16Gb | not published | TechInsights 2022 teardown | Dated by the teardown, not a vendor release. A first-generation DDR5 die in a retail module. |
| 1anm 24Gb DDR5 (samples shipped) | SK hynix | DDR5 | 1anm | Sampling | 12/2021 | 24Gb | not published | SK hynix 2021 release | |
| 14nm EUV DDR5 (mass production) | Samsung | DDR5 | 14nm | Mass production | 10/2021 | not published | 7200MT/s | Samsung 2021 release | |
| 1Ynm 16Gb DDR5 (developed; RDIMM and UDIMM supplied to a chipset maker) | SK hynix | DDR5 | 1Ynm | Announced | 11/2018 | 16Gb | 5200MT/s | SK hynix 2018 release | |
| 1B (10nm-class) 8Gb DDR4 (volume production) | Nanya | DDR4 | 1B | Mass production | 7/2025 | 8Gb | not published | Nanya Technology 2025 release | |
| 1α DDR4 (volume production; to 16Gb range; die area from a secondary source) | Micron | DDR4 | 1α (1-alpha) | Mass production | 2021 | not published | not published | Micron 2021 releaseTechInsights 2021 teardown | |
| 1Znm 16Gb DDR4 (developed) | SK hynix | DDR4 | 1Znm | Announced | 10/2019 | 16Gb | 3200MT/s | SK hynix 2019 release | |
| 8Gb DDR4 (mass production announced) | CXMT | DDR4 | not published | Mass production | 9/2019 | 8Gb | not published | CXMT 2019 release | |
| 1z nm 16Gb DDR4 (mass production) | Micron | DDR4 | 1z nm | Mass production | 8/2019 | 16Gb | not published | Micron 2019 release | |
| 3rd-generation 10nm-class (1z) 8Gb DDR4 (development) | Samsung | DDR4 | 3rd-generation 10nm-class (1z-nm) | Announced | 3/2019 | 8Gb | not published | Samsung 2019 release | |
| 1Ynm 8Gb DDR4 (developed) | SK hynix | DDR4 | 1Ynm | Announced | 11/2018 | 8Gb | 3200MT/s | SK hynix 2018 release | |
| 20nm 8Gb DDR4 (mass production) | Nanya | DDR4 | 20nm | Mass production | 1/2018 | 8Gb | not published | Nanya Technology 2018 release | |
| 2nd-generation 10nm-class (1y) 8Gb DDR4 (mass production) | Samsung | DDR4 | 2nd-generation 10nm-class (1y-nm) | Mass production | 12/2017 | 8Gb | 3600MT/s | Samsung 2017 release | |
| 10nm-class (1x) 8Gb DDR4 (mass production) | Samsung | DDR4 | 10nm-class (1x) | Mass production | 4/2016 | 8Gb | 3200MT/s | Samsung 2016 release | |
| 20nm 8Gb DDR4 (mass production) | Samsung | DDR4 | 20nm | Mass production | 10/2014 | 8Gb | 2400MT/s | Samsung 2014 release | |
| 20nm-class 4Gb DDR4 (16GB NVDIMM announced) | SK hynix | DDR4 | 20nm class | Announced | 10/2014 | 4Gb | 2133MT/s | SK hynix 2014 release | |
| 20nm-class 8Gb DDR4 (128GB TSV module announced) | SK hynix | DDR4 | 20nm class | Announced | 4/2014 | 8Gb | 2133MT/s | SK hynix 2014 release | |
| 30nm 4Gb DDR4 (sampling) | Nanya | DDR4 | 30nm | Sampling | 7/2012 | 4Gb | not published | Nanya Technology 2012 release | |
| 30nm 4Gb DDR4 (sampling) | Micron | DDR4 | 30nm | Sampling | 5/2012 | 4Gb | 2400MT/s | Micron 2012 release | |
| 30nm-class 2Gb DDR4 (developed) | SK hynix | DDR4 | 30nm class | Announced | 4/2011 | 2Gb | 2400MT/s | SK hynix 2011 release | |
| 20nm 4Gb DDR3 (volume shipment) | Nanya | DDR3 | 20nm | Mass production | 10/2017 | 4Gb | not published | Nanya Technology 2017 release | |
| 25nm 8Gb monolithic DDR3 (announced) | Micron | DDR3 | 25nm | Announced | 7/2014 | 8Gb | not published | Micron 2014 release | |
| 30nm 4Gb DDR3 (sampling) | Nanya | DDR3 | 30nm | Sampling | 5/2014 | 4Gb | not published | Nanya Technology 2014 release | |
| 20nm 4Gb DDR3 (mass production) | Samsung | DDR3 | 20nm | Mass production | 3/2014 | 4Gb | not published | Samsung 2014 release | |
| 20nm-class 4Gb DDR3 (shown at MWC, volume production planned 1H 2012) | SK hynix | DDR3 | 20nm class | Announced | 2/2012 | 4Gb | 2133MT/s | SK hynix 2012 release | |
| 42nm 2Gb DDR3 (joint Micron and Nanya) | Nanya | DDR3 | 42nm | Announced | 2/2010 | 2Gb | 1866MT/s | Micron 2010 release | |
| 40nm-class 2Gb DDR3 (Intel validation, mass production begun) | SK hynix | DDR3 | 40nm class | Mass production | 11/2009 | 2Gb | 1333MT/s | SK hynix 2009 release | |
| 54nm 1Gb DDR3 second generation (mass production) | SK hynix | DDR3 | 54nm | Mass production | 10/2009 | 1Gb | not published | SK hynix 2009 release | |
| 50nm 2Gb DDR3 (mass production) | Samsung | DDR3 | 50nm | Mass production | 9/2008 | 2Gb | not published | Samsung 2008 release | |
| 66nm 1Gb DDR3 (SO-DIMM validation; component validated 10/2007 per the release) | SK hynix | DDR3 | 66nm | Announced | 4/2008 | 1Gb | 1066MT/s | SK hynix 2008 release | |
| 78nm 2Gb DDR3 (sampling modules) | Micron | DDR3 | 78nm | Sampling | 10/2007 | 2Gb | 1333MT/s | Micron 2007 release | |
| 78nm 1Gb DDR3 (evaluation samples) | Micron | DDR3 | 78nm | Sampling | 5/2007 | 1Gb | 1066MT/s | Micron 2007 release | |
| 80nm 1Gb DDR3 (first Intel validation) | SK hynix | DDR3 | 80nm | Announced | 5/2007 | 1Gb | 1066MT/s | SK hynix 2007 release | |
| 50nm 2Gb DDR2 (announced, sampling planned 9/2010) | Micron | DDR2 | 50nm | Announced | 7/2010 | 2Gb | not published | Micron 2010 release | |
| 50nm 1Gb DDR2 (mass production) | Samsung | DDR2 | 50nm | Mass production | 4/2008 | 1Gb | not published | Samsung 2008 release | |
| 50nm-class 1Gb DDR2 (Intel validation) | SK hynix | DDR2 | 50nm-class | Announced | 11/2007 | 1Gb | not published | SK hynix 2007 release | |
| 60nm-class 2Gb DDR2 (announced) | Samsung | DDR2 | 60nm-class | Announced | 9/2007 | 2Gb | not published | Samsung 2007 release | |
| 60nm-class 1Gb DDR2 (mass production) | Samsung | DDR2 | 60nm-class | Mass production | 3/2007 | 1Gb | not published | Samsung 2007 release | |
| 60nm 1Gb DDR2 (introduced; Intel validated) | SK hynix | DDR2 | 60nm | Announced | 12/2006 | 1Gb | 800MT/s | SK hynix 2006 release | |
| 75nm 512Mb DDR2 (qualified, Qimonda joint development) | Nanya | DDR2 | 75nm | Mass production | 9/2006 | 0.5Gb | not published | Nanya Technology and Qimonda 2006 release | |
| 80nm 1Gb DDR2 (mass production; secondary source) | Samsung | DDR2 | 80nm | Mass production | 9/2006 | 1Gb | not published | EE Times 2006 release | |
| 80nm 2Gb DDR2 (announced) | Samsung | DDR2 | 80nm | Announced | 9/2004 | 2Gb | not published | Samsung 2004 release | |
| 0.11-micron 512Mb DDR2 (samples to Intel) | SK hynix | DDR2 | .11-micron | Sampling | 9/2003 | 0.5Gb | 667MT/s | SK hynix 2003 release | |
| 0.11-micron 1Gb DDR2 (development completed) | SK hynix | DDR2 | 0.11-micron | Announced | 8/2003 | 1Gb | not published | SK hynix 2003 release | |
| 0.14u 256Mb DDR400 (announced) | Nanya | DDR | 0.14u | Announced | 2/2003 | 0.25Gb | 400MT/s | Nanya Technology 2003 release | |
| 256Mb DDR400 (sample and mass production quantities) | SK hynix | DDR | not published | Mass production | 2/2003 | 0.25Gb | 400MT/s | SK hynix 2003 release | |
| 0.10-micron 512Mb DDR (development announced) | SK hynix | DDR | 0.10-micron | Announced | 10/2002 | 0.5Gb | 400MT/s | SK hynix 2002 release | |
| 128Mb DDR333 (volume production) | Nanya | DDR | not published | Mass production | 11/2001 | 0.13Gb | 333MT/s | Nanya Technology 2001 release | |
| 256Mb DDR333 (volume production) | Nanya | DDR | not published | Mass production | 11/2001 | 0.25Gb | 333MT/s | Nanya Technology 2001 release | |
| 0.22 micron 128Mb DDR (samples; release names the maker HEI) | SK hynix | DDR | 0.22 micron | Sampling | 6/1999 | 0.13Gb | 266MT/s | SK hynix 1999 release |
JEDEC DDR revisions behind the dashed line
| Revision | Published | Maximum data rate | Source |
|---|---|---|---|
| DDR5 JESD79-5C | 4/2024 | 8800MT/s | JEDEC Updates JESD79-5C DDR5 SDRAM Standard: Elevating Performance and Security for Next-Gen Technologies |
| DDR5 JESD79-5A | 10/2021 | 6400MT/s | JEDEC Publishes Update to DDR5 SDRAM Standard Used in High-Performance Computing Applications |
| DDR5 JESD79-5 | 7/2020 | 4800MT/s | JEDEC Publishes New DDR5 Standard for Advancing Next-Generation High Performance Computing Systems |
| DDR4 JESD79-4 | 9/2012 | 3200MT/s | JEDEC Announces Publication of DDR4 Standard |
| DDR3 JESD79-3 | 6/2007 | 1600MT/s | JEDEC Publication of JEDEC DDR3 SDRAM Standard |
The dashed line on the data rate chart steps up at each revision. Each revision is dated by JEDEC's own first publication of it, from its public page or press release.
LPDDR mobile memory 12 dies
Low-power dies for phones, tablets and thin laptops, usually soldered next to the processor.
| Die | Vendor | Generation | Node class | Status | Date | Density | Data rate | Source | Note |
|---|---|---|---|---|---|---|---|---|---|
| 16GB LPDDR6 (sampled and validated on a Qualcomm Snapdragon platform) | Samsung | LPDDR6 | not published | Sampling | 9/2026 | not published | 10700MT/s | Samsung 2026 release | Samsung gives up to 114GB/s and up to 21% better power efficiency than LPDDR5X for its LPDDR6. |
| 1c 16Gb LPDDR6 (development; supply planned for 2H 2026) | SK hynix | LPDDR6 | 1c | Announced | 3/2026 | 16Gb | ≥10700MT/s | SK hynix 2026 release | |
| LPDDR5T (samples in 16GB multi-chip packages) | SK hynix | LPDDR5T | 1anm | Sampling | 1/2023 | not published | 9600MT/s | SK hynix 2023 release | T for Turbo is SK hynix's own name. The release calls it an upgraded LPDDR5X, not a new JEDEC generation. |
| 1cnm LPDDR5X (in a 192GB SOCAMM2 module, mass production) | SK hynix | LPDDR5X | 1cnm (sixth-generation 10nm-class) | Mass production | 4/2026 | not published | not published | SK hynix 2026 release | Dated by the module release. It gives no die density or data rate for the LPDDR5X die. |
| 1γ LPDDR5X (qualification samples) | Micron | LPDDR5X | 1γ (1-gamma) | Sampling | 6/2025 | not published | 10700MT/s | Micron 2025 release | Micron calls it the first LPDDR5X on its 1γ node; the release does not give the die density. |
| 16Gb LPDDR5X (D1b, found in a Vivo X200 Pro Satellite; secondary source) | Samsung | LPDDR5X | D1b (mid-12nm class) | Mass production | 11/2024 | 16Gb | not published | TechInsights 2024 teardown | Dated by the teardown, not a Samsung release. The die was in a shipping phone, die marking K4K6E165YE. |
| 12nm-class 10.7Gbps LPDDR5X (development) | Samsung | LPDDR5X | 12nm-class | Announced | 4/2024 | not published | 10700MT/s | Samsung 2024 release | |
| 10nm-class 12Gb LPDDR5 (mass production) | Samsung | LPDDR5 | 10nm-class | Mass production | 7/2019 | 12Gb | 5500MT/s | Samsung 2019 release | |
| 10nm-class 8Gb LPDDR5 (development) | Samsung | LPDDR5 | 10nm-class | Announced | 7/2018 | 8Gb | 6400MT/s | Samsung 2018 release | |
| 20nm 8Gb LPDDR4 (mass production) | Samsung | LPDDR4 | 20nm | Mass production | 12/2014 | 8Gb | 3200MT/s | Samsung 2014 release | |
| 20nm-class 4Gb LPDDR3 (mass production) | Samsung | LPDDR3 | 20nm-class | Mass production | 4/2013 | 4Gb | 2133MT/s | Samsung 2013 release | |
| 30nm-class 4Gb LPDDR2 (mass production) | Samsung | LPDDR2 | 30nm-class | Mass production | 3/2011 | 4Gb | 1066MT/s | Samsung 2011 release |
GDDR graphics memory 9 dies
Graphics dies, soldered around a GPU and run at the highest data rates on this page.
| Die | Vendor | Generation | Node class | Status | Date | Density | Data rate | Source | Note |
|---|---|---|---|---|---|---|---|---|---|
| 24Gb GDDR7 (development; commercial supply planned early 2025) | Samsung | GDDR7 | 5th-generation 10nm-class | Announced | 10/2024 | 24Gb | 40000MT/s | Samsung 2024 release | |
| GDDR7 (introduced; mass production planned 3Q 2024) | SK hynix | GDDR7 | not published | Announced | 7/2024 | not published | 32000MT/s | SK hynix 2024 release | The release gives no die density or node name. |
| 1β GDDR7 (sampling; available 2H 2024) | Micron | GDDR7 | 1β | Sampling | 6/2024 | not published | 32000MT/s | Micron 2024 release | |
| 16Gb GDDR7 (development) | Samsung | GDDR7 | not published | Announced | 7/2023 | 16Gb | 32000MT/s | Samsung 2023 release | Uses PAM3 signaling, three levels, in place of the two-level NRZ of earlier GDDR. |
| 16Gb GDDR6X (volume production; in GeForce RTX 3090 Ti) | Micron | GDDR6X | not published | Mass production | 4/2022 | 16Gb | 21000MT/s | Micron 2022 release | Twice the capacity of the 8Gb GDDR6X and up to 15% higher performance, per Micron. |
| 8Gb GDDR6X (available; in GeForce RTX 3080 and 3090) | Micron | GDDR6X | not published | Mass production | 9/2020 | 8Gb | 21000MT/s | Micron 2020 release | The first memory to use PAM4 signaling, four levels carrying two bits per transfer, per Micron. |
| 10nm-class 16Gb GDDR6 (mass production) | Samsung | GDDR6 | 10nm-class | Mass production | 1/2018 | 16Gb | 18000MT/s | Samsung 2018 release | |
| 20nm 8Gb GDDR5 (mass production) | Samsung | GDDR5 | 20nm | Mass production | 1/2015 | 8Gb | 8000MT/s | Samsung 2015 release | |
| 512Mb GDDR4 (supply for AMD Radeon HD 2900XT cards) | Samsung | GDDR4 | not published | Mass production | 6/2007 | 0.5Gb | 3200MT/s | Samsung 2007 release | The release says Samsung was the only maker of GDDR4 in production, and that a 1GB Radeon HD 2900XT card carried 16 of these dies. |
DDR5, LPDDR5X, GDDR7 and HBM side by side, from JEDEC only
| Standard | JEDEC document | Data rate JEDEC states | Organisation | Supply voltage |
|---|---|---|---|---|
| DDR5 | JESD79-5 | 4.8Gb/s per pin expected at launch JEDEC 2020 release | Burst length 16, 32 banks; a DIMM has two 40-bit independent sub-channels JEDEC 2020 release | Vdd 1.1V JEDEC 2020 release |
| DDR5 | JESD79-5C | Timing parameters defined up to 8,800Mb/s JEDEC 2024 release | not published | not published |
| LPDDR5X | JESD209-5B | Not stated for LPDDR5X itself; the same revision lifts LPDDR5 to up to 8,533Mb/s from 6,400Mb/s JEDEC 2021 standard | not published | not published |
| GDDR7 | JESD239F | Up to 192GB/s per device; the standard's clocking example is 28Gb/s per pin, 14 gigabaud PAM3 JEDEC 2024 standardJEDEC 2026 standard | Four independent channels, 16 banks per channel, 32n prefetch of 256 bits, PAM3 signalling JEDEC 2026 standard | VDD and VDDQ 1.2V JEDEC 2026 standard |
| HBM3 | JESD238B.01 | Up to 6.4Gb/s per pin, 819GB/s per device JEDEC 2022 standard | Up to 16 channels per stack, 64 data pins per channel, 256-bit prefetch, burst length 8 JEDEC 2025 standard | I/O 1.1V, transmit driver 0.4V JEDEC 2025 standard |
| HBM4 | JESD270-4 | Up to 8Gb/s per pin over a 2,048-bit interface JEDEC 2025 standard | not published | not published |
Every cell is a figure from a JEDEC standard, its public page or its press release, and links to that source. The standards are written differently, so a dash means the JEDEC pages saved here do not state the figure; it does not mean the standard lacks it. Vendor figures for shipping dies sit in the tables above and are not mixed in.
Each value links to the source it was read from. A figure a paper reports for a test chip is not the same as a shipping part's. The Note column is a short remark on an unusual part, from the sources in its row. On a phone, swipe a table sideways to see every column.
Download the dies and their sources: CSV or JSON. Each row is one sourced value with the source it was read from, and the D and T marks as columns.
Research papers and makers’ speeds
What the newest research chips reached on a bench, and the most each maker lists for a part it sells. Neither is a measured product, so neither is drawn on the chart above.
8 ISSCC papers, 2023 to 20268 rows
Newest first. Each speed is the one printed in the paper’s title, because the full papers are behind a paywall, and a title does not say what the speed was measured on. The bar compares a paper only with others in the same unit.
Makers’ listed speeds7 rows
Quoted from each maker’s product page, with the generation the page names. An “up to” speed is a ceiling the maker chose, not what a part delivers in a computer, and the pages carry no date, so none is shown. SK hynix’s product pages could not be read, so no SK hynix speed is listed.
| Maker | Generation | Listed as | Speed |
|---|---|---|---|
| Micron | DDR5 | “RDIMM speeds up to 9200 MT/s and MRDIMM up to 8800 MT/s” | 9200 MT/s |
| Micron | LPDDR5 | “peak speeds of up to 6.4 Gb/s” | 6.4 Gb/s |
| Samsung | LPDDR5X | “up to 10.7 Gbps data processing speeds” | 10.7 Gbps |
| Micron | GDDR7 | “total system bandwidth is greater than 1.5 TB/s with a 32 Gb/s data rate” | 32 Gb/s |
| SK hynix | DDR5 | “While 16Gb or 24Gb DDR5 can process data at a rate of 5,600Mbps at present” | 5600 Mbps |
| SK hynix | LPDDR5 | “18GB of capacity and 6,400Mbps in transfer speeds” | 6400 Mbps |
| SK hynix | GDDR7 | “a boosted speed of up to 32Gbps” | 32 Gbps |
What it will not tell you
A die sits at the date of its release, not the date modules with it shipped in volume. Vendors do not all publish the same numbers, so a die with no stated speed is not on the data rate chart even when its density is known. Die area is published for few of these parts: it comes from TechInsights teardowns of shipping dies, and the bit density chart draws only dies with both a density and an area. For stacked DRAM on accelerators, see the HBM Timeline, and for the flash side, the NAND Die Timeline. ISSCC, IEDM and the VLSI Symposium, where device papers on these dies are published, are on the events calendar.
The guides behind this data
- Working Memory, Part 2: DRAM From the Inside
How a DRAM cell is read and refreshed, how banks and ranks organize it, what DDR timing numbers measure, and how one cell serves three buses.
- Working Memory, Part 5: Current Memory ICs
A sourced guide to the DRAM chips in use now: DDR5, LPDDR5X, GDDR7 and HBM3E and HBM4, what is shipping, what is only sampling, and what is still research.
- Photolithography, Part 3: High-NA EUV and What It Means for Memory
High-NA EUV’s anamorphic optics and half field, what comes after it, nanoimprint, and why DRAM took EUV while 3D NAND scaled by stacking instead.