Working Memory, Part 1: SRAM and the Processor Cache

The memory map drew the memory hierarchyThe memory hierarchy combines memories that differ in cost, speed and power, from SRAM cache on the processor to DRAM main memory and storage, to act like one ideal memory. but skipped the cacheA processor cache is a small SRAM memory on the processor die that copies main-memory data the processor will likely need soon. Each added level is bigger and slower. on the processor die at its top. This part opens the cell that cache is made of, static RAM, or SRAMSRAM is fast memory of latching cells with several transistors each. It needs no refresh but takes far more area per bit than DRAM, so it serves as on-chip memory., and asks why every fast processor spends so much of its die on it. The L1, L2 and L3 entries on a CPU specification are small, fast, and costly in area and power, and extra last-level cache now sometimes sits on a second, stacked die. This is Part 1 of the Working Memory series, on the memory a processor works out of.

Three things are left to other pages. Part 2 covers the DRAM cell, its read and its refresh. Memories proposed for the cache are in Beyond NAND, Part 3. SRAM inside an SSD controller is in Flash Foundations Part 5. Everything else is on the series page.

Parenthetical tags give the source type. Vendor is the company’s own document or claim, and the sentence names the company. Lecture is university course slides, used for mechanism and rounded teaching numbers. Roadmap is IRDS, the IEEE roadmap. Research study is an imec design for cells no product uses yet. Where only an abstract or a title was read, the text says so, and derived means arithmetic on numbers already given. Latencies stay in cycles, and the text never turns cycles into nanoseconds without a stated clock.

Six transistors hold one bit

An SRAM cell is a latch built from two inverters that hold each other, plus two switches that let the outside world read or change what they hold. Naming the six transistors and walking through one read and one write makes “fast”, “large” and “leaky” in the next sections point at something physical.

Two inverters that hold each other

An MIT lecture describes the 6T cell as two CMOS inverters, four transistors, each driving the other’s input. That loop has two stable states, and one of them is the stored bit. Two access transistors connect the two storage nodes to a pair of bitlines (lecture). IRDS calls the six-transistor cell the conventional SRAM cell (IRDS 2022 More Moore, roadmap). Most commercial chips use it, and a Harvey Mudd lecture says the cell is most of an SRAM array’s area (lecture). A UCSB lecture says embedded SRAM in microprocessor caches uses 6T cells (lecture). The 1996 cell table that the next section uses also lists four-transistor cells with resistor or thin-film-transistor loads, which that section compares with the six-transistor cell.

Reading without flipping it

To read, the drivers precharge both bitlines to the supply voltage and leave them floating. Next the decoder raises one wordline. Each cell on that word slowly pulls one of its two bitlines toward ground, and a sense amplifierA sense amplifier compares the current or voltage of a selected cell against a reference to decide which stored level the cell holds. detects the difference (lecture). The cell’s pull-down transistor is sized slightly stronger than the access transistorAn access transistor is the switch that connects one memory cell to its bit line when the cell’s word line rises, so only the selected row is read or written.. A stronger pull-down raises the cell’s read noise margin. MIT’s lecture puts it plainly. The transistors are sized so that writes overpower the cell but reads don’t. Static noise margin names how much disturbance the pair tolerates, and it cannot exceed half the supply even with ideal inverters (lecture, UCSB).

Writing by overpowering it

To write, the drivers hold the bitlines at the new value while the wordline rises, and they overpower the cell. Keeping the ratio of pull-up to access transistor below about 1.8 lets them (lecture, UCSB). That same sizing makes reads safe and writes possible. A single-port SRAM does one read or one write per cycle, and adding ports grows the cell (lecture, MIT).

No refresh

The latch holds the bit as long as the supply is on, which DRAM can’t do, because DRAM needs periodic refresh (CUHK lecture, lecture). Static does not mean non-volatile. Power off and the bit is gone. Part 2 explains DRAM’s refresh as a row operation.

Figure 1.1 draws one cell twice. On the left, the bitlines start high and one side of the cell pulls a bitline down through the access and pull-down transistors, which is the read. On the right, the drivers force the bitlines to opposite values and overpower the pull-up transistors, which is the write. The figure’s only number is the sizing ratio, which comes from a lecture.

Why it is fast, and why it is large

Both properties come from the same six transistors. An actively driven latch beside the logic is fast. Six transistors and their contacts take about 20 times the area of a DRAM cell (lecture).

Speed

In the MIT lecture’s rounded teaching table, SRAM is 1ns to 10ns for roughly 10KB to 10MB, and DRAM is 80ns for roughly 10GB (lecture). A held cell drives its own bitline from a stored state, where a DRAM cell shares a small charge with a long line and needs a sense step and a restore, which Part 2’s read cycle walks through. On TSMC’s account, SRAM sits on the logic chip as cache for the fastest access, and DRAM is about 10 times slower (TSMC, vendor).

Area in F²

Cell area is counted in units of F², where F is the smallest feature a process can draw, and the memory map explains the unit. A UCSD lecture lists a 65nm 6T cell at 0.52µm² and, citing ITRS 2008, gives the cell size as 123F² to 140F² (lecture). Lage and colleagues (Motorola, IEDM 1996) tabulated real cells. Their table lists simple 6T cells at 167F² to 176F², advanced 6T cells at 64F² to 166F², and four-transistor cells at 45F² to 63F². Six-transistor cells have been dominant for on-chip storage in advanced microprocessors (paper). That paper also says four-transistor cells are typically smaller but generally need a more complex process and have poorer stability, especially at low voltage. A 2026 review in Communications Engineering still says a cell occupies approximately 140F² (secondary).

Against the DRAM cell

IRDS puts the common DRAM cell today at 6F² (IRDS, roadmap). That count cannot be divided into the SRAM count above, because the two use different F. IRDS measures F as the DRAM half-pitch (IRDS, roadmap). UCSD’s count fits its own numbers, since 0.52µm² over a 65nm F squared is 123F² (derived), which sits at the low end of its range. A lecture from MIT compares the two cells without F, and Part 2 cites it too. In its rounded teaching figure, a one-transistor DRAM cell with a trench capacitor is about 20 times smaller in area than an SRAM cell (lecture). That gap is one reason a processor holds megabytes of SRAM and a DIMM holds gigabytes of DRAM.

Figure 1.2 draws each cell on a grid of its own F, with rectangles that show area and not layout shape. SRAM’s rectangle covers 123 to 140 squares, and the dashed outline marks where the smaller count ends. The DRAM cell covers six squares of its own F, drawn in a separate panel because its squares are not the same size as SRAM’s.

A cell that always draws current

A held latch leaks while it holds, and a cache is millions of held latches. The cost shows up in a 2005 paper and in the choices designers made about it.

Leakage while holding

Power reaches the latch for as long as it holds data. Kim, Blaauw and Mudge (IEEE TVLSI, 2005) say the on-chip L1 and L2 caches are a sizeable fraction of microprocessor power, and that subthreshold leakage is becoming one of their dominant components. Among SRAM’s costs, the 2026 review lists high leakage power (secondary).

How large the share became

Kim and colleagues cite a 90nm Pentium 4 at 110W with roughly 40% of its power in leakage (paper). Its own analysis puts the largest share of cache leakage in the SRAM cell array. Homayoun and Veidenbaum (UC Irvine, ICCD 2007) model a 4MB L2 at 65nm with CACTI 5 (paper, modeled). Across the SPEC2K benchmarks, leakage averages above 90% of the L2’s total power. Both figures are dated and labeled with node and year, and they have different denominators. One is a whole processor and the other is one cache.

What designers trade

Slower transistors with a higher threshold leak less. In Kim and colleagues’ simulation, a 256KB L2 built that way kept the average access time of a 128KB L2 and cut L2 leakage power by 70% (paper, simulated). Homayoun’s model adds that the peripheral circuits leak about 90% of what remains once the cells use high-threshold devices, because they use larger, leakier transistors (paper).

Figure 1.3 puts the two figures on one axis, each tagged with its year and denominator. Read them as two points in time and two scopes. They show leakage as a large share of one processor’s power in 2005 and most of one modeled cache’s power in 2007, and they do not show what leakage is at a node built today.

Why caches are built from it

Large memories are slow even when built from fast parts. Per the MIT lecture, that is why a hierarchy is used to fake a large, fast, cheap memory (lecture). SRAM is the fast part, built in the same process as the logic beside it, as the CUHK lecture puts it (lecture).

L1, L2 and L3 on one die

To read the cache entries on a CPU specification, the cleanest way is to put vendor tables side by side. Intel’s optimization manual gives, for Sandy Bridge, a 32KB L1 data cache at 4 cycles best case and 5 in the common case, a 256KB L2 at 12 cycles, and a shared last-level cache at 26 to 31 cycles (Intel 356477, vendor). Intel adds that the actual latency varies with cache queue occupancy and ring occupancy. Volume 1 of the current manual gives the Skylake server core a 32KB L1 data cache at 4 to 6 cycles (Intel 248966, vendor). Its L2 is 1MB at 14 cycles. Its last-level cache holds up to 1.375MB per core and takes 50 to 70 cycles. For the Ice Lake client core, the manual gives a 48KB L1 data cache at 5 cycles and a 512KB L2 cache at 13 cycles.

AMD’s Zen 5 optimization guide gives a 48KB, 12-way L1 data cache with a 4- or 5-cycle integer load-to-use latency, a 1MB L2 per core at no less than 14 cycles, and an L3 of up to 96MB, depending on the part, shared inside a CPU complex at an average of 46 cycles (AMD 58455, vendor). AMD’s Hot Chips 2024 talk shows 32MB of L3 for an 8-core complex (AMD, vendor).

Across vendors and generations the pattern holds. Each level out is larger and slower (derived), and the L1 stays at 4 to 6 cycles. The size steps run from about 4 to 32 times. L1 to L2 is 8 times on Sandy Bridge (32KB to 256KB) and 32 times on Skylake server (32KB to 1MB). L2 to L3 on Zen 5 is 4 times, counting each core’s 4MB share of the 8-core complex’s 32MB against its 1MB L2. The slowdown per step is 2 to 5 times. In latency, each step is slower by its own factor. L1 to L2 is about 2.3 to 3.5 times, and L2 to the last level is about 2.2 to 2.6 times on Sandy Bridge, 3.3 on Zen 5 and 3.6 to 5 on Skylake server. The Skylake last-level figure is a per-core share of a larger shared cache, so it gives a latency step and no like-for-like capacity step.

How large the last level got

AMD’s EPYC 9005 white paper says one Zen 5 die has 32MB of L3 and a processor holds up to 16 dies, and the 16-core 9175F turns on one core on each, so every core has a whole die’s 32MB of L3 to itself, where the cores of an 8-core die share it at 4MB each (AMD, vendor). That puts 512MB of L3 in one package (derived, 16 dies times 32MB). In that one configuration, a package carries hundreds of megabytes of cache. It is the cell a lecture puts at about 20 times DRAM’s area.

Figure 1.4 stacks the levels for four cores from two vendors, with box widths on a log scale. Where a vendor gives a range or a floor, the box says so. Copper L1 boxes are the ones that stay within a cycle or two of each other across all four.

The cell stopped shrinking

From 45nm to 5nm the SRAM cell got smaller at every node in this list. From one foundry’s published cells, it shrank about 11.5 times from 45nm to 5nm and at N2 is no smaller than at 5nm (derived). The numbers come first, then what the industry did about it.

One foundry’s cell, seven processes

TSMC’s high-density cell was 0.242µm² at 45nm (paper abstract, TSMC), 0.07µm² at 16nm (Semiconductor Digest, secondary), 0.027µm² at 7nm (a paper title, listed in the IRDS references), and 0.021µm² at 5nm (a paper title, Yeap and colleagues, IEDM 2019). At N3 it was 0.0199µm² (Chang and colleagues, IEDM 2022, abstract), and at N3E 0.021µm², larger than N3’s (SemiWiki, secondary). At N2 it is 0.021µm² again (ISSCC 2025, abstract). That is about 11.5 times smaller from 45nm to 5nm, about 5% smaller at N3 than at 5nm, and no smaller at N2 than at 5nm (derived). Node names are product names and not a feature size, so these cells are in µm² and not F².

Why

Bitcell scaling is slowing because fin pitch and gate pitch are slowing (IRDS, roadmap). IEEE Spectrum says the six-transistor cellAn SRAM cell is two cross-coupled inverters and two access transistors, six transistors in all. It takes more silicon area per bit than any other memory in the hierarchy. has not shrunk as fast as logic for several generations (Spectrum, secondary). Sizing rules from the first section still apply at every node. The pull-down must stay stronger than the access transistor, and the pull-up to access ratio must stay below about 1.8 (lecture, UCSB).

Density from the edges of the array

If the cell is flat, density can still come from around it. TSMC’s N2 SRAM reaches 38.1Mb/mm², 1.1 times the previous node, through design-technology co-optimization around the same 0.021µm² cell (paper abstract), and its N2 platform paper gives about 38Mb/mm² for the macro, with more than 1.15 times chip density over N3 (TSMC, paper abstract). Per Spectrum, the steps are 6% at N3 and 11% at N2 (secondary). Spectrum calls 38Mb/mm² a cell, and TSMC calls it a macro, so this guide uses TSMC’s word.

On paper, the next shrink

TSMC says its next node’s SRAM cell will shrink again. In its IEDM 2026 paper on the A14 platform, TSMC claims the smallest SRAM reported, with a cell under 0.017µm² (program abstract), which would be smaller than the N2 cell above. It is a maker’s claim, and TSMC puts A14 on track for volume production in 2028 (program abstract).

imec’s design studies show where the cell could go, and they are not products. An A10 outer-wall forksheet cell is 22% smaller than an A14 nanosheet cell (imec, research study). An A7 double-row CFET cell is more than 40% smaller than one built in A14 nanosheet technology (imec, research study). IRDS also names CFET as the opportunity to reduce SRAM area significantly (roadmap).

Moving cache to another die

IRDS says the slowdown in SRAM scaling brings the last-level cacheThe last-level cache is the outermost cache level, shared by all the cores in a processor. A request that misses it goes out to main memory. off the logic die and onto a stacked die on top of it, and that stacked SRAM is likely to become a mainstream alternative to fully integrated SRAM or eDRAM cache (roadmap). AMD’s 3D V-Cache adds a stacked cache die to an L3 that stays on the logic die. A cache die hybrid-bonded onto a Zen 3 die expands its L3 from 32MB to 96MB, with up to 2TB/s of bandwidth and a 15% average gaming uplift by AMD’s own measurement (Wuu and colleagues, ISSCC 2022, abstract). In the 2026 review, the stacked die is SRAM (secondary), so the second die is the same memory as the L3 below it, not HBM and not eDRAM.

Figure 1.5 plots the seven points on a log axis. Filled points are abstracts that state the area, hollow points are titles or trade press. From 45nm to 5nm the fall is steep, and from 5nm to N2 the line is flat at 0.021µm².

Where the cache sits

Whether another memory can take the cache’s place is still open. The IRDS Beyond CMOS roadmap, which Beyond NAND, Part 3 also cites, puts SOT-MRAM for cache-level use at a rather early stage of research (roadmap), and that part explains the device. The caches on the processors cited here are SRAM, and IRDS names eDRAM as the other on-chip option it weighs stacked SRAM against (roadmap).

Nagare Labs designs its Z2RAM as memory stacked on an AI accelerator, not as a processor cache, and claims more bit density than SRAM. Each bit sits in two transistors and a shield, with no capacitor, and the oxide-semiconductor cells are deposited in layers on one die that is joined directly to the accelerator (Nagare Labs, vendor). Nagare Labs projects that its six-layer first generation will reach 5 times the bit density of 2nm high-density SRAM, a figure taken from layout simulation (vendor, projection). Two transistors and no capacitor make it a 2T0C cell, the capacitorless design that Working Memory, Part 3 follows for DRAM.

The L1, L2 and L3 entries on a spec sheet now read as a capacity and a cycle count for the six-transistor SRAM cell. DRAM is the memory one tier down, and Part 2 opens its 6F² cell, which is read by sharing charge and kept by refresh.

Figure 1.6 is the memory map’s hierarchy with the cache highlighted. It says cycles for the cache and leaves nanoseconds to the memories below.