Standards & Interfaces
Which limits the standards set for every later layer, and why to measure sustained speed, thermals and the negotiated link instead of the burst number.
Start here: no earlier part needed
Technical guide
Flash Foundations
A working map from datasheet claims to NAND behavior, firmware choices, and the operational consequences of both.
Ten chapters connecting NAND physics to storage behavior. Read in order, or choose the layer you need.
The whole series
How the ten parts connect
Each part after the first rests on concepts that an earlier part teaches once, in full. Knowing the links tells you what to read first for the question you have.
How the ten parts connect
Parts 2 and 3 carry the heaviest links to later parts.
Arc thickness is the number of shared concepts.
Physics and the cell hierarchy carry the heaviest links. Charge, voltage windows and wear sit under the cell hierarchy, garbage collection and error correction, and pages, blocks and dies decide what the controller, the translation layer, garbage collection and error correction can do. The standards in Part 1 are the outer envelope, which is why they reach the controller, the performance numbers and the roadmap.
Chapters 01–03
The foundation
The standards, charge physics, and cell organization that define what every SSD can and cannot do.
The Physics of Flash
Why every extra bit per cell shrinks the voltage margin, and how wear shows up as a rising raw bit error rate.
Builds on Part 1
From Cell to Die
What a read, a program and an erase can touch, and why a page that cannot be overwritten in place makes garbage collection necessary.
Builds on Part 2
Chapters 04–07
How a drive behaves
Where density meets controller design, firmware translation, garbage collection, and the realities of wear.
3D NAND Stacking
Why stacking changed the scale of the hierarchy and not its rules, and why die density says more than layer count.
Builds on Part 2
The Controller
Which controller resources set the NAND-side ceiling, and where to look first when tail latency or the first I/O after idle misbehaves.
The Flash Translation Layer
How one logical-to-physical map turns write-once flash into rewritable storage, and why firmware maturity is a purchasing criterion.
Builds on Part 3
Garbage Collection & Wear
What every garbage-collection copy costs, and how write amplification explains the gap between a spec sheet and the field.
Chapters 08–10
Reliability and what follows
Error correction, endurance tradeoffs, and the technologies reshaping how flash is used next.
Error Correction & Integrity
How error correction (ECC) bridges the raw error rate and the uncorrectable rate, and what the spent headroom looks like as a drive ages.
Performance & Endurance
How to read a spec-sheet number as a set of conditions: one workload, one fill level, day one.
Builds on Part 1
The Future of Flash
Which directions are production-ready for a purchase today and which still belong on the watch list.
Explore the layers
One system,
many perspectives
Open a layer to see where it fits.
01Cell+
It starts with charge
A NAND cell stores information as an electrical state. Distinguishing those states is the foundation of reading flash.
Read the chapter →02Die+
Small cells, larger structures
Cells are organized into pages and blocks on a die. That organization shapes how data can be read, programmed, and erased.
Read the chapter →03Controller+
Making flash work as a drive
The controller and its firmware manage address translation, error correction, and the work of moving data to and from NAND.
Read the chapter →04Host+
Where the system meets storage
The host communicates with the drive through a storage protocol and interface. Those choices shape how commands and data travel.
Read the chapter →Continue on this site