Beyond NAND, Part 2: Phase-Change Memory and Optane

The memory map ended on a measured fact. A drive built on Intel and Micron’s 3D XPoint answered a small read far faster than a NAND drive, and it was discontinued anyway. This part is the account behind that sentence. A reader who finishes it can read an Optane specification line and say what the material does, explain why a phase-change cell is fast but sensitive to heat and why that decided where it shipped, say who built it, and say what ended and what did not.

Several subjects are left to other pages. Cost per bit, and why NAND is cheap, is in the memory map, and Part 1 keeps NOR and why embedded flash stopped fitting. MRAM in microcontrollers is in Part 3. Phase-change devices used as analog weights are in the synapse guide. Why none of these memories replaced DRAM is in the memory map and Part 8 of that series. CXL itself is in Flash Foundations Part 10, and the SLC flash cell is in Flash Foundations Part 2. Beyond NAND’s series page lists the rest, and Part 3 is the next family.

The gap between DRAM and NAND

Numbers here carry one of ten tags. A paper value is a published measurement from a peer-reviewed or conference paper. A research study value is a simulation or model result. A vendor value is a company’s own release, brief, letter, datasheet or specification page, and the company is named in the sentence. A filing value comes from a document filed with the U.S. Securities and Exchange Commission. A roadmap value comes from the IRDS roadmap. A lecture value comes from conference or consortium slides. A secondary value comes from a trade report, a teardown or a review that repeats someone else’s figure, and the outlet is named in the sentence. A vendor claim is a vendor value that the company states as its own comparison or plan, with no test described. An own measurement is a result from my own bench, with the method stated. Derived means arithmetic on numbers already given, shown in the text. Only the two dollar figures from the filings are printed, and no prices or market shares appear. Bandwidth is in GB/s.

Phase-change memoryPhase-change memory stores data in a material that switches between a crystalline, low-resistance state and an amorphous, high-resistance state when heated. was wanted for a place that flash and DRAM both leave empty. That place is a memory slower than DRAM, much faster than a NAND drive, and nonvolatile. Numbers for that place sit in one spot here, so the rest of the part can point back to them.

What sat between DRAM and flash

Burr and colleagues described roughly 100ns to 1ms of access time between DRAM and flash, with nothing in it (Burr et al., paper). The memory map draws the whole hierarchy. Only the memories the figure needs are used here.

What each number measures

Intel’s specification page puts a typical read of 5µs on the Optane P5800X (Intel, vendor). In Intel’s own evaluation, the older P4800X averaged 12µs or less for a 4KiB random read at queue depthIOPS counts commands finished per second. Queue depth is how many commands are outstanding at once, and a drive needs a deeper queue to reach its top IOPS. 1 (Intel evaluation guide, vendor). Micron’s specification page puts a typical 4KiB read of 80µs at queue depth 1 for its 7450, a TLC data-center SSD (Micron, vendor). Five microseconds against 80 is 16 times lower read latency (derived). Both are vendor ratings, from different drive classes, so the ratio shows the size of the difference and is not a test of the two drives against each other.

On my own bench, 4KiB reads at queue depth 1, median of four CrystalDiskMark 8.0.4 runs, took 12.9µs on an Intel Optane 905P, 10.2µs on an Intel Optane P5800X and 56.9µs on a Samsung 980 NAND drive (own measurement).

Figure 2.1 puts these memories on one logarithmic axis, from DRAM at the top to the NAND drive at the bottom. Optane DIMM latency sits a few times above DRAM, the two Optane SSDs sit in single-digit and low double-digit microseconds, and the TLC drive sits more than six times beyond the slower of them (derived: 80 divided by 12). DRAM and DIMM bars come from a measurement paper described in the fifth section, and the drive bars are ratings. Mixing the two is deliberate. The figure shows where the product sat in the hierarchy. A head-to-head test would use one method on both.

What Optane was sold on

Endurance was the other half of the pitch. Intel rates the P5800X at 100 drive writes per dayDrive writes per day is the number of times the full capacity can be written each day for the warranty period, which equals TBW divided by capacity and days. (Intel, vendor), and the 375GB P4800X at 30 drive writes per day, which is 20.5PBW (Intel, vendor). Micron rates the 7450 PRO at up to 28,000TB written at 1 drive write per day, and the 7450 MAX at up to 70,000TB at 3 (Micron, vendor). Against 1 to 3, a rating of 100 is 33 to 100 times higher (derived).

Intel and Micron’s 2015 announcement went further. Intel and Micron’s release claimed that 3D XPoint is up to 1,000 times faster than NAND, has up to 1,000 times the endurance, and is 10 times denser than conventional memory (vendor). Intel and Micron state those multipliers themselves, and the release gives no latency figure in nanoseconds or microseconds.

How a phase-change cell stores a bit

A phase-change cell holds a bit in the structure of a small piece of material. Trapped charge is how flash holds one. Papers supply the mechanism, because the limits, the products and the selector in later sections all point back to it.

Two structural states

Storage uses a chalcogenide, a glassy alloy that can sit in two structural states. Amorphous is high resistance and crystalline is low resistance. SET means the low-resistance stateThe low-resistance state is the resistive cell state that passes current easily, and it usually stores a one. and RESET the high (Wong et al., paper). In Burr’s review the crystalline phase has a resistivity that is sometimes 3 or 4 orders of magnitude lower than the amorphous phase (paper). Wong and colleagues say the difference can reach five orders in some materials but is typically two in real devices, because the set-state resistance includes contact and heater resistance, and melt-quenched material is less resistive than as-deposited amorphous material (paper).

SET, RESET and read

To RESET the cell, the programming region is melted and then quenched fast with a large, short current pulse. That leaves a region of amorphous material in series with whatever stays crystalline. To SET it, a medium pulse anneals the region at a temperature between the crystallization temperature and the melting temperature, long enough for it to crystallize. A read passes a current too small to disturb the state (Wong et al., paper).

Threshold switching

RESET has a problem. Amorphous material is too resistive to carry the current that would heat it. Wong and colleagues explain how it gets past that: when the electric field across the amorphous region reaches a threshold, its resistance collapses to a value comparable to the crystalline state, and SET can go ahead. Threshold switching is reversible if the pulse is removed quickly, and it is essential to SET programming (paper). Remember it. Used as a switch in series with the memory element, the same effect is the selector in the fifth section.

Where it came from

Burr and colleagues say electrical phase change in chalcogenides was demonstrated as long ago as the 1960s, and Wong and colleagues say phase-change memory was described in that decade too (paper). Its first commercial success was not memory. Alloys on the GeTe-Sb₂Te₃ line showed large optical contrast and switched rapidly between amorphous and crystalline phases under laser pulses, which gave rewritable optical discs (Wong et al., paper). Early electrical materials crystallized too slowly to compete, in microseconds to milliseconds. Materials able to recrystallize in nanoseconds arrived in the late 1980s (Burr et al., paper).

How fast

Sub-10ns SET pulses and a 400ps amorphization have been shown, as single-device lab results (Burr et al., paper). A 2012 report in Science covers a lab device that crystallized in 500ps, helped by holding a constant low voltage so the material is partly ordered before the write pulse arrives. That report’s abstract is the source (paper, abstract). Cell read time in that review is 1ns to 10ns (Burr et al., paper). A whole chip takes longer, which the fifth section shows.

Figure 2.2 is a schematic and is not to scale. Left of the figure, one cell is shown with the programmed region crystalline and then amorphous. Right of the figure, the two pulses that make those states are drawn. RESET’s pulse is tall and short. It crosses the melting line and stops fast enough to freeze the melt. SET’s pulse is lower and longer, staying between the crystallization line and the melting line. Shape is the cost: the tall pulse needs current and the long one needs time.

Heat, drift and wear

Phase-change memory has three limits that follow directly from the mechanism. Phase-change memory is far tougher than flash, it creeps in resistance over time, and its retention depends on temperature. Each limit below has its numbers, so that the end of Optane is not mistaken for a physical failure, and so that the car story in the next section makes sense.

Endurance

Burr’s review reports a best single-device endurance of 10¹² SET-RESET cycles, for the lowest-energy RESET pulses, shown as early as 2001. Larger arrays tended to show 10⁸ to 10¹⁰ cycles. Flash is typically 10⁴ to 10⁵ program-erase cycles, limited by stress-induced leakage current (paper). Lee, Ipek, Mutlu and Burger asked what PCM would cost as main memory in a simulation. A baseline PCM system was 1.6 times slower and needed 2.2 times the energy of a DRAM system. Buffering narrowed those to 1.2 times and 1.0 times, and partial writes gave a 5.6-year lifetime (ISCA 2009, research study).

How cells fail

Burr’s review names two failure modes after cycling. In stuck-SET a cell slowly loses its resistance contrast. In stuck-RESET its resistance suddenly jumps to a blown-fuse state, higher than the RESET state. Burr’s review also finds that every tenfold increase in pulse energy goes with about three orders of magnitude less endurance (paper). Neighbors are a second worry. Burr summarizes a thermal simulation out to the 65nm node. Temperature rise at the cell next to one being RESET stays well under 100°C, so disturb looked like a second-order problem (research study, via Burr’s review).

Drift

After the melt-quench the amorphous phase keeps relaxing, and its resistance rises over time as a power law. Burr’s review puts the drift coefficient at about 0.05 to 0.1 for thin amorphous GST layers (paper). Wong and colleagues call it typically of order 0.1, and note that it depends on temperature (paper). Drift raises the gap between the states, which helps a cell that holds one bit. Drift is a major concern when a cell must hold several bits in resistance levels that move (Wong et al., paper). The synapse guide takes that up where phase-change devices store analog weights.

Heat and retention

A bit that melts to be written can crystallize back by itself, so retention is a heat question. Crystallization temperature has to stay high enough to keep the amorphous phase for ten years at the operating temperature, which Wong and colleagues give as 85°C for embedded memory and even 150°C for automotive use (paper).

Qualification bakes are converted to a lower temperature with the Arrhenius form, where the speedup depends on an activation energy. Burr, citing Kim and colleagues on 64Mb PCM chips, reports 2.1eV for fully processed cells and 2.46eV for as-deposited films (paper). Flash is taken here at 1.1eV as a teaching value. A bake of 1,000 hours at 125°C then stands for about 20 years at 70°C at 1.1eV, about 2,000 years at 2.1eV, and about 11,000 years at 2.46eV (derived from the Arrhenius form with those energies). One bake at 1,000 hours cannot stand in for both activation energies.

Figure 2.3 has two panels. Endurance sits on a logarithmic axis at left, with flash at the bottom, arrays of PCM several orders above it, and the best single device higher still. Bake arithmetic is three bars at right, with one bar for each activation energy, so the same 1,000 hours reads as decades, millennia or tens of millennia. Together they say what phase-change memory is good at, which is cycling, and why one bake condition cannot qualify both memories.

Phase-change memory in phones and cars

Phase-change memory shipped before Optane, and ST was still announcing it after Optane ended. Who built it, what the first parts were, and why heat decides where it ends up are set out below.

Who built it

Company release copies, two filings and trade reports supply the histories below, and peer-reviewed papers are absent from that set, with each sentence naming its source.

Intel and Ovonyx are the earliest dated line here. EE Times reported in July 2001 that Intel’s Stefan Lai described Ovonyx unified memory, a chalcogenide film on a CMOS wafer. It had worked in single cells and in a 4Mb test chip, with read and write times of 100ns, according to the report (secondary). The Register reported that Intel highlighted a paper Gordon Moore co-authored more than thirty years earlier on amorphous semiconductors (secondary).

IBM, Infineon and Macronix started a joint program next. A copy of the announcement on Semiconductor Digest, dated May 24, 2005, says the work would run at IBM’s Watson and Almaden labs with about 20 to 25 people from the three companies (secondary). By September 2006 EE Times called it the IBM/Qimonda/Macronix PCRAM Joint Project, Qimonda having inherited Infineon’s place, and described an IEDM abstract with a doped germanium antimonide cell and a reset current under 100µA (secondary). A relay of IBM’s December 2006 release says IBM said its prototype measured 3nm by 20nm, was 500 times faster than flash and used half the power (secondary). IBM stated those figures, relayed by a trade site. Ovonyx and Qimonda signed a cross license for phase-change patents on January 16, 2007, according to a copy of their release (vendor). In January 2008, Semiconductor Digest reported that Qimonda and Macronix signed a five-year deal to develop nonvolatile memory together (secondary). Infineon appears in this account only as the first partner and as Qimonda’s parent.

Samsung worked on its own line. In September 2006 it said it had a working 512Mb prototype. Samsung’s release, as reprinted by phys.org, describes vertical diodes on a DRAM-style three-dimensional transistor structure and a 0.0467µm² cell. It claimed the part was effectively 30 times faster than flash and was expected to last at least 10 times longer, and expected it to be available from 2008 (vendor). The Register reported on September 23, 2009 that Samsung was starting production of a 512Mb part on a 60nm-class process, and that rival Numonyx then had a 128Mb part on 90nm and had taped out a 1Gb die on 45nm (secondary). By April 2010 the same outlet reported Samsung shipping a 512Mb, 60nm PRAM in a multichip package as a NOR replacement for phones (secondary). Samsung’s 2006 release looked to 2008; The Register’s reports put the start of production in 2009 and shipping in 2010.

Numonyx is the line that ends at Micron. Intel’s release of March 31, 2008 says Numonyx was created by Intel, STMicroelectronics and Francisco Partners to make NOR and NAND flashNAND flash is the memory that keeps data with the power off. Writing it is much slower than writing DRAM, and it must be erased before it is rewritten.. Intel transferred its NOR business and certain phase-change assets for 45.1%, STMicroelectronics took 48.6% and Francisco Partners 6.3% (vendor). ST’s own Form 6-K says its contribution included its phase-change memory resources (filing). Micron’s release of May 7, 2010 says it completed the acquisition of Numonyx and issued about 138 million shares to Intel, STMicroelectronics and Francisco Partners (filing). Filings give that ownership record. The record does not say which company designed the Micron parts below.

The first parts

Micron’s P8P was a 128Mb parallel PCM made on a 90nm process. Its datasheet rates it at a minimum of 1,000,000 writes per 32-byte page and 10 years of retention at 70°C, with a 115ns initial read and no erase step (vendor). A 45nm generation followed at IEDM 2009, and a 45nm 1Gb chip at ISSCC 2010; both are paper titles only (paper, title only). In July 2012 Micron’s release announced high-volume availability of a 45nm 1Gb PCM stacked with 512Mb of LPDDR2 in a multichip package for mobile devices (vendor).

Why a car

An engine bay is hot, and the amorphous state crystallizes faster as it warms, as the last section showed. Amorphous phase-change material has to hold for ten years at 85°C for embedded memory and at 150°C for automotive (Wong et al., paper). STMicroelectronics said it was sampling 28nm FD-SOI microcontrollers with embedded phase-change memory, which it called ePCM, to alpha customers. It described them as the first to use ePCM, rated AEC-Q100 Grade 0 at up to +165°C, with firmware retention through high-temperature soldering reflow (SEMI’s account of ST’s release, secondary; the page carries no date). SEMI’s page cites an IEDM 2018 paper whose title says it embeds 16MB of phase-change memory (paper, title only). EE Journal repeats the 165°C rating and says the heater in the cell is a buried bipolar transistor (secondary).

What PCM gives a microcontroller

ST’s Stellar release of October 20, 2020 says its embedded PCM allows single-bit alterability at run time without an erase, and over-the-air updates with no downtime, to AEC-Q100 Grade 0 at up to +165°C (vendor). SR6 parts announced on June 16, 2021 have up to 20MB of PCM and a dual-image mode that holds two 20MB images for updates. ST’s comparison is that PCM access is faster than 1T NOR flash (vendor claim).

Soldering is one requirement behind the reflow claim. A microcontroller is soldered to its board and its code must come out intact. IRDS 2022 says NOR flash survives board soldering at about 250°C (IRDS 2022, roadmap). Part 1 keeps the longer account, and Part 3 covers what MRAM does in the same place.

What ST announced since

On March 19, 2024 ST announced an 18nm FD-SOI process with ePCM, co-developed with Samsung Foundry. Against its 40nm embedded nonvolatile memory, ST claims more than 50% better performance-to-power ratio and 2.5 times the NVM density. First samples were planned for the second half of 2024 and production for the second half of 2025 (vendor claim). The schedule is ST’s plan, and that release left delivery unconfirmed. On April 16, 2025 ST announced Stellar with xMemory, an extensible memory based on its proprietary PCM, with production planned later that year (vendor).

Figure 2.4 has two panels. A temperature ladder at the top marks the 70°C retention rating of the P8P, the 85°C and 150°C targets for embedded and automotive memory, the +165°C Grade 0 rating of ST’s PCM, and the 250°C solder test. A dated strip below it shows who built it, with one row for each line of work described above and only the dates drawn. Both panels answer one question from two sides: where PCM can live, and who got it there.

3D XPoint and Optane

Intel and Micron’s 3D XPoint is the best-known product that a teardown and the IRDS roadmap place in the phase-change family, and the least documented. What the companies disclosed comes first, then what other sources fill in, what the products were, and how they measured, and the evidence tags stay apart.

What the companies said

Intel and Micron’s 2015 release describes a transistor-less cross point architecture. A memory cell sits at the crossing of each word line and bit line, and each cell is individually addressable. Cells are built from “unique material compounds,” and the release does not name them. Sampling was planned for later that year (vendor). Intel’s later evaluation guide says the media does not store data by trapping electrons as NAND does, and instead stores it by a change in a property of the material (vendor). IRDS 2023 calls it a form of phase-change memory, though the companies called it a resistive memory (IRDS 2023, roadmap).

What fills it in

Intel and Numonyx’s 2009 paper, A stackable cross point Phase Change Memory, shows a PCM cell with an ovonic threshold switchAn ovonic threshold switch is a chalcogenide layer that conducts only above a threshold voltage, used as the selector in phase-change crosspoint memory. as the selector, with a 9ns reset and 10⁶ cycles (paper, abstract). This is not a claim about 3D XPoint. The paper shows the memory-plus-selector arrangement in the literature six years before the 2015 release. Threshold switching from the second section is that switch, used in series with the memory element. TechInsights took an Optane die apart and reported a chalcogenide phase-change element with a separate arsenic-doped chalcogenide as the selector in a double-stacked structure (secondary). Its second-generation analysis found a four-layer stack on a 256Gb die in the P5800X, against two layers and 128Gb in the first generation. It also reports the first generation used 20nm double patterning for the bit lines and word lines (secondary). Neither company confirmed any of this. TechInsights’ layer count stands as an independent teardown finding.

Figure 2.5 is a schematic of the cell as the teardowns describe it, and the label says it is not company-confirmed. Each crossing holds a memory element and a selector in series. Two layers at left make the first generation at 128Gb, and four layers at right make the second generation at 256Gb. Look at the selector. It lets a cell with no transistor be read without disturbing its neighbors, using the threshold effect from the second section. Part 5 covers why a crossbar needs one.

The products

Optane SSD DC P4800X for the data center reached customers in 2017 (Intel, vendor). Intel’s April 2019 brief describes persistent memory modules fitting DDR4 slots in 128GiB, 256GiB and 512GiB sizes (Intel brief, vendor). They ran in two modes. In Memory Mode, the system used the module as large volatile memory with DRAM acting as a cache. In App Direct Mode, software addressed it as persistent memory (vendor). Intel claimed the 200 series gave 32% more memory bandwidth on average than the first generation and up to 6TB of total memory per socket (Intel brief, vendor claim).

How the module measured

Izraelevitz and colleagues measured the first module. Random loads took an average of 305ns against 81ns for DRAM on the same platform, and sequential loads averaged 169ns (Izraelevitz et al., paper). 305 divided by 81 is about 3.8 times DRAM’s random-load latency (derived).

Yang and colleagues measured a different platform with a different method, in a FAST 2020 paper. They found read latency 2 to 3 times that of DRAM, and a gap between random and sequential reads of 80% for the Optane module against 20% for DRAM (paper). Tests differ, so the two ratios differ. This guide gives each with its source and does not average them.

Yang and colleagues also explain why small writes are expensive. Media on the module is accessed in 256-byte units, so smaller stores become read-modify-write operations and cause write amplification. A write-combining buffer of about 16KB merges adjacent writes (paper). One module reached 6.6GB/s read and 2.3GB/s write at best, which is a read-to-write ratio of 2.9 against 1.3 for DRAM. Six interleaved modules raised peak read and write bandwidth by 5.8 times and 5.6 times (paper).

Why Optane ended, and what came after

Optane ended in two steps, a year and a half apart, and each company left a short written record. Records follow in order, then what they pointed at.

Micron, March 2021

On March 16, 2021 Micron said it would cease development of 3D XPoint with immediate effect. It said it had determined there was insufficient market validation to justify the high level of investment needed to commercialize it at scale, was in discussions to sell its Lehi, Utah fab, and would increase investment in products that use CXL (Micron, filing). Its fiscal second-quarter results record a $49 million 3D XPoint inventory write-down, and classify the Lehi property, plant and equipment as held for sale (Micron, filing). Both figures are accounting entries, and neither one is an Optane selling price.

Intel, July 2022

Intel’s 10-Q for the quarter ended July 2, 2022 says Intel initiated the wind-down of its Optane memory business in that quarter. Optane was not aligned to its strategic priorities, Intel continues to embrace the CXL standard, and the filing records a $559 million inventory impairment (filing). Intel’s letter to customers of March 21, 2023 says Intel announced in July 2022 the end of future development of Optane. Existing products would be supported and warranted, media inventory should sustain shipments through 2025, support resources are in place through 2030, and Intel sees CXL as the standard of future tiered-memory solutions (vendor). Intel’s support table lists the Optane SSD DC P5800X as end of life on March 22, 2024, with interactive support ending on December 31, 2025 (vendor).

What neither said

Neither company gave a detailed reason beyond those statements. Hutchby’s 2024 review calls Optane’s performance excellent. Economies of scale stayed out of reach, and Intel discontinued it in 2022 (Hutchby, secondary). IRDS 2023 adds that the Lehi fab was sold and that Micron never made 3D XPoint products in significant volume (roadmap).

The memory map says Optane was faster and tougher than NAND, in a market that did not pay the difference at the volume needed to keep the fab running. That reading of this site is set out there with the cost-per-bit argument behind it.

What it pointed at: CXL

Both companies pointed at CXL. CXL is an interface. The cell underneath stays whatever the module uses. CXL is built on PCIePCI Express is the serial link between an SSD and the host, built from one or more lanes. Each generation roughly doubles the rate per lane. infrastructure. Its 1.0 specification was released in March 2019, 2.0 in November 2020 and 3.0 in August 2022 (CXL Consortium slides at SNIA, lecture). A Type 3 device supports only CXL.ioCXL carries three protocols on one link: CXL.io for device control, CXL.cache for coherent caching by a device, and CXL.mem for host access to device memory. and CXL.mem and is aimed at expanding memory capacity and bandwidth (SMART Modular white paper, vendor).

Micron’s CZ120 is an example of what followed. CZ120 is a CXL 2.0 Type 3 module in 128GB and 256GB capacities, in the E3.S 2T form factor on a PCIe Gen5 x8 interface, with up to 36GB/s of read and write bandwidth, built on Micron’s high-volume DRAM process, with up to 2TB of incremental memory per CPU (StorageReview’s copy of the release, vendor). Micron claims servers with it see up to 96% more database queries per day and 24% more memory read and write bandwidth per CPU than servers with RDIMM memory alone, in a test it does not describe (vendor claim). CXL gave a way to add DRAM capacity. Where memory goes next takes up why that does not fill DRAM’s job. Flash Foundations Part 10 covers the link itself.

Low-latency NAND

Keeping NAND and changing its job was the other answer to the same gap. Samsung’s SZ985 Z-NAND SSD brief, which carries no date, lists an 800GB drive on PCIe Gen3 x4 with sustained random read latency of 12 to 20µs, typical write latency of 16µs, and 30 drive writes per day, built on the V-NAND structure. Samsung claims 5.5 times lower latency than leading NVMe SSDs (vendor). Read latency of 12 to 20µs is a range, and the brief gives no single typical read figure. Kioxia’s XL-FLASH comes as a 128Gb SLC die or a 256Gb MLC die, with a 4KB page, 16 planes and a read latency under 5µs, by Kioxia’s own figures (vendor). Flash Foundations Part 2 explains the SLC cell, the die timeline records the dies, and high bandwidth flash uses XL-FLASH’s plane count. Storage-Next covers the SSDs Kioxia builds on XL-FLASH for GPU-initiated reads.

Figure 2.6 puts the dated events on one axis. Optane events sit above the line, beginning with the 2009 paper, then the 2015 release, the 2017 drive and the 2019 modules, then the exit markers in 2021 and 2022, with the 2024 end of life. Three CXL releases sit below the line. Order is all the figure shows. CXL 1.0 came two years before Micron stopped, and Intel’s wind-down came in the same year as CXL 3.0. Filing statements link the two timelines. Dates alone leave Intel’s and Micron’s CXL remarks unconnected.

Optane ended as a product: Micron stopped in March 2021 and Intel wound down in 2022. Phase-change memory as a cell continued, and ST still describes it in its automotive microcontrollers. Part 3 takes the next family, MRAM.