Flash Foundations companion · Lab
Parallelism Lab
An SSD is fast because it writes to many dies at once. Pick a real NAND die, a real controller and a capacity, and see which limit sets the write speed.
Try this: Scroll through the five presets, from one die to a mismatched controller and die, and watch which of the three bars is lowest.
One idea
The slowest of three limits wins
A drive writes only as fast as its dies, its channel buses and its PCIe link allow. Each picture below shows one channel over time and the three limits as bars, and the lowest bar sets the speed.
The walkthrough
Five presets of one picture
Each preset is set up on load. Thin bars show where the change started.
1 One die
A die takes a page over the bus, then spends its program time on it, so the bus sits idle. The dies bar is the lowest, so it sets the speed.
2 More planes
Each plane programs its own page at the same moment, so more planes write more in one program time. At sixteen planes the die outruns its bus, and the bus bar becomes the lowest.
3 More dies per channel
While one die programs, the bus feeds another, so dies add up until the bus is full. After that, more dies add nothing.
4 More capacity
A bigger drive is more dies, not a bigger die, and the controller spreads writes across them until the PCIe link is the lowest bar.
5 Controller and die mismatch
A faster controller lifts the bus bar, but an older die behind it still sets the speed. The controller and the die have to match.
Sandbox
Try any pair
Choose a die, a controller and a capacity, and switch between writing and reading. The dies come from published papers and the controllers from vendor product briefs.
More settings
What you now know
- Write speed is the lowest of three limits: the dies' combined programming speed, the channels times the bus speed, and the PCIe link.
- More dies help only until a channel or the link becomes the limit; after that extra dies add no speed.
- In read mode the first limit becomes planes x page size / tR, so the same drive reads at a different limit than it writes.
- The numbers are upper bounds from published papers. A real drive is slower.
How it works
One die programs at the speed its paper prints. Where a paper prints only tPROG, the lab uses planes x page size / tPROG. The dies for a capacity are the capacity divided by the die size, rounded up. They spread across the controller's channels, and each channel can address a fixed number of dies.
The three limits are the dies' combined programming speed, the channels times the bus speed, and the PCIe link. The bus runs at the slower of the die and the controller, one byte per transfer. The write speed is the lowest of the three, and that bar is the one marked "Sets the speed". The gauge uses a fixed log scale, so a bar moves only when its number changes. The timeline runs one channel through a small schedule: the dies share the bus, and each die can take the next page while it programs. In the sandbox its time axis follows the die's program time.
In read mode the sandbox swaps the first limit: a die returns a page from every plane each tR, so it reads at planes x page size / tR, using the tR its paper prints. Only dies whose paper prints both a page size and a tR can be read. The bus and the PCIe link are the same limits as for writes. Reads leave out the cache-read pipeline, so a real read is slower than the lab says.
More settings holds the rest. Commands in flight limits how many dies are working: with a few commands outstanding and no write cache to absorb them, each lands on a die at random, so some dies sit idle and some commands wait behind another. PCIe link swaps in another generation and lane count. Generation 6 is 64GT/s, 8GB/s a lane before framing, from the PCI-SIG announcement of the specification; the lab does not take out its flit overhead. Packet framing takes a share off the link: a packet adds about 20 bytes around its payload, so a 256-byte payload is about 93% of the link and a 128-byte payload about 86%. That figure comes from a white paper on older PCIe generations, so it is a teaching value for the newer ones.
Cache register off models a die that cannot load its next page while the last one programs. The classic asynchronous SLC die is a real one: a 2Gb part with a 2KB page, a tPROG of 220µs and 25ns per byte on the bus. Without a cache register a page takes 220µs plus 51µs of transfer, which is the 7.5MB/s the manufacturer's technical note prints. The 16-channel and 32-channel controllers are what-if geometries, not products: only the 16-channel part's channel count and PCIe generation come from a vendor announcement.
Terms
- Die
- One piece of silicon holding NAND flash. An SSD carries many dies, each able to work on its own.
- Plane
- A section of a die with its own page buffer. Planes of one die can program a page each at the same moment.
- Page
- The smallest unit a die programs in one operation, usually 16KB per plane on the dies in this lab.
- tPROG
- tPROG is the time a die takes to program a page. The die is busy for that long and cannot take another page into its array.
- Channel
- A bus between the controller and a group of dies. The dies on one channel share its wires, so only one moves data at a time.
- Cache register
- The die has a one-page cache register, so the next page can travel over the bus while the last one programs.
- MT/s
- Megatransfers per second. On an eight-bit NAND bus one transfer is one byte, so 1,200MT/s moves 1,200MB/s.
- PCIe link
- The link between the SSD and the host. A PCIe 3.0 x4 link carries about 3.9GB/s at best, a PCIe 4.0 x4 link about 7.9GB/s.
What it leaves out
- These are upper bounds. A real drive writes slower than the lab says.
- It leaves out command and address overhead, the decode time inside a plain read, garbage collection, the SLC cache, thermal throttling and the drive's DRAM.
- The page leaves out the host command queue, read-retry and ECC decoding, channel I/O voltage and a tPROG builder. They are in the model but not on this page.
- It uses one die per chip-enable line.
- A die in pseudo-SLC mode writes faster than its native mode. The lab does not model that, because no paper in its sources prints the speed-up.
- A die without a printed page size has its write limits drawn but no timeline, and the read timeline is not drawn at all.
- The sources and method name the paper behind every number.