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    NAND Die Timeline

    Real NAND dies, placed at the date of the earliest paper or announcement cited for each. Choose a measure and see how word-line layers, bit density, interface speed and cell type moved. Every point links to its sources.

    Open the timeline RankingsEvery die and its source
    201520202025400 layers4XX-layer bonded 1Tb TLC with 5.6 Gb/s/pin IO (JSSC 2025, BV-NAND), 10/2025

    Chart of dies by year

    From one planar layer in 2002 to ≥400 layers in 2025

    Bit density climbed from 0.0077Gb/mm2 in 2002 to 37.6Gb/mm2 in 2026

    I/O speed climbed from 333MT/s in 2011 to 4800MT/s in 2025

    From MLC in 2005 to PLC in 2023: more bits in every cell

    Measure
    Makers
    Manufacturer, chart and table

    Counts are per measure: a die with no value for the chosen measure is hidden, so this count can be lower than the 97 in All.

    Word-line layers runs from 24 (2013) to 400 (2025) across 55 dies. The 32 planar dies from 2002 on have one layer of cells, so they sit on the bottom line. Samsung’s 2008 double-stacked test chip, two planar layers on top of each other, is drawn on its own and sets no record: it is not vertical 3D NAND.
    125102050100200500Word-line layers, log scale; planar dies at 12002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026120nm 1Gb planar NAND (Lee et al., JSSC 2002): planar, drawn at 1 layer, 11/2002130nm 1Gb planar NAND (JSSC 2002): planar, drawn at 1 layer, 11/200290nm 2Gb planar NAND (JSSC 2003): planar, drawn at 1 layer, 11/200370nm 8Gb MLC planar NAND (JSSC 2006): planar, drawn at 1 layer, 200556nm 8Gb MLC planar NAND (ISSCC 2006): planar, drawn at 1 layer, 2/200650nm 4Gb (Intel and Micron), sampling: planar, drawn at 1 layer, 7/200670nm 16Gb 4b/cell planar NAND (VLSI 2007): planar, drawn at 1 layer, 200743nm 16Gb MLC planar NAND (ISSCC 2008): planar, drawn at 1 layer, 2/200834nm 32Gb MLC (Intel and Micron), announced: planar, drawn at 1 layer, 5/200850nm 8Gb DDR-interface NAND (Intel and Micron, ISSCC 2008): planar, drawn at 1 layer, 200856nm 16Gb MLC all-bitline NAND (ISSCC 2008): planar, drawn at 1 layer, 200856nm 16Gb TLC planar NAND (Li et al., ISSCC 2008): planar, drawn at 1 layer, 200845nm 4Gb MLC double-stacked NAND, two planar layers (ISSCC 2008): 2, 2008Sub-35nm 32Gb TLC planar NAND (ISSCC 2009): planar, drawn at 1 layer, 2/200948nm 32Gb TLC planar NAND (ISSCC 2009): planar, drawn at 1 layer, 200943nm 64Gb 4b/cell planar NAND (ISSCC 2009): planar, drawn at 1 layer, 200932nm 32Gb MLC planar NAND (Lee et al., ISSCC 2010): planar, drawn at 1 layer, 2/201025nm 64Gb MLC (Intel and Micron), announced: planar, drawn at 1 layer, 2/201034nm 32Gb TLC planar NAND (Intel and Micron, ISSCC 2010): planar, drawn at 1 layer, 2/201032nm 32Gb MLC planar NAND (ISSCC 2010): planar, drawn at 1 layer, 2/201026nm 32Gb MLC planar NAND (ISSCC 2011): planar, drawn at 1 layer, 2/201120nm-class 64Gb TLC planar NAND (ISSCC 2011): planar, drawn at 1 layer, 2/201120nm 64Gb MLC (Intel and Micron), announced: planar, drawn at 1 layer, 4/201124nm 64Gb MLC planar NAND (ISSCC 2011): planar, drawn at 1 layer, 201120nm 128Gb MLC (Intel and Micron), announced: planar, drawn at 1 layer, 12/2011Sub-20nm 64Gb MLC planar NAND (ISSCC 2012): planar, drawn at 1 layer, 201219nm 128Gb TLC planar NAND (ISSCC 2012): planar, drawn at 1 layer, 201219nm 64Gb MLC planar NAND (ISSCC 2012): planar, drawn at 1 layer, 201220nm 128Gb TLC planar NAND (ISSCC 2013) (die size and density from a Toshiba table, secondary source): planar, drawn at 1 layer, 201316nm 64Gb MLC planar NAND (ISSCC 2014): planar, drawn at 1 layer, 201316nm 128Gb MLC, sampling: planar, drawn at 1 layer, 7/20131st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source), mass production: 24, 8/20132nd-gen V-NAND 128Gb TLC (32 WL): 32, 2/201532-layer 256Gb MLC (Micron and Intel) (die area from a teardown, secondary source), announced: 32, 3/201532-layer 384Gb TLC (Micron and Intel) (die area and density from a teardown, secondary source), announced: 32, 3/201515nm 64Gb MLC planar NAND (ISSCC 2015): planar, drawn at 1 layer, 20153rd-gen V-NAND 256Gb TLC (48 WL), mass production: 48, 8/2015BiCS 48-layer 256Gb TLC (Toshiba) (die area and density from a teardown, secondary source), announced: 48, 8/201514nm 128Gb MLC planar NAND (ISSCC 2016 paper 7.5): planar, drawn at 1 layer, 2/20164th-gen V-NAND 512Gb TLC (64 WL): 64, 8/2016BiCS3 512Gb TLC (Toshiba/WD, 64 WL layers): 64, 2/201772-layer 256Gb TLC 3D NAND (density from a teardown, secondary source), announced: 72, 4/2017BiCS 64-layer 768Gb QLC (Toshiba), announced: 64, 6/201764-stacked-WL 1Tb QLC (ISSCC 2018): 64, 2/2018BiCS4 512Gb TLC (Toshiba Memory, 96 WL layers; product interface speed from a review, secondary source): 96, 2/201864-layer 1Tb QLC (Micron and Intel), shipping: 64, 5/20185th-gen V-NAND 256Gb TLC (Toggle DDR 4.0), mass production: ≥90, 7/201896-layer 512Gb TLC 4D NAND (CTF and PUC) (density from a teardown, secondary source), launched: 96, 11/20186th-gen V-NAND 512Gb TLC (product interface speed from a review, secondary source): ≥120, 2/2019ISSCC 2019 512Gb TLC 128 WL layers, CuA, 4-plane: 128, 2/2019128-layer 1Tb TLC 4D NAND, mass production: 128, 6/201964-layer 256Gb TLC (Xtacking) (die area, density and planes from a teardown, secondary source), mass production: 64, 9/2019BiCS4 1.33Tb QLC (96 WL layers): 96, 1/2020BiCS5 112-layer 512Gb TLC (density from a teardown, secondary source), announced: 112, 1/202092-stacked-WL 1Tb QLC (ISSCC 2020 paper 13.1): 92, 2/202096L QLC 1Tb (PUC): 96, 2/202096L FG 1Tb QLC (CuA; product interface speed from a review, secondary source): 96, 5/2020X2-6070 128-layer QLC (Xtacking 2.0): 128, 2020X2-9060 128-layer TLC (Xtacking 2.0; die area, density and planes from a teardown, secondary source): 128, 2020176-layer TLC (capacity, die area and density from a teardown, secondary source), shipping: 176, 11/2020XL-FLASH G1 128Gb SLC (96 WL layers): 96, 1/2021144L FG 1Tb QLC (product interface speed from a review, secondary source): 144, 2/2021ISSCC 2021 1Tb TLC 170+ WL layers, CuA, 4-plane: ≥170, 2/20217th-gen V-NAND 512Gb TLC (CoP; density note cites a teardown, secondary source): 176, 2/2021176L TLC 512Gb (4D PUC; die area from a teardown, secondary source): 176, 2/2021128-layer 512Gb TLC (die B37R; teardown, secondary source): 128, 2021176-layer QLC (replacement gate) (density from a teardown, secondary source), shipping: 176, 1/2022BiCS6 1Tb QLC (162 WL layers, WD/Kioxia): 162, 2/2022176-stacked-WL 1Tb QLC (ISSCC 2022): 176, 2/2022X3-9070 1Tb TLC (Xtacking 3.0; layer count, die area and density from a teardown, secondary source): 232, 2022G8 232-layer TLC, shipping: 232, 7/2022238-layer 512Gb TLC 4D NAND, developed: 238, 8/2022192L FG 1.67Tb 5b/cell (PLC): 192, 2/2023128-layer 512Gb TLC (single deck, die K9AHGD8U0B; teardown, secondary source): 128, 2023300+ layer 1Tb TLC (ISSCC 2023 paper 28.2): ≥300, 2023192L QLC (D5-P5336): 192, 10/2023280-layer 1Tb QLC (ISSCC 2024 paper 13.3): 280, 2/2024BiCS8 218-layer 1Tb TLC (Kioxia/Sandisk, VLSI 2023 and IEDM 2023): 218, 3/2024X4-9060 512Gb TLC (Xtacking 4.0; die area and layer count from a teardown, secondary source): 160, 2024G9 276-layer TLC (Micron 2650), shipping: 276, 7/2024321-layer 1Tb TLC (die area and density from a teardown, secondary source), mass production: 321, 11/2024321-layer 2Tb 4b/cell (ISSCC 2025 paper): 321, 2/2025BiCS10 332-layer 1Tb TLC (previewed at ISSCC 2025), sampling: 332, 20254XX-layer bonded 1Tb TLC with 5.6 Gb/s/pin IO (JSSC 2025, BV-NAND): ≥400, 10/2025BiCS10 332-layer 2Tb QLC 6-plane (ISSCC 2026 paper 15.1, with Sandisk): 332, 2026BiCS9 230-layer 1Tb TLC, sampling: 230, 7/2026V10 375-layer 1Tb TLC, shown at fms: 375, 8/2026G11 400+ layers (volume ramp 2H 2027), announced: ≥400, 10/2026
    Bit density runs from 0.0077Gb/mm2 (2002) to 37.6Gb/mm2 (2026) across 61 dies.
    0.0050.010.050.10.5151050Bit density, Gb per mm2, log scale2002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026120nm 1Gb planar NAND (Lee et al., JSSC 2002): 0.0077Gb/mm2, 11/2002130nm 1Gb planar NAND (JSSC 2002): 0.008Gb/mm2, 11/200290nm 2Gb planar NAND (JSSC 2003): 0.014Gb/mm2, 11/200370nm 8Gb MLC planar NAND (JSSC 2006): 0.055Gb/mm2, 200556nm 8Gb MLC planar NAND (ISSCC 2006): 0.079Gb/mm2, 2/200643nm 16Gb MLC planar NAND (ISSCC 2008): 0.13Gb/mm2, 2/200834nm 32Gb MLC (Intel and Micron), announced: 0.19Gb/mm2, 5/200856nm 16Gb TLC planar NAND (Li et al., ISSCC 2008): 0.11Gb/mm2, 2008Sub-35nm 32Gb TLC planar NAND (ISSCC 2009): 0.28Gb/mm2, 2/200932nm 32Gb MLC planar NAND (ISSCC 2010): 0.2Gb/mm2, 2/201032nm 32Gb MLC planar NAND (Lee et al., ISSCC 2010): 0.22Gb/mm2, 2/201025nm 64Gb MLC (Intel and Micron), announced: 0.38Gb/mm2, 2/201020nm 64Gb MLC (Intel and Micron), announced: 0.54Gb/mm2, 4/201124nm 64Gb MLC planar NAND (ISSCC 2011): 0.42Gb/mm2, 201119nm 64Gb MLC planar NAND (ISSCC 2012): 0.57Gb/mm2, 201219nm 128Gb TLC planar NAND (ISSCC 2012): 0.75Gb/mm2, 201216nm 64Gb MLC planar NAND (ISSCC 2014): 0.69Gb/mm2, 201320nm 128Gb TLC planar NAND (ISSCC 2013) (die size and density from a Toshiba table, secondary source): 0.87Gb/mm2, 20131st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source), mass production: 0.96Gb/mm2, 8/20132nd-gen V-NAND 128Gb TLC (32 WL): 1.86Gb/mm2, 2/201532-layer 384Gb TLC (Micron and Intel) (die area and density from a teardown, secondary source), announced: 2.28Gb/mm2, 3/2015BiCS 48-layer 256Gb TLC (Toshiba) (die area and density from a teardown, secondary source), announced: 2.43Gb/mm2, 8/20153rd-gen V-NAND 256Gb TLC (48 WL), mass production: 2.6Gb/mm2, 8/201514nm 128Gb MLC planar NAND (ISSCC 2016 paper 7.5): 0.98Gb/mm2, 2/2016768Gb 3b/cell 3D floating-gate NAND with CMOS under array (Micron and Intel, ISSCC 2016 paper 7.7): 4.29Gb/mm2, 2/20164th-gen V-NAND 512Gb TLC (64 WL): 3.98Gb/mm2, 8/2016BiCS3 512Gb TLC (Toshiba/WD, 64 WL layers): 3.88Gb/mm2, 2/201772-layer 256Gb TLC 3D NAND (density from a teardown, secondary source), announced: 3.55Gb/mm2, 4/201764-stacked-WL 1Tb QLC (ISSCC 2018): 5.63Gb/mm2, 2/2018BiCS4 512Gb TLC (Toshiba Memory, 96 WL layers; product interface speed from a review, secondary source): 5.95Gb/mm2, 2/201896-layer 512Gb TLC 4D NAND (CTF and PUC) (density from a teardown, secondary source), launched: 6.3Gb/mm2, 11/20186th-gen V-NAND 512Gb TLC (product interface speed from a review, secondary source): 5Gb/mm2, 2/2019ISSCC 2019 512Gb TLC 128 WL layers, CuA, 4-plane: 7.8Gb/mm2, 2/201964-layer 256Gb TLC (Xtacking) (die area, density and planes from a teardown, secondary source), mass production: 4.42Gb/mm2, 9/2019BiCS5 112-layer 512Gb TLC (density from a teardown, secondary source), announced: 7.08Gb/mm2, 1/2020BiCS4 1.33Tb QLC (96 WL layers): 8.5Gb/mm2, 1/202092-stacked-WL 1Tb QLC (ISSCC 2020 paper 13.1): 7.53Gb/mm2, 2/202096L QLC 1Tb (PUC): 8.4Gb/mm2, 2/202096L FG 1Tb QLC (CuA; product interface speed from a review, secondary source): 8.9Gb/mm2, 5/2020X2-9060 128-layer TLC (Xtacking 2.0; die area, density and planes from a teardown, secondary source): 8.47Gb/mm2, 2020176-layer TLC (capacity, die area and density from a teardown, secondary source), shipping: 10.27Gb/mm2, 11/20207th-gen V-NAND 512Gb TLC (CoP; density note cites a teardown, secondary source): 8.5Gb/mm2, 2/2021ISSCC 2021 1Tb TLC 170+ WL layers, CuA, 4-plane: 10.4Gb/mm2, 2/2021176L TLC 512Gb (4D PUC; die area from a teardown, secondary source): 10.8Gb/mm2, 2/2021144L FG 1Tb QLC (product interface speed from a review, secondary source): 13.8Gb/mm2, 2/2021128-layer 512Gb TLC (die B37R; teardown, secondary source): 7.76Gb/mm2, 2021176-layer QLC (replacement gate) (density from a teardown, secondary source), shipping: 14.9Gb/mm2, 1/2022176-stacked-WL 1Tb QLC (ISSCC 2022): 14.8Gb/mm2, 2/2022BiCS6 1Tb QLC (162 WL layers, WD/Kioxia): 15Gb/mm2, 2/2022X3-9070 1Tb TLC (Xtacking 3.0; layer count, die area and density from a teardown, secondary source): 15.03Gb/mm2, 2022G8 232-layer TLC, shipping: 14.6Gb/mm2, 7/2022192L FG 1.67Tb 5b/cell (PLC): 23.3Gb/mm2, 2/2023128-layer 512Gb TLC (single deck, die K9AHGD8U0B; teardown, secondary source): 6.96Gb/mm2, 2023192L QLC (D5-P5336): 18.6Gb/mm2, 10/2023280-layer 1Tb QLC (ISSCC 2024 paper 13.3): 28.5Gb/mm2, 2/2024BiCS8 218-layer 1Tb TLC (Kioxia/Sandisk, VLSI 2023 and IEDM 2023): 18.3Gb/mm2, 3/2024321-layer 1Tb TLC (die area and density from a teardown, secondary source), mass production: 23.52Gb/mm2, 11/2024321-layer 2Tb 4b/cell (ISSCC 2025 paper): 28.8Gb/mm2, 2/2025BiCS10 332-layer 1Tb TLC (previewed at ISSCC 2025), sampling: ≥29Gb/mm2, 20254XX-layer bonded 1Tb TLC with 5.6 Gb/s/pin IO (JSSC 2025, BV-NAND): 28Gb/mm2, 10/2025BiCS10 332-layer 2Tb QLC 6-plane (ISSCC 2026 paper 15.1, with Sandisk): 37.6Gb/mm2, 2026
    I/O speed runs from 333MT/s (2011) to 4800MT/s (2025) across 31 dies.
    010002000300040005000Interface speed the shipping part was specified at, MT/s20112012201320142015201620172018201920202021202220232024202520nm 128Gb MLC (Intel and Micron), announced: 333MT/s, 12/20111st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source), mass production: 533MT/s, 8/20132nd-gen V-NAND 128Gb TLC (32 WL): 400MT/s, 2/201532-layer 256Gb MLC (Micron and Intel) (die area from a teardown, secondary source), announced: 667MT/s, 3/201532-layer 384Gb TLC (Micron and Intel) (die area and density from a teardown, secondary source), announced: 667MT/s, 3/20153rd-gen V-NAND 256Gb TLC (48 WL), mass production: 400MT/s, 8/20154th-gen V-NAND 512Gb TLC (64 WL): 800MT/s, 8/2016BiCS3 512Gb TLC (Toshiba/WD, 64 WL layers): 533MT/s, 2/2017BiCS4 512Gb TLC (Toshiba Memory, 96 WL layers; product interface speed from a review, secondary source): 800MT/s, 2/20185th-gen V-NAND 256Gb TLC (Toggle DDR 4.0), mass production: 1400MT/s, 7/20186th-gen V-NAND 512Gb TLC (product interface speed from a review, secondary source): 1400MT/s, 2/2019128-layer 1Tb TLC 4D NAND, mass production: 1400MT/s, 6/201996L FG 1Tb QLC (CuA; product interface speed from a review, secondary source): 800MT/s, 5/2020X2-6070 128-layer QLC (Xtacking 2.0): 1600MT/s, 2020X2-9060 128-layer TLC (Xtacking 2.0; die area, density and planes from a teardown, secondary source): 1600MT/s, 2020176-layer TLC (capacity, die area and density from a teardown, secondary source), shipping: 1600MT/s, 11/2020144L FG 1Tb QLC (product interface speed from a review, secondary source): 1200MT/s, 2/2021176-layer QLC (replacement gate) (density from a teardown, secondary source), shipping: 1600MT/s, 1/20228th-gen V-NAND 1Tb TLC (Toggle DDR 5.0): 2400MT/s, 2/2022X3-9070 1Tb TLC (Xtacking 3.0; layer count, die area and density from a teardown, secondary source): 2400MT/s, 2022G8 232-layer TLC, shipping: 1600MT/s, 7/2022238-layer 512Gb TLC 4D NAND, developed: 2400MT/s, 8/2022X3-6070 1Tb QLC (Xtacking 3.0): 2400MT/s, 2023BiCS8 218-layer 1Tb TLC (Kioxia/Sandisk, VLSI 2023 and IEDM 2023): 3600MT/s, 3/2024V9 1Tb TLC (Toggle 5.1), announced: 3200MT/s, 4/2024X4-9060 512Gb TLC (Xtacking 4.0; die area and layer count from a teardown, secondary source): 3600MT/s, 2024X4-9070 1Tb TLC (Xtacking 4.0): 3600MT/s, 2024G9 276-layer TLC (Micron 2650), shipping: 3600MT/s, 7/2024G9 2Tb QLC (Micron 2600), announced: 3600MT/s, 6/2025X4-6080 2Tb QLC (Xtacking 4.0): 3600MT/s, 2025BiCS10 332-layer 1Tb TLC (previewed at ISSCC 2025), sampling: 4800MT/s, 2025
    Cell type across 90 of the 97 dies: 2 SLC, 21 MLC, 43 TLC, 23 QLC, 1 PLC. The other 7 have no cell type in their sources, so they are left off. Each row is one cell type, from SLC at the bottom to the most bits per cell at the top, and each point is colored by its type.
    SLCMLCTLCQLCPLCCell type, bits stored per cell200520062007200820092010201120122013201420152016201720182019202020212022202320242025202670nm 8Gb MLC planar NAND (JSSC 2006): MLC, 200556nm 8Gb MLC planar NAND (ISSCC 2006): MLC, 2/200670nm 16Gb 4b/cell planar NAND (VLSI 2007): QLC, 200743nm 16Gb MLC planar NAND (ISSCC 2008): MLC, 2/200834nm 32Gb MLC (Intel and Micron), announced: MLC, 5/200850nm 8Gb DDR-interface NAND (Intel and Micron, ISSCC 2008): SLC, 200845nm 4Gb MLC double-stacked NAND, two planar layers (ISSCC 2008): MLC, 200856nm 16Gb MLC all-bitline NAND (ISSCC 2008): MLC, 200856nm 16Gb TLC planar NAND (Li et al., ISSCC 2008): TLC, 2008Sub-35nm 32Gb TLC planar NAND (ISSCC 2009): TLC, 2/200948nm 32Gb TLC planar NAND (ISSCC 2009): TLC, 200943nm 64Gb 4b/cell planar NAND (ISSCC 2009): QLC, 200932nm 32Gb MLC planar NAND (Lee et al., ISSCC 2010): MLC, 2/201025nm 64Gb MLC (Intel and Micron), announced: MLC, 2/201032nm 32Gb MLC planar NAND (ISSCC 2010): MLC, 2/201034nm 32Gb TLC planar NAND (Intel and Micron, ISSCC 2010): TLC, 2/201026nm 32Gb MLC planar NAND (ISSCC 2011): MLC, 2/201120nm-class 64Gb TLC planar NAND (ISSCC 2011): TLC, 2/201120nm 64Gb MLC (Intel and Micron), announced: MLC, 4/201124nm 64Gb MLC planar NAND (ISSCC 2011): MLC, 201120nm 128Gb MLC (Intel and Micron), announced: MLC, 12/2011Sub-20nm 64Gb MLC planar NAND (ISSCC 2012): MLC, 201219nm 64Gb MLC planar NAND (ISSCC 2012): MLC, 201219nm 128Gb TLC planar NAND (ISSCC 2012): TLC, 201216nm 64Gb MLC planar NAND (ISSCC 2014): MLC, 201320nm 128Gb TLC planar NAND (ISSCC 2013) (die size and density from a Toshiba table, secondary source): TLC, 201316nm 128Gb MLC, sampling: MLC, 7/20131st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source), mass production: MLC, 8/20132nd-gen V-NAND 128Gb TLC (32 WL): TLC, 2/201532-layer 256Gb MLC (Micron and Intel) (die area from a teardown, secondary source), announced: MLC, 3/201532-layer 384Gb TLC (Micron and Intel) (die area and density from a teardown, secondary source), announced: TLC, 3/201515nm 64Gb MLC planar NAND (ISSCC 2015): MLC, 20153rd-gen V-NAND 256Gb TLC (48 WL), mass production: TLC, 8/2015BiCS 48-layer 256Gb TLC (Toshiba) (die area and density from a teardown, secondary source), announced: TLC, 8/201514nm 128Gb MLC planar NAND (ISSCC 2016 paper 7.5): MLC, 2/2016768Gb 3b/cell 3D floating-gate NAND with CMOS under array (Micron and Intel, ISSCC 2016 paper 7.7): TLC, 2/20164th-gen V-NAND 512Gb TLC (64 WL): TLC, 8/2016BiCS3 512Gb TLC (Toshiba/WD, 64 WL layers): TLC, 2/201772-layer 256Gb TLC 3D NAND (density from a teardown, secondary source), announced: TLC, 4/2017BiCS 64-layer 768Gb QLC (Toshiba), announced: QLC, 6/2017BiCS4 512Gb TLC (Toshiba Memory, 96 WL layers; product interface speed from a review, secondary source): TLC, 2/201864-stacked-WL 1Tb QLC (ISSCC 2018): QLC, 2/201864-layer 1Tb QLC (Micron and Intel), shipping: QLC, 5/20185th-gen V-NAND 256Gb TLC (Toggle DDR 4.0), mass production: TLC, 7/201896-layer 512Gb TLC 4D NAND (CTF and PUC) (density from a teardown, secondary source), launched: TLC, 11/20186th-gen V-NAND 512Gb TLC (product interface speed from a review, secondary source): TLC, 2/2019ISSCC 2019 512Gb TLC 128 WL layers, CuA, 4-plane: TLC, 2/2019128-layer 1Tb TLC 4D NAND, mass production: TLC, 6/201964-layer 256Gb TLC (Xtacking) (die area, density and planes from a teardown, secondary source), mass production: TLC, 9/2019BiCS5 112-layer 512Gb TLC (density from a teardown, secondary source), announced: TLC, 1/2020BiCS4 1.33Tb QLC (96 WL layers): QLC, 1/202092-stacked-WL 1Tb QLC (ISSCC 2020 paper 13.1): QLC, 2/202096L QLC 1Tb (PUC): QLC, 2/202096L FG 1Tb QLC (CuA; product interface speed from a review, secondary source): QLC, 5/2020X2-9060 128-layer TLC (Xtacking 2.0; die area, density and planes from a teardown, secondary source): TLC, 2020X2-6070 128-layer QLC (Xtacking 2.0): QLC, 2020176-layer TLC (capacity, die area and density from a teardown, secondary source), shipping: TLC, 11/2020XL-FLASH G1 128Gb SLC (96 WL layers): SLC, 1/2021ISSCC 2021 1Tb TLC 170+ WL layers, CuA, 4-plane: TLC, 2/20217th-gen V-NAND 512Gb TLC (CoP; density note cites a teardown, secondary source): TLC, 2/2021176L TLC 512Gb (4D PUC; die area from a teardown, secondary source): TLC, 2/2021144L FG 1Tb QLC (product interface speed from a review, secondary source): QLC, 2/2021176-layer QLC (replacement gate) (density from a teardown, secondary source), shipping: QLC, 1/20228th-gen V-NAND 1Tb TLC (Toggle DDR 5.0): TLC, 2/2022BiCS6 1Tb QLC (162 WL layers, WD/Kioxia): QLC, 2/2022176-stacked-WL 1Tb QLC (ISSCC 2022): QLC, 2/2022X3-9070 1Tb TLC (Xtacking 3.0; layer count, die area and density from a teardown, secondary source): TLC, 2022G8 232-layer TLC, shipping: TLC, 7/2022238-layer 512Gb TLC 4D NAND, developed: TLC, 8/2022192L FG 1.67Tb 5b/cell (PLC): PLC, 2/2023300+ layer 1Tb TLC (ISSCC 2023 paper 28.2): TLC, 2023X3-6070 1Tb QLC (Xtacking 3.0): QLC, 2023192L QLC (D5-P5336): QLC, 10/2023280-layer 1Tb QLC (ISSCC 2024 paper 13.3): QLC, 2/2024BiCS8 218-layer 1Tb TLC (Kioxia/Sandisk, VLSI 2023 and IEDM 2023): TLC, 3/2024V9 1Tb TLC (Toggle 5.1), announced: TLC, 4/2024X4-9060 512Gb TLC (Xtacking 4.0; die area and layer count from a teardown, secondary source): TLC, 2024X4-9070 1Tb TLC (Xtacking 4.0): TLC, 2024G9 276-layer TLC (Micron 2650), shipping: TLC, 7/2024V9 1Tb QLC, announced: QLC, 9/2024321-layer 1Tb TLC (die area and density from a teardown, secondary source), mass production: TLC, 11/2024321-layer 2Tb 4b/cell (ISSCC 2025 paper): QLC, 2/2025G9 2Tb QLC (Micron 2600), announced: QLC, 6/2025BiCS10 332-layer 1Tb TLC (previewed at ISSCC 2025), sampling: TLC, 2025X4-6080 2Tb QLC (Xtacking 4.0): QLC, 20254XX-layer bonded 1Tb TLC with 5.6 Gb/s/pin IO (JSSC 2025, BV-NAND): TLC, 10/2025MSA-CBA multi-wafer stacked prototype, QLC (VLSI 2026 T1.4, with Sandisk), announced: QLC, 6/2026BiCS10 332-layer 2Tb QLC 6-plane (ISSCC 2026 paper 15.1, with Sandisk): QLC, 2026BiCS9 230-layer 1Tb TLC, sampling: TLC, 7/2026V10 375-layer 1Tb TLC, shown at fms: TLC, 8/2026

    Every dot in a row is the same cell type. Each maker’s dots sit a little above or below the line so dies from the same year don’t cover each other. The offset has no meaning.

    • Record: the best any die had reached by then
    • Samsung
    • Kioxia and WD
    • SK hynix
    • Micron
    • Intel
    • Solidigm
    • YMTC
    • Fastest published interface standard (ONFI or JESD230)
    • Fastest NAND speed a public controller brief listed
    • SLC
    • MLC
    • TLC
    • QLC
    • PLC

    Showing the 32 planar dies only, in the chart and the die table.

    Showing the 1 stacked-planar test chip only, in the chart and the die table: whole planar arrays stacked on each other, not vertical 3D NAND.

    Showing the 64 3D dies only, in the chart and the die table.

    15 records, oldest first. Each die beat every earlier die on word-line layers.

    1. 11/2002

      Planar

      120nm 1Gb planar NAND (Lee et al., JSSC 2002)

      The first record on the chart.

      Maker
      Samsung

    2. 8/2013

      24 layers

      1st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source), mass production

      Up from Planar, set by 120nm 1Gb planar NAND (Lee et al., JSSC 2002).

      Maker
      Samsung

    3. 2/2015

      32 layers

      2nd-gen V-NAND 128Gb TLC (32 WL)

      Up from 24 layers, set by 1st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source), mass production.

      Maker
      Samsung

    4. 8/2015

      48 layers

      3rd-gen V-NAND 256Gb TLC (48 WL), mass production

      Up from 32 layers, set by 2nd-gen V-NAND 128Gb TLC (32 WL).

      Maker
      Samsung

    5. 8/2016

      64 layers

      4th-gen V-NAND 512Gb TLC (64 WL)

      Up from 48 layers, set by 3rd-gen V-NAND 256Gb TLC (48 WL), mass production.

      Maker
      Samsung

    6. 4/2017

      72 layers

      72-layer 256Gb TLC 3D NAND (density from a teardown, secondary source), announced

      Up from 64 layers, set by 4th-gen V-NAND 512Gb TLC (64 WL).

      Maker
      SK hynix

    7. 2/2018

      96 layers

      BiCS4 512Gb TLC (Toshiba Memory, 96 WL layers; product interface speed from a review, secondary source)

      Up from 72 layers, set by 72-layer 256Gb TLC 3D NAND (density from a teardown, secondary source), announced.

      Maker
      Kioxia and WD

    8. 2/2019

      ≥120 layers

      6th-gen V-NAND 512Gb TLC (product interface speed from a review, secondary source)

      Up from 96 layers, set by BiCS4 512Gb TLC (Toshiba Memory, 96 WL layers; product interface speed from a review, secondary source).

      Maker
      Samsung

    9. 2/2019

      128 layers

      ISSCC 2019 512Gb TLC 128 WL layers, CuA, 4-plane

      Up from ≥120 layers, set by 6th-gen V-NAND 512Gb TLC (product interface speed from a review, secondary source).

      Maker
      Kioxia and WD

    10. 2/2021

      176 layers

      7th-gen V-NAND 512Gb TLC (CoP; density note cites a teardown, secondary source)

      Up from 128 layers, set by ISSCC 2019 512Gb TLC 128 WL layers, CuA, 4-plane.

      Maker
      Samsung

    11. 8/2022

      238 layers

      238-layer 512Gb TLC 4D NAND, developed

      Up from 176 layers, set by 7th-gen V-NAND 512Gb TLC (CoP; density note cites a teardown, secondary source).

      Maker
      SK hynix

    12. 2023

      ≥300 layers

      300+ layer 1Tb TLC (ISSCC 2023 paper 28.2)

      Up from 238 layers, set by 238-layer 512Gb TLC 4D NAND, developed.

      Maker
      SK hynix

    13. 11/2024

      321 layers

      321-layer 1Tb TLC (die area and density from a teardown, secondary source), mass production

      Up from ≥300 layers, set by 300+ layer 1Tb TLC (ISSCC 2023 paper 28.2).

      Maker
      SK hynix

    14. 2025

      332 layers

      BiCS10 332-layer 1Tb TLC (previewed at ISSCC 2025), sampling

      Up from 321 layers, set by 321-layer 1Tb TLC (die area and density from a teardown, secondary source), mass production.

      Maker
      Kioxia and WD

    15. 10/2025

      ≥400 layers

      4XX-layer bonded 1Tb TLC with 5.6 Gb/s/pin IO (JSSC 2025, BV-NAND)

      Up from 332 layers, set by BiCS10 332-layer 1Tb TLC (previewed at ISSCC 2025), sampling.

      Maker
      Samsung

    33 records, oldest first. Each die beat every earlier die on bit density.

    1. 11/2002

      0.0077Gb/mm2

      120nm 1Gb planar NAND (Lee et al., JSSC 2002)

      The first record on the chart.

      Maker
      Samsung

    2. 11/2002

      0.008Gb/mm2

      130nm 1Gb planar NAND (JSSC 2002)

      Up from 0.0077Gb/mm2, set by 120nm 1Gb planar NAND (Lee et al., JSSC 2002).

      Maker
      Kioxia and WD

    3. 11/2003

      0.014Gb/mm2

      90nm 2Gb planar NAND (JSSC 2003)

      Up from 0.008Gb/mm2, set by 130nm 1Gb planar NAND (JSSC 2002).

      Maker
      Samsung

    4. 2005

      0.055Gb/mm2

      70nm 8Gb MLC planar NAND (JSSC 2006)

      Up from 0.014Gb/mm2, set by 90nm 2Gb planar NAND (JSSC 2003).

      Maker
      Kioxia and WD

    5. 2/2006

      0.079Gb/mm2

      56nm 8Gb MLC planar NAND (ISSCC 2006)

      Up from 0.055Gb/mm2, set by 70nm 8Gb MLC planar NAND (JSSC 2006).

      Maker
      Kioxia and WD

    6. 2/2008

      0.13Gb/mm2

      43nm 16Gb MLC planar NAND (ISSCC 2008)

      Up from 0.079Gb/mm2, set by 56nm 8Gb MLC planar NAND (ISSCC 2006).

      Maker
      Kioxia and WD

    7. 5/2008

      0.19Gb/mm2

      34nm 32Gb MLC (Intel and Micron), announced

      Up from 0.13Gb/mm2, set by 43nm 16Gb MLC planar NAND (ISSCC 2008).

      Maker
      Micron

    8. 2/2009

      0.28Gb/mm2

      Sub-35nm 32Gb TLC planar NAND (ISSCC 2009)

      Up from 0.19Gb/mm2, set by 34nm 32Gb MLC (Intel and Micron), announced.

      Maker
      Kioxia and WD

    9. 2/2010

      0.38Gb/mm2

      25nm 64Gb MLC (Intel and Micron), announced

      Up from 0.28Gb/mm2, set by Sub-35nm 32Gb TLC planar NAND (ISSCC 2009).

      Maker
      Micron

    10. 4/2011

      0.54Gb/mm2

      20nm 64Gb MLC (Intel and Micron), announced

      Up from 0.38Gb/mm2, set by 25nm 64Gb MLC (Intel and Micron), announced.

      Maker
      Micron

    11. 2012

      0.75Gb/mm2

      19nm 128Gb TLC planar NAND (ISSCC 2012)

      Up from 0.54Gb/mm2, set by 20nm 64Gb MLC (Intel and Micron), announced.

      Maker
      Kioxia and WD

    12. 8/2013

      0.96Gb/mm2

      1st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source), mass production

      Up from 0.75Gb/mm2, set by 19nm 128Gb TLC planar NAND (ISSCC 2012).

      Maker
      Samsung

    13. 2/2015

      1.86Gb/mm2

      2nd-gen V-NAND 128Gb TLC (32 WL)

      Up from 0.96Gb/mm2, set by 1st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source), mass production.

      Maker
      Samsung

    14. 3/2015

      2.28Gb/mm2

      32-layer 384Gb TLC (Micron and Intel) (die area and density from a teardown, secondary source), announced

      Up from 1.86Gb/mm2, set by 2nd-gen V-NAND 128Gb TLC (32 WL).

      Maker
      Micron

    15. 8/2015

      2.6Gb/mm2

      3rd-gen V-NAND 256Gb TLC (48 WL), mass production

      Up from 2.28Gb/mm2, set by 32-layer 384Gb TLC (Micron and Intel) (die area and density from a teardown, secondary source), announced.

      Maker
      Samsung

    16. 2/2016

      4.29Gb/mm2

      768Gb 3b/cell 3D floating-gate NAND with CMOS under array (Micron and Intel, ISSCC 2016 paper 7.7)

      Up from 2.6Gb/mm2, set by 3rd-gen V-NAND 256Gb TLC (48 WL), mass production.

      Maker
      Micron

    17. 2/2018

      5.63Gb/mm2

      64-stacked-WL 1Tb QLC (ISSCC 2018)

      Up from 4.29Gb/mm2, set by 768Gb 3b/cell 3D floating-gate NAND with CMOS under array (Micron and Intel, ISSCC 2016 paper 7.7).

      Maker
      Samsung

    18. 2/2018

      5.95Gb/mm2

      BiCS4 512Gb TLC (Toshiba Memory, 96 WL layers; product interface speed from a review, secondary source)

      Up from 5.63Gb/mm2, set by 64-stacked-WL 1Tb QLC (ISSCC 2018).

      Maker
      Kioxia and WD

    19. 11/2018

      6.3Gb/mm2

      96-layer 512Gb TLC 4D NAND (CTF and PUC) (density from a teardown, secondary source), launched

      Up from 5.95Gb/mm2, set by BiCS4 512Gb TLC (Toshiba Memory, 96 WL layers; product interface speed from a review, secondary source).

      Maker
      SK hynix

    20. 2/2019

      7.8Gb/mm2

      ISSCC 2019 512Gb TLC 128 WL layers, CuA, 4-plane

      Up from 6.3Gb/mm2, set by 96-layer 512Gb TLC 4D NAND (CTF and PUC) (density from a teardown, secondary source), launched.

      Maker
      Kioxia and WD

    21. 1/2020

      8.5Gb/mm2

      BiCS4 1.33Tb QLC (96 WL layers)

      Up from 7.8Gb/mm2, set by ISSCC 2019 512Gb TLC 128 WL layers, CuA, 4-plane.

      Maker
      Kioxia and WD

    22. 5/2020

      8.9Gb/mm2

      96L FG 1Tb QLC (CuA; product interface speed from a review, secondary source)

      Up from 8.5Gb/mm2, set by BiCS4 1.33Tb QLC (96 WL layers).

      Maker
      Intel

    23. 11/2020

      10.27Gb/mm2

      176-layer TLC (capacity, die area and density from a teardown, secondary source), shipping

      Up from 8.9Gb/mm2, set by 96L FG 1Tb QLC (CuA; product interface speed from a review, secondary source).

      Maker
      Micron

    24. 2/2021

      10.4Gb/mm2

      ISSCC 2021 1Tb TLC 170+ WL layers, CuA, 4-plane

      Up from 10.27Gb/mm2, set by 176-layer TLC (capacity, die area and density from a teardown, secondary source), shipping.

      Maker
      Kioxia and WD

    25. 2/2021

      10.8Gb/mm2

      176L TLC 512Gb (4D PUC; die area from a teardown, secondary source)

      Up from 10.4Gb/mm2, set by ISSCC 2021 1Tb TLC 170+ WL layers, CuA, 4-plane.

      Maker
      SK hynix

    26. 2/2021

      13.8Gb/mm2

      144L FG 1Tb QLC (product interface speed from a review, secondary source)

      Up from 10.8Gb/mm2, set by 176L TLC 512Gb (4D PUC; die area from a teardown, secondary source).

      Maker
      Intel

    27. 2/2022

      15Gb/mm2

      BiCS6 1Tb QLC (162 WL layers, WD/Kioxia)

      Up from 13.8Gb/mm2, set by 144L FG 1Tb QLC (product interface speed from a review, secondary source).

      Maker
      Kioxia and WD

    28. 2022

      15.03Gb/mm2

      X3-9070 1Tb TLC (Xtacking 3.0; layer count, die area and density from a teardown, secondary source)

      Up from 15Gb/mm2, set by BiCS6 1Tb QLC (162 WL layers, WD/Kioxia).

      Maker
      YMTC

    29. 2/2023

      23.3Gb/mm2

      192L FG 1.67Tb 5b/cell (PLC)

      Up from 15.03Gb/mm2, set by X3-9070 1Tb TLC (Xtacking 3.0; layer count, die area and density from a teardown, secondary source).

      Maker
      Intel

    30. 2/2024

      28.5Gb/mm2

      280-layer 1Tb QLC (ISSCC 2024 paper 13.3)

      Up from 23.3Gb/mm2, set by 192L FG 1.67Tb 5b/cell (PLC).

      Maker
      Samsung

    31. 2/2025

      28.8Gb/mm2

      321-layer 2Tb 4b/cell (ISSCC 2025 paper)

      Up from 28.5Gb/mm2, set by 280-layer 1Tb QLC (ISSCC 2024 paper 13.3).

      Maker
      SK hynix

    32. 2025

      ≥29Gb/mm2

      BiCS10 332-layer 1Tb TLC (previewed at ISSCC 2025), sampling

      Up from 28.8Gb/mm2, set by 321-layer 2Tb 4b/cell (ISSCC 2025 paper).

      Maker
      Kioxia and WD

    33. 2026

      37.6Gb/mm2

      BiCS10 332-layer 2Tb QLC 6-plane (ISSCC 2026 paper 15.1, with Sandisk)

      Up from ≥29Gb/mm2, set by BiCS10 332-layer 1Tb TLC (previewed at ISSCC 2025), sampling.

      Maker
      Kioxia and WD

    9 records, oldest first. Each die beat every earlier die on I/O speed.

    1. 12/2011

      333MT/s

      20nm 128Gb MLC (Intel and Micron), announced

      The first record on the chart.

      Maker
      Micron

    2. 8/2013

      533MT/s

      1st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source), mass production

      Up from 333MT/s, set by 20nm 128Gb MLC (Intel and Micron), announced.

      Maker
      Samsung

    3. 3/2015

      667MT/s

      32-layer 256Gb MLC (Micron and Intel) (die area from a teardown, secondary source), announced

      Up from 533MT/s, set by 1st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source), mass production.

      Maker
      Micron

    4. 8/2016

      800MT/s

      4th-gen V-NAND 512Gb TLC (64 WL)

      Up from 667MT/s, set by 32-layer 256Gb MLC (Micron and Intel) (die area from a teardown, secondary source), announced.

      Maker
      Samsung

    5. 7/2018

      1400MT/s

      5th-gen V-NAND 256Gb TLC (Toggle DDR 4.0), mass production

      Up from 800MT/s, set by 4th-gen V-NAND 512Gb TLC (64 WL).

      Maker
      Samsung

    6. 2020

      1600MT/s

      X2-6070 128-layer QLC (Xtacking 2.0)

      Up from 1400MT/s, set by 5th-gen V-NAND 256Gb TLC (Toggle DDR 4.0), mass production.

      Maker
      YMTC

    7. 2/2022

      2400MT/s

      8th-gen V-NAND 1Tb TLC (Toggle DDR 5.0)

      Up from 1600MT/s, set by X2-6070 128-layer QLC (Xtacking 2.0).

      Maker
      Samsung

    8. 3/2024

      3600MT/s

      BiCS8 218-layer 1Tb TLC (Kioxia/Sandisk, VLSI 2023 and IEDM 2023)

      Up from 2400MT/s, set by 8th-gen V-NAND 1Tb TLC (Toggle DDR 5.0).

      Maker
      Kioxia and WD

    9. 2025

      4800MT/s

      BiCS10 332-layer 1Tb TLC (previewed at ISSCC 2025), sampling

      Up from 3600MT/s, set by BiCS8 218-layer 1Tb TLC (Kioxia/Sandisk, VLSI 2023 and IEDM 2023).

      Maker
      Kioxia and WD

    3 records, oldest first. Each die beat every earlier die on cell type.

    1. 2005

      MLC

      70nm 8Gb MLC planar NAND (JSSC 2006)

      The first record on the chart.

      Maker
      Kioxia and WD

    2. 2007

      QLC

      70nm 16Gb 4b/cell planar NAND (VLSI 2007)

      Up from MLC, set by 70nm 8Gb MLC planar NAND (JSSC 2006).

      Maker
      Kioxia and WD

    3. 2/2023

      PLC

      192L FG 1.67Tb 5b/cell (PLC)

      Up from QLC, set by 70nm 16Gb 4b/cell planar NAND (VLSI 2007).

      Maker
      Intel

    Sort the die table by cell type

    How to read it

    Each point is one die that a paper or announcement describes. It sits at the date of the earliest paper or announcement cited for that die, which is not the year the die went into production, and a later paper that re-reports an old die does not move it. A point sits at its month when a source gives one, and mid-year when only the year is known. The chart shows 97 dies from 150 sources, 64 of them papers, not every die ever made, and a die without a value for the chosen measure is left off.

    Interface speed is the speed the shipping part was specified at, from a datasheet, product page or a vendor statement; a die with no such source is left off. A test chip in a paper can run faster than the interface standards and controllers of its day allowed, so the I/O chart shows the speed each shipping part was specified at, with a dashed line for the fastest published ONFI or JESD230 speed and a dotted line for the fastest NAND speed any public controller brief listed. A peak a paper prints for a test chip is not shown, because it is not what a drive of that year ran.

    Layers are word-line layers as the paper prints them. Vendors stack their arrays in different ways, so a layer count is not a like-for-like measure across vendors. Before 3D NAND, a die was planar: one layer of cells, made denser by shrinking the process node. On the layers chart a planar die sits on the bottom line at 1, and its name gives the node. Samsung’s 2008 double-stacked test chip, two planar layers on top of each other, sits at 2 on its own: Samsung called it 3D, but each layer is a planar floating-gate array, so it is filed as stacked planar and never sets a 3D record. The first vertical 3D record is Samsung’s 24-layer die of 2013. The Structure chips, above the chart and over the die table, show the planar, stacked-planar or 3D dies alone, on the chart and in the table.

    On the cell-type chart each row is one cell type: SLC stores one bit per cell, MLC two, TLC three and QLC four. Points are colored by type and keep their vendor’s shape, so you can see when each maker moved to more bits per cell. A die whose sources do not give its cell type is left off.

    Layers and density use a log scale, where each gridline step multiplies the value rather than adding to it. On a straight scale the older dies would crowd along the floor. Density and interface speed are the sources’ own figures, or a density worked out from the capacity and die size a source prints.

    In the table below, Date is the month and year a press release gives for the announcement, samples or production, or the month the earliest paper or page was published. It is the year alone only when none of that year’s sources gives a month, such as an undated product page. Status says what the sources describe: a paper, a product page, or a vendor’s announcement, sampling or production news. Structure is the cell a source states: planar or 3D, and floating gate or charge trap. Where no cited source names the cell, it reads planar or 3D from the layer data and says the cell is not stated. tR is the time to read a page, tPROG the time to program one, and Program is the write throughput the source states. A dash means that value hasn’t been published for the die. Where the maker prints nothing, a die size, density, layer count or plane count can come from a TechInsights teardown, marked T, and a density worked out from a die size, the maker’s or a teardown’s, is marked D. A maker's own figure always wins over a teardown figure. Each source is a short label; hover it or open it for the full title.

    Rankings

    The same dies, ranked two ways: by bit density, and by the tallest stack each maker has stated. Every density is read from the die above, so a fix to a die shows here too.

    Density ranking28 dies

    Bit density is a die’s capacity in gigabits over its area in square millimeters (Gb/mm²). Kioxia’s BiCS10 332-layer 2Tb QLC 6-plane (ISSCC 2026 paper 15.1, with Sandisk) leads at 37.6 Gb/mm². The top spot passed through 16 dies here: 2002 (0.0077), 2006 (0.079), 2008 (0.11), 2010 (0.38), 2012 (0.75), 2013 (0.96), 2015 (2.6), 2016 (4.29), 2019 (7.8), 2020 (10.3), 2021 (13.8), 2022 (15), 2023 (23.3), 2024 (28.5), 2025 (29), 2026 (37.6) Gb/mm².

    Bit density of ranked dies by year (Gb/mm²)

    • planar floating gate
    • 3D floating gate
    • 3D charge trap
    • Held the top spot
    0.0010.010.11101002004200820122016202020242026: Kioxia BiCS10 332-layer 2Tb QLC 6-plane (ISSCC 2026 paper 15.1, with Sandisk), 37.6 Gb/mm²37.62025: Kioxia BiCS10 332-layer 1Tb TLC (previewed at ISSCC 2025), 29 Gb/mm²2024: Samsung 280-layer 1Tb QLC (ISSCC 2024 paper 13.3), 28.5 Gb/mm²28.52025: Samsung 4XX-layer bonded 1Tb TLC with 5.6 Gb/s/pin IO (JSSC 2025, BV-NAND), 28 Gb/mm²2024: SK hynix 321-layer 1Tb TLC (die area and density from a teardown, secondary source), 23.5 Gb/mm²2023: Intel 192L FG 1.67Tb 5b/cell (PLC), 23.3 Gb/mm²2024: Kioxia BiCS8 218-layer 1Tb TLC (Kioxia/Sandisk, VLSI 2023 and IEDM 2023), 18.3 Gb/mm²2022: YMTC X3-9070 1Tb TLC (Xtacking 3.0; layer count, die area and density from a teardown, secondary source), 15 Gb/mm²152022: Kioxia BiCS6 1Tb QLC (162 WL layers, WD/Kioxia), 15 Gb/mm²2022: SK hynix 176-stacked-WL 1Tb QLC (ISSCC 2022), 14.8 Gb/mm²2022: Micron G8 232-layer TLC, 14.6 Gb/mm²2021: Intel 144L FG 1Tb QLC (product interface speed from a review, secondary source), 13.8 Gb/mm²2020: Micron 176-layer TLC (capacity, die area and density from a teardown, secondary source), 10.3 Gb/mm²10.32020: YMTC X2-9060 128-layer TLC (Xtacking 2.0; die area, density and planes from a teardown, secondary source), 8.47 Gb/mm²2019: Western Digital / Kioxia (Toshiba Memory) ISSCC 2019 512Gb TLC 128 WL layers, CuA, 4-plane, 7.8 Gb/mm²2021: Micron 128-layer 512Gb TLC (die B37R; teardown, secondary source), 7.76 Gb/mm²2023: Samsung 128-layer 512Gb TLC (single deck, die K9AHGD8U0B; teardown, secondary source), 6.96 Gb/mm²2016: Micron 768Gb 3b/cell 3D floating-gate NAND with CMOS under array (Micron and Intel, ISSCC 2016 paper 7.7), 4.29 Gb/mm²4.292016: Samsung 4th-gen V-NAND 512Gb TLC (64 WL), 3.98 Gb/mm²2015: Samsung 3rd-gen V-NAND 256Gb TLC (48 WL), 2.6 Gb/mm²2013: Samsung 1st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source), 0.96 Gb/mm²0.962013: Micron 20nm 128Gb TLC planar NAND (ISSCC 2013) (die size and density from a Toshiba table, secondary source), 0.87 Gb/mm²2012: SanDisk and Toshiba 19nm 128Gb TLC planar NAND (ISSCC 2012), 0.75 Gb/mm²2010: Micron 25nm 64Gb MLC (Intel and Micron), 0.38 Gb/mm²0.382010: Hynix 32nm 32Gb MLC planar NAND (Lee et al., ISSCC 2010), 0.22 Gb/mm²2008: SanDisk and Toshiba 56nm 16Gb TLC planar NAND (Li et al., ISSCC 2008), 0.11 Gb/mm²0.112006: Toshiba and SanDisk 56nm 8Gb MLC planar NAND (ISSCC 2006), 0.079 Gb/mm²0.0792002: Samsung 120nm 1Gb planar NAND (Lee et al., JSSC 2002), 0.0077 Gb/mm²0.0077
    Log scale. Only dies on this board are plotted, not every die ever made. The dashed line joins each die that beat all earlier ones here.

    Planar floating gate, 3D floating gate and 3D charge trap are ranked together but never mixed up: each has its own color and filter. For 15 dies the class rests on a statement about the maker’s whole product family, and the table marks them “family only”. A rank is a rank among these dies, not every die ever made.

    RankMakerDieClassLayersCapacity (Gb)Gb/mm²YearSource
    1KioxiaBiCS10 332-layer 2Tb QLC 6-plane (ISSCC 2026 paper 15.1, with Sandisk)took #13D charge trapfamily only3322,04837.62026ISSCC 2026 paper
    2KioxiaBiCS10 332-layer 1Tb TLC (previewed at ISSCC 2025)took #13D charge trapfamily only3321,024292025IEEE JSSC 2026 paper
    3Samsung280-layer 1Tb QLC (ISSCC 2024 paper 13.3)took #13D charge trapfamily only2801,02428.52024ISSCC 2024 paper
    4Samsung4XX-layer bonded 1Tb TLC with 5.6 Gb/s/pin IO (JSSC 2025, BV-NAND)3D charge trapfamily only≥4001,024282025IEEE JSSC 2025 paper
    5SK hynix321-layer 1Tb TLC (die area and density from a teardown, secondary source)3D charge trapfamily only3211,02423.52024TechInsights 2026 teardown
    6Intel192L FG 1.67Tb 5b/cell (PLC)took #13D floating gate1921,71023.32023ISSCC 2023 paper
    7KioxiaBiCS8 218-layer 1Tb TLC (Kioxia/Sandisk, VLSI 2023 and IEDM 2023)3D charge trapfamily only2181,02418.32024Kioxia 2024 release
    8YMTCX3-9070 1Tb TLC (Xtacking 3.0; layer count, die area and density from a teardown, secondary source)took #13D charge trapfamily only2321,024152022TechInsights 2023 teardown
    9KioxiaBiCS6 1Tb QLC (162 WL layers, WD/Kioxia)3D charge trapfamily only1621,024152022ISSCC 2022 paper
    10SK hynix176-stacked-WL 1Tb QLC (ISSCC 2022)3D charge trapfamily only1761,02414.82022ISSCC 2022 paper
    11MicronG8 232-layer TLC3D charge trapfamily only2321,02414.62022Micron 2022 release
    12Intel144L FG 1Tb QLC (product interface speed from a review, secondary source)took #13D floating gate1441,02413.82021ISSCC 2021 paper
    13Micron176-layer TLC (capacity, die area and density from a teardown, secondary source)took #13D charge trap17651210.32020TechInsights 2021 teardown
    14YMTCX2-9060 128-layer TLC (Xtacking 2.0; die area, density and planes from a teardown, secondary source)3D charge trap1285128.472020TechInsights 2023 teardown
    15Western Digital / Kioxia (Toshiba Memory)ISSCC 2019 512Gb TLC 128 WL layers, CuA, 4-planetook #13D charge trapfamily only1285127.82019ISSCC 2019 paper
    16Micron128-layer 512Gb TLC (die B37R; teardown, secondary source)3D charge trap1285127.762021TechInsights 2021 teardown
    17Samsung128-layer 512Gb TLC (single deck, die K9AHGD8U0B; teardown, secondary source)3D charge trap1285126.962023TechInsights 2023 teardown
    18Micron768Gb 3b/cell 3D floating-gate NAND with CMOS under array (Micron and Intel, ISSCC 2016 paper 7.7)took #13D floating gate7684.292016ISSCC 2016 paper
    19Samsung4th-gen V-NAND 512Gb TLC (64 WL)3D charge trap645123.982016IEEE JSSC 2018 paper
    20Samsung3rd-gen V-NAND 256Gb TLC (48 WL)took #13D charge trap482562.62015IEEE JSSC 2017 paper
    21Samsung1st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source)took #13D charge trap241280.962013IEEE JSSC 2020 paper
    22Micron20nm 128Gb TLC planar NAND (ISSCC 2013) (die size and density from a Toshiba table, secondary source)planar floating gate1280.872013ISSCC 2017 paper
    23SanDisk and Toshiba19nm 128Gb TLC planar NAND (ISSCC 2012)took #1planar floating gatefamily only1280.752012ISSCC 2017 paper
    24Micron25nm 64Gb MLC (Intel and Micron)took #1planar floating gatefamily only640.38*2010Intel/Micron 2010 release
    25Hynix32nm 32Gb MLC planar NAND (Lee et al., ISSCC 2010)planar floating gate320.22*2010ISSCC 2010 paper
    26SanDisk and Toshiba56nm 16Gb TLC planar NAND (Li et al., ISSCC 2008)took #1planar floating gate160.112008ISSCC 2008 paper
    27Toshiba and SanDisk56nm 8Gb MLC planar NAND (ISSCC 2006)took #1planar floating gatefamily only80.0792006ISSCC 2008 paper
    28Samsung120nm 1Gb planar NAND (Lee et al., JSSC 2002)took #1planar floating gatefamily only10.0077*2002IEEE JSSC 2002 paper

    * Computed from the capacity and die size the source gives. A die’s name links to its row in the full die list below.

    Layer race31 points

    How tall each maker has said its 3D NAND stack is, year by year: one line per maker, stepping up whenever it states a higher count. A point is the year of the statement, which can come before the die ships. 11 of 31 are marked shipping because the source says mass production, volume shipments or shipping; the rest are announced. The highest count so far: Samsung 400+ (announced), Micron 400+ (announced), SK hynix 375 (announced), Kioxia/Sandisk 332 (announced), YMTC 232 (shipping), Solidigm/Intel 192 (announced).

    Highest layer count each maker has stated, by year

    • Samsung
    • SK hynix
    • Kioxia/Sandisk
    • Micron
    • YMTC
    • Solidigm/Intel
    • Source says shipping
    • Announced
    010020030040020132015201720192021202320252013: Samsung 24 layers, V-NAND gen 1, 128Gb MLC, shipping2014: Samsung 32 layers, V-NAND gen 2, 3-bit MLC, announced2015: Samsung 48 layers, V-NAND gen 3, 256Gb TLC, shipping2018: Samsung 90+ layers, V-NAND gen 5, 256Gb, shipping2024: Samsung 280 layers, 280-layer 1Tb QLC (ISSCC 2024 paper 13.3), announced2026: Samsung 400+ layers, V10 BV-NAND, announced400+2017: SK hynix 72 layers, 72-layer 256Gb TLC, announced2018: SK hynix 96 layers, 96-layer 512Gb TLC 4D NAND, announced2019: SK hynix 128 layers, 128-layer 1Tb TLC 4D NAND, shipping2022: SK hynix 238 layers, 238-layer 512Gb TLC 4D NAND, announced2023: SK hynix 300+ layers, 1Tb TLC (ISSCC 2023 paper 28.2), announced2024: SK hynix 321 layers, 321-layer 1Tb TLC 4D NAND, shipping2026: SK hynix 375 layers, 375-layer 1Tb TLC 4D NAND (shown at FMS 2026), announced3752015: Kioxia 48 layers, BiCS FLASH 256Gb (Toshiba), announced2017: Kioxia 64 layers, BiCS3 512Gb TLC (ISSCC 2017 paper 11.1), announced2020: Kioxia 112 layers, BiCS5 512Gb TLC, announced2022: Kioxia 162 layers, BiCS6 1Tb QLC (ISSCC 2022), announced2023: Kioxia 218 layers, BiCS8 1Tb TLC, announced2026: Kioxia 332 layers, BiCS10, announced3322015: Micron 32 layers, 32-layer 256Gb MLC / 384Gb TLC (with Intel), announced2018: Micron 64 layers, 64-layer 1Tb QLC (with Intel), shipping2020: Micron 176 layers, 176-layer TLC, shipping2022: Micron 232 layers, 232-layer TLC, shipping2024: Micron 276 layers, G9 TLC (in Micron 2650), shipping2026: Micron 400+ layers, G11, announced2019: YMTC 64 layers, 64-layer 256Gb TLC (Xtacking), shipping2020: YMTC 128 layers, X2-6070 128-layer 1.33Tb QLC, announced2023: YMTC 232 layers, 232-layer TLC (Xtacking 3.0), secondary source, shipping2322015: Micron 32 layers, 32-layer 256Gb MLC / 384Gb TLC (with Intel), announced2018: Micron 64 layers, 64-layer 1Tb QLC (with Intel), shipping2020: Solidigm/Intel 96 layers, 96-layer FG QLC with CuA (IMW 2020), announced2021: Solidigm/Intel 144 layers, 1Tb QLC 144-tier FG (ISSCC 2021 paper 30.2), announced2023: Solidigm/Intel 192 layers, 192-layer FG PLC 1.67Tb (ISSCC 2023), announced192
    Layers (or word lines, where the source counts those), linear scale. The line steps up each time a maker states a higher count and runs on to the right edge, which does not mean the maker has said anything newer. The maker’s own wording decides filled or hollow.

    MakerLayers as statedYearStatusProductSource kindSourceNote
    Micron400+2026AnnouncedG11maker webinar slidess25.q4cdn.com">400 layers"; plotted at 400. Volume ramp in 2H 2027, so not shipping yet; Micron's shipping high stays 276 (G9).
    Samsung400+2026AnnouncedV10 BV-NANDmaker tech blogsemiconductor.samsung.com"more than 400 word lines"; plotted at 400. Blog is about the FMS 2026 award; no shipping wording.
    SK hynix3752026Announced375-layer 1Tb TLC 4D NAND (shown at FMS 2026)maker newsroomnews.skhynix.comShown as wafer and packages; no shipping wording.
    Kioxia3322026AnnouncedBiCS10maker releasekioxia.comSample shipments, not volume.
    SK hynix3212024Shipping321-layer 1Tb TLC 4D NANDmaker releasenews.skhynix.com
    Samsung2802024Announced280-layer 1Tb QLC (ISSCC 2024 paper 13.3)ISSCC paper title (Crossref/OpenAlex)doi.orgA conference paper, not a shipping claim.
    Micron2762024ShippingG9 TLC (in Micron 2650)maker release + product briefinvestors.micron.comThe release gives no layer count; "276-layer" is from Micron’s 2650 product brief ("Micron 3D 276-layer TLC NAND").
    SK hynix300+2023Announced1Tb TLC (ISSCC 2023 paper 28.2)ISSCC paper title (Crossref/OpenAlex)doi.org"over 300"; plotted at 300. The IEEE abstract does not name the maker; SK hynix is per ComputerBase.
    YMTC2322023Shipping232-layer TLC (Xtacking 3.0), secondary sourceTechInsights teardown blogtechinsights.comTechInsights teardown comparison (secondary source), read in the saved page; no YMTC page opened states 232 layers.
    Kioxia2182023AnnouncedBiCS8 1Tb TLCmaker R&D pagekioxia.comR&D page; figures credited ©IEEE 2023. No shipping wording on it. The page counts 218 word lines stacked.
    Solidigm/Intel1922023Announced192-layer FG PLC 1.67Tb (ISSCC 2023)ISSCC paper title (Crossref/OpenAlex)doi.org
    SK hynix2382022Announced238-layer 512Gb TLC 4D NANDmaker releasenews.skhynix.com
    Micron2322022Shipping232-layer TLCmaker releaseinvestors.micron.com
    Kioxia1622022AnnouncedBiCS6 1Tb QLC (ISSCC 2022)ISSCC paper title (Crossref/OpenAlex)doi.orgKioxia with Western Digital. The paper counts 162 WL layers (Fig 7.1.1).
    Solidigm/Intel1442021Announced1Tb QLC 144-tier FG (ISSCC 2021 paper 30.2)ISSCC paper title (Crossref/OpenAlex)doi.org
    Micron1762020Shipping176-layer TLCmaker releaseinvestors.micron.com
    YMTC1282020AnnouncedX2-6070 128-layer 1.33Tb QLCmaker releaseymtc.com
    Kioxia1122020AnnouncedBiCS5 512Gb TLCmaker releasekioxia.com
    Solidigm/Intel962020Announced96-layer FG QLC with CuA (IMW 2020)IMW paper title (Crossref/OpenAlex)doi.orgIMW, not ISSCC/IEDM.
    SK hynix1282019Shipping128-layer 1Tb TLC 4D NANDmaker releasenews.skhynix.com
    YMTC642019Shipping64-layer 256Gb TLC (Xtacking)maker releaseymtc.com
    SK hynix962018Announced96-layer 512Gb TLC 4D NANDmaker releasenews.skhynix.comMass production was planned, not yet started.
    Samsung90+2018ShippingV-NAND gen 5, 256Gbmaker releasenews.samsung.com"more than 90"; plotted at 90.
    Micron642018Shipping64-layer 1Tb QLC (with Intel)maker release (Intel)intc.comJoint release; drawn in both lanes.
    SK hynix722017Announced72-layer 256Gb TLCmaker releasenews.skhynix.comSame release says 48-layer "is already in mass production".
    Kioxia642017AnnouncedBiCS3 512Gb TLC (ISSCC 2017 paper 11.1)ISSCC paper title (Crossref/OpenAlex)doi.orgToshiba with SanDisk. The paper counts 64 word-line layers.
    Kioxia482015AnnouncedBiCS FLASH 256Gb (Toshiba)maker release (Toshiba)global.toshiba
    Samsung482015ShippingV-NAND gen 3, 256Gb TLCmaker releasenews.samsung.com
    Micron322015Announced32-layer 256Gb MLC / 384Gb TLC (with Intel)maker release (Intel)intc.comJoint Intel-Micron release; drawn in both lanes.
    Samsung322014AnnouncedV-NAND gen 2, 3-bit MLCmaker releasenews.samsung.comStated in the 2015 release; "introduced" gives no shipping wording.
    Samsung242013ShippingV-NAND gen 1, 128Gb MLCmaker releasenews.samsung.com

    These are stated counts, not a ranking of who is ahead: makers count layers differently, and a die with fewer layers can still win on density. A product links to the die it is about in the full list below. A row marked “secondary source” rests on a teardown or report, not the maker or its own paper.

    Every die and its source

    Structure, chart and table
    Cell type
    • means the maker hasn't published this figure.
    • Teardown figures are measured by TechInsights, not published by the maker.
    • Derived figures are the capacity divided by the die size in the cited source.
    DieVendorStatusDateCell typeStructureLayersCapacityDensityDie sizePlanesI/O speedtRtPROGProgramSource
    G11 400+ layers (volume ramp 2H 2027)MicronAnnounced10/2026not published3D, cell not stated≥400not publishednot publishednot publishednot publishednot publishednot publishednot publishednot publishedMicron 2026 release
    V10 375-layer 1Tb TLCSK hynixShown at FMS8/2026TLC3D, cell not stated3751Tbnot publishednot publishednot publishednot publishednot publishednot publishednot publishedSK hynix 2026 release
    BiCS9 230-layer 1Tb TLCKioxia/WDSampling7/2026TLC3D, cell not stated2301Tbnot publishednot publishednot publishednot publishednot publishednot publishednot publishedKioxia 2026 release
    MSA-CBA multi-wafer stacked prototype, QLC (VLSI 2026 T1.4, with Sandisk)Kioxia/WDAnnounced6/2026QLC3D, cell not statednot publishednot publishednot publishednot publishednot publishednot publishednot publishednot publishednot publishedKioxia 2026 release
    BiCS10 332-layer 2Tb QLC 6-plane (ISSCC 2026 paper 15.1, with Sandisk)Kioxia/WDPaper2026QLC3D, cell not stated3322Tb37.6Gb/mm2not published6not published≤65µsnot published≥85MB/sISSCC 2026 paperKioxia / Sandisk 2026 release
    4XX-layer bonded 1Tb TLC with 5.6 Gb/s/pin IO (JSSC 2025, BV-NAND)SamsungPaper10/2025TLC3D, cell not stated≥4001Tb28Gb/mm2not publishednot publishednot publishednot publishednot publishednot publishedIEEE JSSC 2025 paperSamsung 2026 release
    G9 2Tb QLC (Micron 2600)MicronAnnounced6/2025QLC3D, cell not statednot published2Tbnot publishednot published63600MT/snot publishednot publishednot publishedMicron 2025 releaseMicron 2025 product page
    321-layer 2Tb 4b/cell (ISSCC 2025 paper)SK hynixPaper2/2025QLC3D, cell not stated3212Tb28.8Gb/mm2not published6not published80µs1300µs75MB/sISSCC 2025 paperSK hynix 2025 release
    BiCS10 332-layer 1Tb TLC (previewed at ISSCC 2025)Kioxia/WDSampling2025TLC3D, cell not stated3321Tb≥29Gb/mm2not published44800MT/snot publishednot publishednot publishedKioxia 2026 releaseIEEE JSSC 2026 paperKioxia 2025 releaseKioxia 2026 release
    X4-6080 2Tb QLC (Xtacking 4.0)YMTCProduct2025QLC3D, cell not statednot published2Tbnot publishednot published83600MT/snot publishednot publishednot publishedYMTC 2025 product page
    321-layer 1Tb TLC (die area and density from a teardown, secondary source)SK hynixMass production11/2024TLC3D, cell not stated3211Tb23.52Gb/mm2, teardown figure, measured by TechInsights43.54mm2, teardown figure, measured by TechInsightsnot publishednot publishednot publishednot publishednot publishedSK hynix 2024 releaseTechInsights 2026 teardown
    V9 1Tb QLCSamsungAnnounced9/2024QLC3D, cell not statednot published1Tbnot publishednot publishednot publishednot publishednot publishednot publishednot publishedSamsung 2024 release
    G9 276-layer TLC (Micron 2650)MicronShipping7/2024TLC3D, cell not stated2761Tbnot publishednot published63600MT/snot publishednot publishednot publishedMicron 2024 product pageMicron 2024 release
    V9 1Tb TLC (Toggle 5.1)SamsungAnnounced4/2024TLC3D, cell not statednot published1Tbnot publishednot publishednot published3200MT/snot publishednot publishednot publishedSamsung 2024 release
    BiCS8 218-layer 1Tb TLC (Kioxia/Sandisk, VLSI 2023 and IEDM 2023)Kioxia/WDProduct3/2024TLC3D, cell not stated2181Tb18.3Gb/mm2not published43600MT/s40µsnot published205MB/sKioxia 2024 releaseKioxia 2025 product page
    280-layer 1Tb QLC (ISSCC 2024 paper 13.3)SamsungPaper2/2024QLC3D, cell not stated2801Tb28.5Gb/mm2not publishednot publishednot publishednot publishednot publishednot publishedISSCC 2024 paper
    X4-9060 512Gb TLC (Xtacking 4.0; die area and layer count from a teardown, secondary source)YMTCProduct2024TLC3D, cell not stated160, teardown figure, measured by TechInsights512Gbnot published40.44mm2, teardown figure, measured by TechInsightsnot published3600MT/snot publishednot publishednot publishedYMTC 2024 product pageTechInsights 2024 teardown
    X4-9070 1Tb TLC (Xtacking 4.0)YMTCProduct2024TLC3D, cell not statednot published1Tbnot publishednot published63600MT/snot publishednot publishednot publishedYMTC 2024 product page
    192L QLC (D5-P5336)SolidigmProduct10/2023QLC3D, cell not stated192not published18.6Gb/mm2not publishednot publishednot publishednot publishednot publishednot publishedSolidigm 2024 product pageSolidigm 2023 release
    192L FG 1.67Tb 5b/cell (PLC)IntelPaper2/2023PLC3D floating gate1921.67Tb23.3Gb/mm273.3mm24not published354µs5500µsnot publishedISSCC 2023 paper
    128-layer 512Gb TLC (single deck, die K9AHGD8U0B; teardown, secondary source)SamsungAnnounced2023not published3D, cell not stated128, teardown figure, measured by TechInsights512Gb, teardown figure, measured by TechInsights6.96Gb/mm2, teardown figure, measured by TechInsights73.6mm2, teardown figure, measured by TechInsightsnot publishednot publishednot publishednot publishednot publishedTechInsights 2023 teardown
    300+ layer 1Tb TLC (ISSCC 2023 paper 28.2)SK hynixPaper2023TLC3D, cell not stated≥3001Tbnot publishednot publishednot publishednot published34µsnot published194MB/sISSCC 2023 paperComputerBase 2023 release
    X3-6070 1Tb QLC (Xtacking 3.0)YMTCProduct2023QLC3D, cell not statednot published1Tbnot publishednot publishednot published2400MT/snot publishednot publishednot publishedYMTC 2023 product page
    238-layer 512Gb TLC 4D NANDSK hynixDeveloped8/2022TLC3D charge trap238512Gbnot publishednot publishednot published2400MT/snot publishednot publishednot publishedSK hynix 2022 releaseSK hynix 2023 release
    G8 232-layer TLCMicronShipping7/2022TLC3D, cell not stated2321Tb14.6Gb/mm2not published61600MT/snot publishednot publishednot publishedMicron 2022 releaseMicron 2022 product page
    176-stacked-WL 1Tb QLC (ISSCC 2022)SK hynixPaper2/2022QLC3D, cell not stated1761Tb14.8Gb/mm2not published4not published90µsnot published40MB/sISSCC 2022 paperISSCC 2025 paper
    8th-gen V-NAND 1Tb TLC (Toggle DDR 5.0)SamsungPaper2/2022TLC3D, cell not statednot published1Tbnot publishednot publishednot published2400MT/snot publishednot published164MB/sISSCC 2022 paperSamsung 2022 release
    BiCS6 1Tb QLC (162 WL layers, WD/Kioxia)Kioxia/WDPaper2/2022QLC3D, cell not stated1621Tb15Gb/mm268mm24not published65µsnot published60MB/sISSCC 2022 paper
    176-layer QLC (replacement gate) (density from a teardown, secondary source)MicronShipping1/2022QLC3D charge trap176not published14.9Gb/mm2, teardown figure, measured by TechInsightsnot publishednot published1600MT/snot publishednot publishednot publishedMicron 2022 releaseTechInsights 2023 teardown
    X3-9070 1Tb TLC (Xtacking 3.0; layer count, die area and density from a teardown, secondary source)YMTCProduct2022TLC3D, cell not stated232, teardown figure, measured by TechInsights1Tb15.03Gb/mm2, teardown figure, measured by TechInsights68.15mm2, teardown figure, measured by TechInsights62400MT/snot publishednot publishednot publishedYMTC 2022 product pageYMTC 2022 releaseTechInsights 2023 teardown
    144L FG 1Tb QLC (product interface speed from a review, secondary source)IntelPaper2/2021QLC3D floating gate1441Tb13.8Gb/mm274.03mm241200MT/s85µs1630µs40MB/sISSCC 2021 paperTom's Hardware 2021 review
    176L TLC 512Gb (4D PUC; die area from a teardown, secondary source)SK hynixPaper2/2021TLC3D, cell not stated176512Gb10.8Gb/mm246.5mm2, teardown figure, measured by TechInsights4not published50µsnot published168MB/sISSCC 2021 paperTechInsights 2023 teardown
    7th-gen V-NAND 512Gb TLC (CoP; density note cites a teardown, secondary source)SamsungPaper2/2021TLC3D, cell not stated176512Gb8.5Gb/mm2not published4not published40µsnot published184MB/sISSCC 2021 paperSamsung 2021 release
    ISSCC 2021 1Tb TLC 170+ WL layers, CuA, 4-planeKioxia/WDPaper2/2021TLC3D, cell not stated≥1701Tb10.4Gb/mm298mm24not published50µsnot published160MB/sISSCC 2021 paper
    XL-FLASH G1 128Gb SLC (96 WL layers)Kioxia/WDPaper1/2021SLC3D, cell not stated96128Gbnot published96.34mm216not published4µs75µsnot publishedIEEE JSSC 2021 paper
    128-layer 512Gb TLC (die B37R; teardown, secondary source)MicronAnnounced2021not published3D charge trap128, teardown figure, measured by TechInsights512Gb, teardown figure, measured by TechInsights7.76Gb/mm2, teardown figure, measured by TechInsights66.02mm2, teardown figure, measured by TechInsightsnot publishednot publishednot publishednot publishednot publishedTechInsights 2021 teardown
    176-layer TLC (capacity, die area and density from a teardown, secondary source)MicronShipping11/2020TLC3D charge trap176512Gb, teardown figure, measured by TechInsights10.27Gb/mm2, teardown figure, measured by TechInsights49.84mm2, teardown figure, measured by TechInsightsnot published1600MT/snot publishednot publishednot publishedMicron 2020 releaseTechInsights 2021 teardown
    96L FG 1Tb QLC (CuA; product interface speed from a review, secondary source)IntelPaper5/2020QLC3D floating gate961Tb8.9Gb/mm2114.6mm24800MT/s90µs2080µs30MB/sIMW 2020 paperISSCC 2021 paperTom's Hardware 2021 review
    92-stacked-WL 1Tb QLC (ISSCC 2020 paper 13.1)SamsungPaper2/2020QLC3D, cell not stated921Tb7.53Gb/mm2136mm22not published110µs2000µs18MB/sISSCC 2020 paper
    96L QLC 1Tb (PUC)SK hynixPaper2/2020QLC3D, cell not stated961Tb8.4Gb/mm2122mm24not published170µs2150µs30MB/sISSCC 2020 paperISSCC 2021 paper
    BiCS4 1.33Tb QLC (96 WL layers)Kioxia/WDPaper1/2020QLC3D, cell not stated961.33Tb8.5Gb/mm2158.4mm22not published160µs3380µs9.7MB/sIEEE JSSC 2020 paperISSCC 2021 paper
    BiCS5 112-layer 512Gb TLC (density from a teardown, secondary source)Kioxia/WDAnnounced1/2020TLC3D, cell not stated112512Gb7.08Gb/mm2, teardown figure, measured by TechInsightsnot publishednot publishednot publishednot publishednot publishednot publishedKioxia 2020 releaseTechInsights 2022 teardown
    X2-6070 128-layer QLC (Xtacking 2.0)YMTCProduct2020QLC3D charge trap1281.33Tbnot publishednot publishednot published1600MT/snot publishednot publishednot publishedYMTC 2020 releaseYMTC 2020 product page
    X2-9060 128-layer TLC (Xtacking 2.0; die area, density and planes from a teardown, secondary source)YMTCProduct2020TLC3D, cell not stated128512Gb8.47Gb/mm2, teardown figure, measured by TechInsights60.42mm2, teardown figure, measured by TechInsights4, teardown figure, measured by TechInsights1600MT/snot publishednot publishednot publishedYMTC 2020 releaseYMTC 2020 product pageTechInsights 2023 teardownTechInsights 2023 teardown
    64-layer 256Gb TLC (Xtacking) (die area, density and planes from a teardown, secondary source)YMTCMass production9/2019TLC3D, cell not stated64256Gb4.42Gb/mm2, teardown figure, measured by TechInsights57.96mm2, teardown figure, measured by TechInsights2, teardown figure, measured by TechInsightsnot publishednot publishednot publishednot publishedYMTC 2019 releaseTechInsights 2023 teardown
    128-layer 1Tb TLC 4D NANDSK hynixMass production6/2019TLC3D charge trap1281Tbnot publishednot published41400MT/snot publishednot publishednot publishedSK hynix 2019 release
    6th-gen V-NAND 512Gb TLC (product interface speed from a review, secondary source)SamsungPaper2/2019TLC3D, cell not stated≥120512Gb5Gb/mm2101.58mm221400MT/s45µsnot published82MB/sISSCC 2019 paperTom's Hardware 2021 reviewISSCC 2021 paper
    ISSCC 2019 512Gb TLC 128 WL layers, CuA, 4-planeKioxia/WDPaper2/2019TLC3D, cell not stated128512Gb7.8Gb/mm266mm24not published56µsnot published132MB/sISSCC 2019 paper
    96-layer 512Gb TLC 4D NAND (CTF and PUC) (density from a teardown, secondary source)SK hynixLaunched11/2018TLC3D charge trap96512Gb6.3Gb/mm2, teardown figure, measured by TechInsightsnot publishednot publishednot publishednot publishednot publishednot publishedSK hynix 2018 releaseTechInsights 2020 teardown
    5th-gen V-NAND 256Gb TLC (Toggle DDR 4.0)SamsungMass production7/2018TLC3D charge trap≥90256Gbnot publishednot publishednot published1400MT/s50µs500µsnot publishedSamsung 2018 release
    64-layer 1Tb QLC (Micron and Intel)MicronShipping5/2018QLC3D floating gate641Tbnot publishednot published4not publishednot publishednot publishednot publishedIntel/Micron 2018 release
    64-stacked-WL 1Tb QLC (ISSCC 2018)SamsungPaper2/2018QLC3D, cell not stated641Tb5.63Gb/mm2181.9mm22not published140µs3000µs12MB/sISSCC 2018 paperIEEE JSSC 2020 paperISSCC 2020 paper
    BiCS4 512Gb TLC (Toshiba Memory, 96 WL layers; product interface speed from a review, secondary source)Kioxia/WDPaper2/2018TLC3D, cell not stated96512Gb5.95Gb/mm286.13mm22800MT/s58µsnot published57MB/sISSCC 2018 paperIEEE JSSC 2020 paperIEEE JSSC 2021 paperTom's Hardware 2020 review
    BiCS 64-layer 768Gb QLC (Toshiba)Kioxia/WDAnnounced6/2017QLC3D, cell not stated64768Gbnot publishednot publishednot publishednot publishednot publishednot publishednot publishedToshiba 2017 release
    72-layer 256Gb TLC 3D NAND (density from a teardown, secondary source)SK hynixAnnounced4/2017TLC3D, cell not stated72256Gb3.55Gb/mm2, teardown figure, measured by TechInsightsnot publishednot publishednot publishednot publishednot publishednot publishedSK hynix 2017 releaseTechInsights 2018 teardown
    BiCS3 512Gb TLC (Toshiba/WD, 64 WL layers)Kioxia/WDPaper2/2017TLC3D, cell not stated64512Gb3.88Gb/mm2132mm22533MT/s64µsnot published46MB/sISSCC 2017 paperSean Webster 2022 measurement
    4th-gen V-NAND 512Gb TLC (64 WL)SamsungPaper8/2016TLC3D, cell not stated64512Gb3.98Gb/mm2128.5mm22800MT/s60µs700µs51MB/sIEEE JSSC 2018 paperSamsung 2016 releaseIEEE JSSC 2020 paper
    14nm 128Gb MLC planar NAND (ISSCC 2016 paper 7.5)SamsungPaper2/2016MLCPlanar, cell not statedPlanar128Gb0.98Gb/mm2, derived: capacity over the die size in the cited source130mm22not publishednot published640µs50MB/sISSCC 2016 paper
    768Gb 3b/cell 3D floating-gate NAND with CMOS under array (Micron and Intel, ISSCC 2016 paper 7.7)MicronPaper2/2016TLC3D floating gatenot published768Gb4.29Gb/mm2179.2mm24not publishednot publishednot published44MB/sISSCC 2016 paper
    3rd-gen V-NAND 256Gb TLC (48 WL)SamsungMass production8/2015TLC3D charge trap48256Gb2.6Gb/mm297.6mm22400MT/s45µs660µs53.3MB/sIEEE JSSC 2017 paperSamsung 2015 releaseComputerBase 2016 release
    BiCS 48-layer 256Gb TLC (Toshiba) (die area and density from a teardown, secondary source)Kioxia/WDAnnounced8/2015TLC3D, cell not stated48256Gb2.43Gb/mm2, derived: capacity over the die size in the cited source105.4mm2, teardown figure, measured by TechInsightsnot publishednot publishednot publishednot publishednot publishedToshiba 2015 releaseTechInsights 2018 teardown
    32-layer 256Gb MLC (Micron and Intel) (die area from a teardown, secondary source)MicronAnnounced3/2015MLC3D floating gate32256Gbnot published168.2mm2, teardown figure, measured by TechInsights4667MT/s77µs1300µsnot publishedIntel/Micron 2015 releaseTechInsights 2016 teardownMicron 2016 product page
    32-layer 384Gb TLC (Micron and Intel) (die area and density from a teardown, secondary source)MicronAnnounced3/2015TLC3D floating gate32384Gb2.28Gb/mm2, teardown figure, measured by TechInsights168.2mm2, teardown figure, measured by TechInsights4667MT/s100µs1630µsnot publishedIntel/Micron 2015 releaseTechInsights 2017 teardownMicron 2016 product page
    2nd-gen V-NAND 128Gb TLC (32 WL)SamsungPaper2/2015TLC3D, cell not stated32128Gb1.86Gb/mm268.9mm21400MT/s45µs700µs50MB/sIEEE JSSC 2016 paperISSCC 2015 paperComputerBase 2016 releaseIEEE JSSC 2018 paperIEEE JSSC 2020 paper
    15nm 64Gb MLC planar NAND (ISSCC 2015)Kioxia/WDPaper2015MLCPlanar, cell not statedPlanar64Gbnot published75mm2not publishednot publishednot publishednot publishednot publishedISSCC 2015 paperPC Watch 2015 release
    1st-gen V-NAND 128Gb MLC (24 WL) (die size and density from a Kioxia table, secondary source)SamsungMass production8/2013MLC3D charge trap24128Gb0.96Gb/mm2133mm22533MT/s49µs600µs50MB/sSamsung 2013 releaseIEEE JSSC 2015 paperSamsung 2014 product pageIEEE JSSC 2020 paper
    16nm 128Gb MLCMicronSampling7/2013MLCPlanar, cell not statedPlanar128Gbnot publishednot publishednot publishednot publishednot publishednot publishednot publishedMicron 2013 releaseISSCC 2014 paper
    16nm 64Gb MLC planar NAND (ISSCC 2014)SK hynixPaper2013MLCPlanar, cell not statedPlanar64Gb0.69Gb/mm2, derived: capacity over the die size in the cited source93.4mm22not publishednot publishednot publishednot publishedISSCC 2014 paperElectronics360 / EE Times 2013 release
    20nm 128Gb TLC planar NAND (ISSCC 2013) (die size and density from a Toshiba table, secondary source)MicronPaper2013TLCPlanar floating gatePlanar128Gb0.87Gb/mm2146.5mm2not publishednot published90µs2300µsnot publishedISSCC 2013 paperISSCC 2017 paperPC Watch 2013 release
    19nm 128Gb TLC planar NAND (ISSCC 2012)Kioxia/WDPaper2012TLCPlanar, cell not statedPlanar128Gb0.75Gb/mm2170.6mm2not publishednot publishednot publishednot published18MB/sISSCC 2012 paperISSCC 2017 paperPC Watch 2012 release
    19nm 64Gb MLC planar NAND (ISSCC 2012)Kioxia/WDPaper2012MLCPlanar, cell not statedPlanar64Gb0.57Gb/mm2, derived: capacity over the die size in the cited source112.8mm21not publishednot published1100µs15MB/sISSCC 2012 paperToshiba 2012 paper
    Sub-20nm 64Gb MLC planar NAND (ISSCC 2012)SamsungPaper2012MLCPlanar, cell not statedPlanar64Gbnot published109.5mm2not publishednot publishednot publishednot publishednot publishedISSCC 2012 paperPC Watch 2012 release
    20nm 128Gb MLC (Intel and Micron)MicronAnnounced12/2011MLCPlanar, cell not statedPlanar128Gbnot publishednot publishednot published333MT/snot publishednot publishednot publishedIntel/Micron 2011 release
    20nm 64Gb MLC (Intel and Micron)MicronAnnounced4/2011MLCPlanar, cell not statedPlanar64Gb0.54Gb/mm2, derived: capacity over the die size in the cited source118mm2not publishednot publishednot publishednot publishednot publishedIntel/Micron 2011 release
    20nm-class 64Gb TLC planar NAND (ISSCC 2011)SamsungPaper2/2011TLCPlanar, cell not statedPlanar64Gbnot publishednot publishednot publishednot publishednot publishednot published7MB/sISSCC 2011 paper
    26nm 32Gb MLC planar NAND (ISSCC 2011)SK hynixPaper2/2011MLCPlanar, cell not statedPlanar32Gbnot publishednot publishednot publishednot publishednot publishednot publishednot publishedISSCC 2011 paper
    24nm 64Gb MLC planar NAND (ISSCC 2011)Kioxia/WDPaper2011MLCPlanar, cell not statedPlanar64Gb0.42Gb/mm2, derived: capacity over the die size in the cited source151mm22not publishednot publishednot publishednot publishedISSCC 2011 paperToshiba 2011 paper
    25nm 64Gb MLC (Intel and Micron)MicronAnnounced2/2010MLCPlanar, cell not statedPlanar64Gb0.38Gb/mm2, derived: capacity over the die size in the cited source167mm2not publishednot publishednot publishednot publishednot publishedIntel/Micron 2010 release
    32nm 32Gb MLC planar NAND (ISSCC 2010)SamsungPaper2/2010MLCPlanar, cell not statedPlanar32Gb0.2Gb/mm2, derived: capacity over the die size in the cited source159mm2not publishednot publishednot publishednot published12MB/sISSCC 2010 paper
    32nm 32Gb MLC planar NAND (Lee et al., ISSCC 2010)SK hynixPaper2/2010MLCPlanar floating gatePlanar32Gb0.22Gb/mm2, derived: capacity over the die size in the cited source146mm2not publishednot publishednot publishednot published13MB/sISSCC 2010 paper
    34nm 32Gb TLC planar NAND (Intel and Micron, ISSCC 2010)MicronPaper2/2010TLCPlanar, cell not statedPlanar32Gbnot published126mm24not published60µs2000µs6MB/sISSCC 2010 paper
    Sub-35nm 32Gb TLC planar NAND (ISSCC 2009)Kioxia/WDPaper2/2009TLCPlanar, cell not statedPlanar32Gb0.28Gb/mm2, derived: capacity over the die size in the cited source112.86mm22not publishednot publishednot publishednot publishedISSCC 2009 paper
    43nm 64Gb 4b/cell planar NAND (ISSCC 2009)Kioxia/WDPaper2009QLCPlanar, cell not statedPlanar64Gbnot published244.45mm2not publishednot publishednot publishednot published5.6MB/sISSCC 2009 paperPC Watch 2009 releaseEE Times 2009 release
    48nm 32Gb TLC planar NAND (ISSCC 2009)SK hynixPaper2009TLCPlanar, cell not statedPlanar32Gbnot published201mm22not publishednot publishednot published5.5MB/sISSCC 2009 paperISSCC / IEEE 2009 paper
    34nm 32Gb MLC (Intel and Micron)MicronAnnounced5/2008MLCPlanar, cell not statedPlanar32Gb0.19Gb/mm2, derived: capacity over the die size in the cited source172mm2not publishednot published50µs900µs9MB/sIntel/Micron 2008 releaseISSCC 2009 paper
    43nm 16Gb MLC planar NAND (ISSCC 2008)Kioxia/WDPaper2/2008MLCPlanar, cell not statedPlanar16Gb0.13Gb/mm2, derived: capacity over the die size in the cited source120mm2not publishednot publishednot publishednot publishednot publishedISSCC 2008 paper
    45nm 4Gb MLC double-stacked NAND, two planar layers (ISSCC 2008)SamsungPaper2008MLCStacked planar floating gate2 planar4Gbnot publishednot publishednot publishednot publishednot publishednot publishednot publishedISSCC 2008 paperUniversity of Seoul research portal 2008 paper
    50nm 8Gb DDR-interface NAND (Intel and Micron, ISSCC 2008)MicronPaper2008SLCPlanar, cell not statedPlanar8Gbnot publishednot published4not published30µsnot published100MB/sISSCC 2008 paperPC Watch 2008 release
    56nm 16Gb MLC all-bitline NAND (ISSCC 2008)Kioxia/WDPaper2008MLCPlanar, cell not statedPlanar16Gbnot published182mm22not publishednot publishednot published34MB/sISSCC 2008 paperSanDisk 2008 paper
    56nm 16Gb TLC planar NAND (Li et al., ISSCC 2008)Kioxia/WDPaper2008TLCPlanar, cell not statedPlanar16Gb0.11Gb/mm2142.5mm2not publishednot publishednot publishednot published8MB/sISSCC 2008 paperSanDisk 2008 paper
    70nm 16Gb 4b/cell planar NAND (VLSI 2007)Kioxia/WDPaper2007QLCPlanar, cell not statedPlanar16Gbnot published168mm2not publishednot publishednot publishednot published0.62MB/sVLSI Circuits 2007 paperSolid State Technology 2007 release
    50nm 4Gb (Intel and Micron)MicronSampling7/2006not publishedPlanar, cell not statedPlanar4Gbnot publishednot publishednot publishednot publishednot publishednot publishednot publishedIntel/Micron 2006 release
    56nm 8Gb MLC planar NAND (ISSCC 2006)Kioxia/WDPaper2/2006MLCPlanar, cell not statedPlanar8Gb0.079Gb/mm298.8mm22not publishednot publishednot published10MB/sISSCC 2006 paperISSCC 2008 paperSanDisk 2008 paper
    70nm 8Gb MLC planar NAND (JSSC 2006)Kioxia/WDPaper2005MLCPlanar, cell not statedPlanar8Gb0.055Gb/mm2, derived: capacity over the die size in the cited source146mm22not publishednot publishednot published6MB/sIEEE JSSC 2006 paperToshiba 2005 product page
    90nm 2Gb planar NAND (JSSC 2003)SamsungPaper11/2003not publishedPlanar, cell not statedPlanar2Gb0.014Gb/mm2, derived: capacity over the die size in the cited source141mm2not publishednot publishednot publishednot publishednot publishedIEEE JSSC 2003 paper
    120nm 1Gb planar NAND (Lee et al., JSSC 2002)SamsungPaper11/2002not publishedPlanar, cell not statedPlanar1Gb0.0077Gb/mm2, derived: capacity over the die size in the cited source129.6mm2not publishednot publishednot publishednot published7MB/sIEEE JSSC 2002 paper
    130nm 1Gb planar NAND (JSSC 2002)Kioxia/WDPaper11/2002not publishedPlanar, cell not statedPlanar1Gb0.008Gb/mm2, derived: capacity over the die size in the cited source125mm2not publishednot publishednot publishednot published10.6MB/sIEEE JSSC 2002 paper

    Each value links to the paper or page it was read from. Chip-level results from a paper are one sample die, not a product.

    Download the dies and their sources: CSV or JSON. Each row is one sourced value with the source it was read from, and the D and T marks as columns.

    Interface standards behind the dashed line

    StandardRevisionPublishedMaximumSource
    ONFI6.01/20264800MT/sOpen NAND Flash Interface Specification Revision 6.0
    Toggle (vendor announcement)6.02/20254800MT/sKioxia and Sandisk Unveil 3D Flash Technology Achieving 4.8Gb/s NAND Interface Speed, Toggle DDR6.0 (ISSCC, 19 Feb 2025)
    JESD230JESD230G11/20244800MT/sJEDEC Announces Enhanced NAND Flash Interface Standard (JESD230G press release, 18 Nov 2024)
    ONFI5.210/20243600MT/sOpen NAND Flash Interface Specification Revision 5.2
    Toggle (vendor announcement)5.14/20243200MT/sSamsung 9th-gen V-NAND mass production, Toggle 5.1 (23 Apr 2024)
    Toggle (vendor announcement)5.011/20222400MT/sSamsung 8th-gen V-NAND mass production, Toggle DDR 5.0, editor note listing Toggle generations (Nov 2022)
    ONFI5.18/20223600MT/sOpen NAND Flash Interface Specification Revision 5.1
    ONFI5.05/20212400MT/sOpen NAND Flash Interface Specification Revision 5.0
    ONFI4.22/20201600MT/sOpen NAND Flash Interface Specification Revision 4.2
    JESD230JESD230D10/20191200MT/sJEDEC JESD230D NAND Flash Interface Interoperability (Oct 2019, hosted on onfi.org)
    Toggle (vendor announcement)4.07/20181200MT/sSamsung 8th-gen V-NAND mass production, Toggle DDR 5.0, editor note listing Toggle generations (Nov 2022)
    ONFI4.112/20171200MT/sOpen NAND Flash Interface Specification Revision 4.1
    JESD230JESD230C11/2016400MT/sJEDEC JESD230C NAND Flash Interface Interoperability (Nov 2016, hosted on onfi.org)
    JESD230JESD230B7/2014400MT/sJEDEC JESD230B NAND Flash Interface Interoperability (Jul 2014, hosted on onfi.org)
    ONFI4.04/2014800MT/sOpen NAND Flash Interface Specification Revision 4.0
    ONFI3.26/2013533MT/sOpen NAND Flash Interface Specification Revision 3.2
    JESD230JESD23011/2012400MT/sJEDEC Announces Enhanced NAND Flash Interface Standard (JESD230G press release, 18 Nov 2024)
    ONFI3.110/2012400MT/sOpen NAND Flash Interface Specification Revision 3.1
    ONFI2.310/2011200MT/sOpen NAND Flash Interface Specification Revision 2.3a
    ONFI3.03/2011400MT/sOpen NAND Flash Interface Specification Revision 3.0
    Toggle (vendor announcement)2.07/2010400MT/sSamsung and Toshiba to Support New Standardized NAND Specification (press release, 22 Jul 2010)
    ONFI2.210/2009200MT/sOpen NAND Flash Interface Specification Revision 2.2
    ONFI2.11/2009200MT/sOpen NAND Flash Interface Specification Revision 2.1
    ONFI2.02/2008133MT/sOpen NAND Flash Interface Specification Revision 2.0
    ONFI1.012/200650MT/sOpen NAND Flash Interface Specification Revision 1.0
    Toggle (vendor announcement)1.0not dated133MT/sSamsung and Toshiba to Support New Standardized NAND Specification (press release, 22 Jul 2010)
    Toggle (vendor announcement)3.0not dated800MT/sSamsung 8th-gen V-NAND mass production, Toggle DDR 5.0, editor note listing Toggle generations (Nov 2022)

    ONFI and JESD230 rows draw the line. Toggle generations are announcements by Samsung, Toshiba, Kioxia and Sandisk, some without a date, so they are listed but not drawn. Some older rates are worked out from the standard’s timing tables rather than stated as MT/s; the source for each row says which.

    What controllers could drive

    The dotted line on the I/O chart is the fastest NAND speed a public controller brief listed by its date. The controllers behind it, the host links they ran, the drives measured on a test bench and the NAND speeds stated in reviews are on the Controller Timeline. ISSCC, IEDM and the VLSI Symposium, where circuit and device papers on these dies are published, are on the events calendar.

    The guides behind this data

    The other timelines