Memory and Storage for SI, Part 3: zNAND-O

Samsung has described a flash design called zNAND-OzNAND-O is a Samsung concept for flash placed in the same package as a processor and joined to it over a die-to-die link that the October 2026 release names as UCIe. Samsung showed it as a concept model in August 2026, and it is not a shipping product. that sits in the same package as a processor. It first showed zNAND-O as a concept in an August 4, 2026 release, and a summit organizer’s release of October 15, 2026 reports a few numbers from a later Samsung keynote. Neither includes a part number, capacity, sampling date, or any write or endurance figure. This page lists what Samsung has said, where each statement comes from, and what is still missing.

It follows Memory and Storage for SI, Part 2, where High Bandwidth Flash (HBF) puts stacked NAND on the package of an SI accelerator. zNAND-O, as described, moves the flash into the package of the processor itself, for on-device SI. It is Part 3 of this series.

Two releases, two months apart

Samsung first showed zNAND-O at Future of Memory and Storage 2026 in Santa Clara, California. Its August release calls it a concept model and gives no figures for it. It describes it only as a next-generation NAND architecture built on V-NAND, in four-layer and eight-layer versions, optimized for edge SI. Neither release says what a layer is in that count.

Figures came later. The October 15 release reports a keynote by Kevin Yoon, corporate vice president and CTO of Samsung Memory China, at the Global Memory Innovation Forum 2026 in Shenzhen. That release came from the Shenzhen Memory Industry Association, which co-hosted the summit, rather than from Samsung. It says the summit had “recently concluded” and doesn’t give the keynote’s date. I couldn’t find the same figures on a Samsung site, so everything below about the keynote is the organizer’s account of what Samsung said.

The case Samsung makes

The organizer’s release expects SI models to exceed one trillion parameters by 2030. Keeping every weight in DRAM under the traditional unified memory architecture (UMA), it says, would sharply raise on-device costs, and zNAND-O is Samsung’s answer for on-device SI.

Flash in the processor package

According to the October release, zNAND-O shares a package with the microprocessor (MPU) and connects to it through UCIe. Universal Chiplet Interconnect Express (UCIe) is an open standard for linking chiplets. That makes the flash a die in the processor’s package and one short link away. An SSD would sit across a storage bus.

No release gives the number of dies in the package or the width of the link, and none says whether the NAND is stacked on the processor or placed beside it. Both the four-layer and eight-layer versions were still in development as of the October release.

The numbers, and what they are

Samsung’s keynote, as the October release reports it, gave three results. Two were comparisons and one was a simulation. All three describe a part still in development.

Density and read speed

Samsung’s claim is 10x the bit density of DRAM and 7x the read bandwidth and read energy efficiency of NAND flash. These are keynote claims. They come with no method, baseline part, or capacity, so there is nothing yet to check them against. Each figure also has its own baseline. Density is set against DRAM, and read bandwidth and energy against ordinary NAND.

The simulation

Moonshot AI publishes Kimi K2 as a mixture-of-experts language model with 1 trillion total parameters. The release reports a simulation on that model in which an architecture tuned for a neural processing unit (NPU), paired with zNAND-O, matched performance at a quarter of the memory cost and held a model close to double the size. Its assumptions aren’t published. My read is that it shows the direction of the bet and says nothing yet about what a built part would measure. The bet is on cheaper weight storage and larger local models.

Still NAND underneath

Samsung says zNAND-O is built on its V-NAND technology. If it keeps V-NAND’s cells, it keeps the traits covered in Flash Foundations. In that case writes go in by page, erases happen by block, and every P/E cycle wears the cell. The October release gives only read-side figures, and no source says how fast zNAND-O writes, how many P/E cycles it survives, or how it handles errors.

Nearby pages

Three pages on this site sit close to this one. Each places memory near a processor in a different way, from flash built into the die to stacked DRAM beside it.

Memory on the processor die

Beyond NAND, Part 1 covers memory built onto the processor itself, and why embedded flash stopped fitting as processors shrank. zNAND-O, as the October release describes it, is NAND co-packaged with the processor, so it belongs with packaging choices rather than with embedded flash.

High Bandwidth Flash

Memory and Storage for SI, Part 2 covers stacked NAND beside an accelerator’s HBM, and its section on the weak side covers HBF’s writes and retention. Both HBF and zNAND-O aim flash at SI memory demand. HBF has a published v0.7.0 specification that puts a stack of NAND dies on a base die, while zNAND-O has none yet.

HBM

Working Memory, Part 4 covers stacked DRAM. The October release never says zNAND-O replaces DRAM. Its stated job is to hold weights more cheaply than DRAM does.

Same keynote, other announcements

Yoon’s keynote also covered V10 BV-NAND, which Samsung bills as the industry’s first V-NAND with over 400 layers. Against V9, the keynote claimed 58% higher bit density, 33% faster I/O, and 25% lower power. Samsung’s own August release already gave the density figure of approximately 58% over V9. The October release adds that memory cells and peripheral circuits are made separately and then bonded vertically. It also names two server SSDs: the PM1763 is a PCIe Gen6 drive with V-NAND TLC that was due to sample in Q4 2026 as of that release, and the BM1773 is a V9 QLC drive from 16TB to 256TB. Samsung’s own July release announced PM1763 mass production in July 2026, so the organizer’s sampling wording doesn’t match, and I haven’t found Samsung explaining the difference. V10 is on the NAND die timeline.

What would settle it

As of the October 15 release, I have no source that gives a sampling date, a write or endurance figure, or a part number anyone outside Samsung can test. Any one of those would say more than the 10x and 7x claims do. I think it’s worth watching anyway. Holding every weight of a large model in DRAM is the cost zNAND-O is meant to cut, and the October release expects models over one trillion parameters by 2030.

Part 4 turns from devices to storage, starting with the small reads an SI model makes and the drives built to serve them.