Memory technology · Lab

Crosspoint Lab

A crossbar packs a memory cell into every crossing of two wires. It is the densest way to wire a memory, and you cannot read one cell without the others getting involved. Read one, watch the current that sneaks around it, then try the fixes.

Start the walkthrough Skip to the bench How it works Sources and method

The walkthrough

From one cell to a solved equation

Six sections, one array. Each section draws the same array again with its own setups, and every setup is written out beside the picture. Press one to change what the array shows, and drag a slider to change the setup itself.

Read one cell, then more

A cell is read by putting the read voltage across it and measuring the current. Add neighbors and the current finds other routes.

A low-resistance cell passes a lot of current at the read voltage.
A high-resistance cell passes very little. The gap between the two reads is the signal, and alone it is almost the whole current.
Current can run along a neighbor, back through the other row and forward through a third cell. That sneak path swamps a high-resistance target.
A low-resistance target with high-resistance neighbors has almost nothing sneaking in beside it. The margin compares these two worst cases.
Every extra row and column adds sneak routes while the signal stays the same size. About a fifth of the signal is left.
The worst-case high read now draws more than the worst-case low read, so no threshold separates them.
The cells you never selected carry most of the current. The margin shows 0% from 4 by 4 on.
This is true for a bare array with floating lines whatever the ratio of high to low resistance.

Hold the idle lines

A driver can hold every line that is not being read at a fixed bias instead of leaving it floating. That sets the voltage idle cells see, which matters most when you write.

Floating lines leave the sneak current unchecked.
Idle lines sit halfway between the read voltage and ground. The margin still shows 0%, because low-resistance cells on the sensed line still feed it.
Idle rows sit a third of the way up and idle columns two thirds. This uses the most power, because the most cells conduct.
The 2(n-1) idle cells on the selected lines sit at half the write voltage. Drag the wire resistance to see the selected cell lose voltage.
Every other cell sits at a third of the write voltage. Both schemes make the voltage predictable, and neither makes it zero.

Block the idle cells

The cure is a part in each cell that stops the idle ones from conducting.

With V/2 and nothing else, the margin is still 0% at this size.
A selector is nearly an open circuit below its threshold, so half-selected cells stay off. The margin comes back to the single-cell value.
Only the selected row's transistors are on. The selected row's other cells still sit at half voltage.

Rows in, columns out

Store a number in each cell as its conductance, put a voltage on every word line, and every bit line adds up its cells' currents. One read does every multiplication and addition at once.

Each column delivers the weighted sum of the inputs.
Eight sums arrive in one read. The solid bars sit on the outlines.
Wire resistance drops voltage along every line, so cells far from the drivers see less than their input and columns read low.
A stuck cell spoils its own column.
Cell-to-cell variation nudges every weight, some up and some down.
More wire resistance, more error.
The error grows with the square of the side.

Signs and repairs

A cell's conductance is never negative, so a signed weight is stored as a difference. Damage can then be partly worked around.

Two cells on neighboring bit lines, set symmetrically around the middle of the range, with their currents subtracted.
One cell per weight against a reference column every weight shares.
The two cells of a pair sit side by side and share what the wires do to them.
A far reference column does not share the drop, so the pair does better once wires are resistive.
Wire resistance hurts most where a lot of current runs a long way.
Reordering the rows moves the weights with them, so the ideal sums do not change and the worst column error falls.
In a measured tantalum-oxide crossbar, 10.1% of the cells were stuck.
A stuck cell's partner is reprogrammed to make up the difference. Some pairs come back exactly right and the rest only get closer.

Solve Ax = b in one step

Put an amplifier on every word line and feed its output back to the bit line with the same number. The circuit settles where the currents cancel, and the output voltages are the answer.

The input currents of a published 3 by 3 experiment, on a teaching matrix. Positive conductances can still give a negative answer, drawn below the zero line.
Only the inputs change, which gives a different answer without rewriting a cell.
The answer exists on paper, but the feedback is not negative and the circuit never reaches it.
A larger system with ideal wires, exact conductances and an ideal amplifier.
Wire resistance takes a voltage drop along every line.
The array holds a slightly different matrix, so it solves the wrong equations exactly.

The bench

Try any array

Choose a size, a cell type, how the idle lines are held and the state of the cell you read. The circuit is solved again each time, and the chart shows the read margin at every size.

Array size Cell typeIdle linesCell being read

How it works

In a crossbar a cell sits between a word line and a bit line. Every point where a wire crosses a cell is a node. Wire segments, cells and line drivers are conductances, and Kirchhoff's current law at each node gives a set of equations. The lab solves that circuit exactly. A selector is solved in a loop: it turns on once the voltage across its cell passes a threshold and off again below a lower holding voltage, until no selector changes.

A cell in the low-resistance state passes a lot of current and one in the high-resistance state passes little. Their on/off ratio sets the read. Other cells give the current a sneak path. The margin compares two worst cases for the selected cell, farthest from the drivers. A high-resistance cell is read with every other cell low-resistance, which sends the most sneak current into the sense line. A low-resistance cell is read with every other cell high-resistance, which sends the least. The margin is shown as 0% when the high read draws more, because then the array can misread. A driver can hold idle lines at a fixed bias, so each half-selected cell sees a predictable voltage. Too much voltage on an idle cell can cause write disturb.

The squares show the current through each cell, or the voltage across it for a write, or the weight stored in it. The bars show what comes out. The solver in the last section is a different network: an operational amplifier on every word line holds it at a virtual ground and feeds back to the bit line. It is solved by dense elimination, with an amplifier of finite gain on every row. The error grows with the condition number of the matrix.

A resistive memory cell is a thin layer between two electrodes whose resistance can be switched. A filament forms at set and breaks at reset. In a valence-change cell oxygen vacancies move, and in an electrochemical metallization cell a metal bridge grows. A fresh cell often needs a one-time forming pulse, and its compliance current helps decide how low its resistance ends up. Most resistive cells are bipolar. A phase-change cell is unipolar: a moderate pulse crystallizes it, and a taller, shorter pulse melts it and freezes it amorphous. Its programming curve is drawn through values read off published curves for two cells, with pulses of 100 to 150ns. A glassy cell conducts only after threshold switching. Its high resistance also drifts upward after it is written, with an exponent near 0.1, so every sum reads low as the weights age. Projected phase-change memory gives the read current a path around the drifting region. A multi-level cell suffers most from drift, and random telegraph noise makes a cell's current flicker, which this lab does not model. Beyond NAND, Part 5 covers how resistive cells form, switch and vary, and Part 1 says where each cell type stands.

A selector is a threshold switch, and a transistor does the job by logic. Set the selector's threshold between half the read voltage and the whole read voltage, and the half-selected cells stay off. Scale sets how good it must be: on a 2,000 by 2,000 tile there are four million idle cells, and to stay under one 100µA program current each must leak under 25pA. For a diode type, the nonlinearity alpha must exceed (n-1) squared, and for a symmetric nonlinear selector (n-1) over 2. At 16 by 16 that is 225 and 7.5, and at 1,024 by 1,024 about a million and 512. With V/2 and an ovonic threshold switch, the median set threshold must exceed the 1.2V window plus four standard deviations of the reset spread plus eight of the set spread. A self-rectifying cell skips the separate part. A complementary resistive switch makes the array's resistance independent of what is stored, at the price of a read that destroys the value. A diode in each cell reverse-biases nearly every idle cell when writing: about n squared block, 2n carry a small bias and one is forward-biased.

A bare crossing is 4F², lines every 2F in both directions. Stacking decks of crossings halves the area per bit with each doubling, but each deck repeats its cell and selector layers, so cost per bit falls more slowly. A vertical design needs about one critical mask whatever the number of layers.

Computing uses the same array. Each cell stores a conductance, with a dynamic range of 100 here, and every column adds a weighted sum. Each cell is one multiply-accumulate, done where the weights are stored, which avoids the von Neumann trip. The converters at the edges are the catch: in one published design the 8-bit converters took 58% of the power and 31% of the area of each tile. A stuck cell spoils its column, variation nudges every weight, and line resistance lowers the voltage cells far from the drivers see. A differential pair holds a signed weight, and bit slicing spreads a weight over several cells. To keep the drop along a line inside a tenth of the input, a cell must be at least about ten times the side of the array times the line's total resistance. Published reviews ask a weight cell for about a hundredfold range, at least 32 distinguishable levels, under 10fJ per switch and retention of ten years or more. They are teaching targets and do not agree on every number. Write-verify trims write noise at a cost in time and energy.

The feedback circuit also fits a line to data, and a published six-point experiment came within 4.9% on the intercept and 0.8% on the slope. A content-addressable memory built from memristors stores a range in each cell and reports a row as a match when every input falls inside its cell's range.

What it leaves out

Every value is a teaching value: cells of 10kΩ and 1MΩ, 2Ω of wire between crossings and in each driver, a 2V read, a selector that turns on at 1.5V and holds above 1V, and a transistor of 1kΩ.
Real devices are nonlinear in ways this lab does not model.
It leaves out capacitance and read time, noise and heat.
Writing appears only as the voltage each cell sees, not as a cell that switches. Whether a cell at that voltage is disturbed depends on how switching voltages vary, which the lab does not model.
The cell physics, the programming curve, the selector thresholds and the decks are described in words here and were drawn in earlier versions of this page. Their model code and tests remain, and the sources and method keep their numbers.
Drift and cell-to-cell variation appear only in the sections on arithmetic, and the drift exponent is a value for one test cell and one material.
It reads one cell at a time against two fixed backgrounds, which are the harshest cases for each read. A real array holds a mix, and the margin is better.
The solver uses a 3 by 3 and an 8 by 8 matrix chosen by hand, with input currents chosen to keep the outputs near a volt. It leaves out the amplifier's output limit, offsets, noise and settling time.
Read the shapes and the trade-offs, not the digits.

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