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    Timelines · Sourced data

    Standards

    The standards that decide how storage and memory connect to a computer, in eight areas. Each area has its history, from the first spec to the newest sample or shipping part, the headline speed by year, and the documents its bodies have published, every row from the body that wrote it or the maker that built it.

    The eight areas What it will not tell you All Timelines

    How to read it

    A drive or a memory module is only as fast as the link between it and the processor, and that link is a written standard. The page holds 143 rows from 107 public sources. Most are one step of one standard: the spec published, a sample, or a first shipping part, drawn on a lane for its family. 45 are documents a standards body published in 2026, linked to the body’s own page. Context rows, such as an update or the newest revision, are drawn as hollow squares because they are not firsts. Where a maker claims a first, the row says it is the maker’s claim.

    A date is as exact as its source: a day, a month or only a year. Speeds are the headline rate each source prints. GT/s is gigatransfers per second on one lane or pin, MT/s is megatransfers per second, and Gb/s is gigabits per second, and these standards count a transfer as one bit on one wire, so the three agree number for number. USB and Thunderbolt quote the total for the whole link, so they get their own chart in plain Gb/s. Real throughput is lower once encoding and protocol overhead are taken off.

    NAND flash interface30 rows

    How a controller talks to NAND: ONFI, Toggle and JEDEC’s JESD230, and the fastest speed each revision allows. The NAND Die Timeline draws the same speeds as its dashed line.

    200020052010201520202025NAND interfaceFebruary 27, 2008: ONFI, ONFI 2.0March 2011: ONFI, ONFI 3.0April 2014: ONFI, ONFI 4.0, with the NV-DDR3 interface at 1.2 VFebruary 2020: ONFI, ONFI 4.2May 2021: ONFI, ONFI 5.0, with the new NV-LPDDR4 interfaceAugust 2022: ONFI, ONFI 5.1November 7, 2022: Samsung, Samsung 8th-generation V-NAND, on Toggle DDR 5.0April 23, 2024: Samsung, Samsung 9th-generation V-NAND, on Toggle 5.1November 18, 2024: JEDEC, JESD230G NAND interface standardJanuary 2026: ONFI, ONFI 6.0, legacy interfaces dropped

    Swipe the timeline sideways to reach the years since 2015.

    • Spec published
    • Sample
    • Shipping
    • Context, not a first
    Each marker is one milestone. Hover or tap a marker for its date and maker; it links to its row in the table.

    Interface speed (MT/s)

    • ONFI
    • JESD230
    • Toggle
    01,2502,5003,7505,00020142016201820202022202420262014: ONFI 4.0, with the NV-DDR3 interface at 1.2 V, 800 MT/s8002020: ONFI 4.2, 1,600 MT/s1,6002021: ONFI 5.0, with the new NV-LPDDR4 interface, 2,400 MT/s2,4002022: ONFI 5.1, 3,600 MT/s3,6002026: ONFI 6.0, legacy interfaces dropped, 4,800 MT/s4,8002024: JESD230G NAND interface standard, 4,800 MT/s2022: Samsung 8th-generation V-NAND, on Toggle DDR 5.0, 2,400 MT/s2,4002024: Samsung 9th-generation V-NAND, on Toggle 5.1, 3,200 MT/s3,200
    MT/s, linear scale. Each point is the headline rate its own source prints for that spec or part.

    StandardWhoStageMeasureHeadline speedDateSourceNote
    JESD230G.02 NAND flash interface interoperability (with ONFI)JEDECPublishedSeptember 2026JEDEC pageNAND interface standard developed by JEDEC and ONFI. JEDEC's catalog page does not say what changed from JESD230G, so no speed is shown.
    ONFI 6.0, legacy interfaces droppedONFISpec published4,800 MT/s4,800 MT/sJanuary 2026ONFI 2026
    Toggle 6.0ToggleSpec published4,800 MT/s4,800 MT/s, fastest modeFebruary 2025Sandisk/Kioxia 2025Kioxia/Sandisk ISSCC release (19 Feb 2025): 4.8 Gb/s interface using 'Toggle DDR6.0'. Sandisk BiCS10 sampling release (2 Jul 2026) repeats 'up to 4.8Gb/s' with Toggle DDR6.0. Date is the vendor announcement; JEDEC JESD230G (Nov 2024) already defines 4800 MT/s, but no page opened says JESD230G is Toggle 6.0, so the link is unproven. The 4.8 figure is a vendor-achieved rate; the defined maximum of Toggle 6.0 is not stated on those pages.
    JESD230G NAND interface standardJEDECSpec published4,800 MT/s (first version: 400)4,800 MT/sNovember 18, 2024JEDEC 2024
    ONFI 5.2ONFISpec published3,600 MT/s3,600 MT/s, fastest modeOctober 2024ONFI 2024Table 4-1: NV-DDR3 / NV-LPDDR4 Maximum Speed 3600 MT/s (no speed increase; adds the SCA protocol). Specs page: 'Published in Oct of 2024', spec file dated Oct. 3, 2024; PDF cover reads 27 February 2024 (document revision date versus posting date). Defined maximum.
    Samsung 9th-generation V-NAND, on Toggle 5.1SamsungFirst shipping (maker’s claim)3.2 Gb/s3,200 MT/sApril 23, 2024Samsung 2024Samsung’s own claim of an industry first for the 9th generation.
    Toggle 5.1ToggleSpec published3,200 MT/s3,200 MT/s, fastest modeApril 2024Samsung 2024Samsung 9th-gen V-NAND release, 23 Apr 2024: 'Toggle 5.1 ... up to 3.2 Gbps'. Korean version footnote lists Toggle DDR 5.1 = 3.2Gbps. Date is first-product announcement.
    Samsung 8th-generation V-NAND, on Toggle DDR 5.0SamsungShipping (not claimed first)2.4 Gb/s2,400 MT/sNovember 7, 2022Samsung 2022A context row: Samsung does not claim this was the first Toggle DDR 5.0 part.
    Toggle 5.0ToggleSpec published2,400 MT/s2,400 MT/s, fastest modeNovember 2022Samsung 2022Samsung 8th-gen V-NAND release (Nov 2022): 'Toggle DDR 5.0 interface ... the latest NAND flash standard', I/O up to 2.4 Gbps; editor note lists 5.0 = 2,400Mbps. Date is first-product announcement (page dated 6 Nov US, 7 Nov global).
    ONFI 5.1ONFISpec published3,600 MT/s3,600 MT/sAugust 2022ONFI 2026
    ONFI 5.0, with the new NV-LPDDR4 interfaceONFISpec published2,400 MT/s2,400 MT/sMay 2021ONFI 2026
    ONFI 4.2ONFISpec published1,600 MT/s1,600 MT/sFebruary 2020ONFI 2026
    JESD230DJEDECSpec published1,200 MT/s1,200 MT/s, fastest modeOctober 2019JEDEC 2019Bytes 146-147 Toggle Mode DDR2 and NV-DDR2: fastest 2.5 ns (400 MHz) = 800 MT/s. Bytes 172-173 'Toggle Mode DDR3/4 and NV-DDR3': fastest bit 12 = 1.667 ns (~600 MHz) = 1200 MT/s (derived). ONFI page date Oct. 21, 2019; the PDF download watermark and JESD230F's change list say June 2019 (conflict). Defined maximum.
    Toggle 4.0ToggleSpec published1,200 MT/s1,200 MT/s, fastest modeJuly 2018Samsung 2022Rate: Samsung editor note lists 4.0 = 1,200Mbps. Date: Samsung press release of 10 Jul 2018 claims 'the industry's first use of the Toggle DDR 4.0 interface' on 5th-gen V-NAND and states 1.4 Gbps for that product. 1.4 is Samsung's product speed, above its own 1,200 definition, so 1200 is used as the standard figure. The date is a first-use announcement, not the spec publication date. Samsung's VLSI 2020 F-chip paper (Table 1, with its earlier F-chip as prior work) lists 1.333 Gb/s/pin for Toggle 3.0 and 1.8 Gb/s/pin for Toggle 4.0. Those are retimed multi-chip-package rates through a buffer chip, not the per-die standard rate, so max_mts stays.
    ONFI 4.1ONFISpec published1,200 MT/s1,200 MT/s, fastest modeDecember 2017ONFI 2017Table 26: NV-DDR3 Maximum Speed 1200 MT/s. Specs page: 'Published in December of 2017 ... NV-DDR3 I/O speeds to 1066 MT/s and 1200 MT/s'; spec dated Dec. 12, 2017. Defined maximum.
    JESD230CJEDECSpec published400 MT/s400 MT/s, fastest modeNovember 2016JEDEC 2016Bytes 146-147 Toggle Mode DDR and NV-DDR2 speed grade, fastest bit 7 = 5 ns (200 MHz) = 400 MT/s (derived). ONFI page: 'published November 2016'. JESD230F's own change list calls it October 2016 (conflict, month unsettled). Defined maximum.
    JESD230BJEDECSpec published400 MT/s400 MT/s, fastest modeJuly 2014JEDEC 2014Parameter page bytes 146-147 'Toggle Mode DDR and NV-DDR2 speed grade': fastest is bit 7, 5 ns (200 MHz) = 400 MT/s (derived, 2 / 5 ns). ONFI page: 'published July 2014'. This is the JEDEC speed-grade ceiling, below ONFI 3.2 (533) and 4.0 (800) at the time. Defined maximum.
    ONFI 4.0, with the NV-DDR3 interface at 1.2 VONFISpec published800 MT/s800 MT/sApril 2014ONFI 2026
    ONFI 3.2ONFISpec published533 MT/s533 MT/s, fastest modeJune 2013ONFI 2013Table 22: SDR 200 MT/s, NV-DDR2 533 MT/s. Specs page: 'Published in June of 2013 ... scales NV-DDR2 I/O speed to 533 MT/s'; spec dated June 13, 2013. Defined maximum.
    JESD230JEDECSpec published400 MT/s400 MT/s, fastest modeNovember 2012JEDEC 2024Date: JEDEC/ONFI joint press release dated 6 Nov 2012 (ONFI page: 'Nov. 1, 2012', 'published October 2012'). That 2012 release describes a package/pinout-focused document and states no speed. The 400 MT/s figure is JEDEC's own 2024 statement 'compared to 400 MT/s in the first version of JESD230 published in 2011', which also gives 2011 as the year, contradicting 2012. A Kioxia article (secondary, not used) says 133 MT/s. Treat the rate as low confidence.
    ONFI 3.1ONFISpec published400 MT/s400 MT/s, fastest modeOctober 2012ONFI 2012Table 21: maximum speed 200 MT/s and 400 MT/s (NV-DDR2 400). Specs page says 'Published in October of 2012'; the spec file is dated Sep. 21, 2012 (errata Oct. 12, 2012). Defined maximum, no speed increase over 3.0.
    ONFI 2.3ONFISpec published200 MT/s200 MT/s, fastest modeOctober 2011ONFI 2011Published October 2011 (ONFI 2.3a spec dated Oct. 19, 2011, errata to 2.2 plus EZ-NAND). Source-synchronous mode 5 tCK 10 ns (~100 MHz) DDR = 200 MT/s. Defined maximum.
    ONFI 3.0ONFISpec publishedUp to 400 MB/s400 MT/s, fastest modeMarch 2011ONFI 2026
    Toggle 2.0ToggleSpec published400 MT/s400 MT/s, fastest modeJuly 2010Toshiba/Samsung (hosted by KIOXIA) 2010Announcement date: Samsung and Toshiba, 22 Jul 2010, commitment to a 400 Mbps toggle DDR 2.0 specification and to standardising it through JEDEC. Samsung 2022 note also lists 2.0 = 400Mbps. This is the announcement of the spec, not first shipment.
    ONFI 2.2ONFISpec published200 MT/s200 MT/s, fastest modeOctober 2009ONFI 2009'Ratified in October of 2009'; spec date Oct. 7, 2009. Source-synchronous timing mode 5 tCK 10 ns (~100 MHz) DDR = 200 MT/s. Defined maximum.
    ONFI 2.1ONFISpec published200 MT/s200 MT/s, fastest modeJanuary 2009ONFI 2009ONFI page: 'ratified in January of 2009 ... speeds of 166 MB/s and 200 MB/s'; spec date Jan. 14, 2009. 200 MT/s = source-synchronous mode 5 (10 ns / ~100 MHz DDR; mode 5 table read in the 2.2 and 2.3a PDFs, not directly in the 2.1 extraction). Defined maximum.
    ONFI 2.0ONFISpec publishedRevision 2.0133 MT/s, fastest modeFebruary 27, 2008ONFI 2008
    ONFI 1.0ONFISpec published50 MT/s50 MT/s, fastest modeDecember 2006ONFI 2006Asynchronous (SDR) only. Fastest timing mode 5 has tRC 20 ns (EDO capable), so 1/20 ns = 50 MT/s (derived from the table, not a stated figure). Date is the spec date on the ONFI specs page (Dec. 28, 2006). The specs page text for 2.0 says the legacy interface was limited to 50 MB/s. Defined maximum.
    Toggle 1.0ToggleSpec published133 MT/s133 MT/s, fastest modeNot datedToshiba/Samsung (hosted by KIOXIA) 2010Samsung/Toshiba release of 22 Jul 2010: 'The current toggle DDR 1.0 specification ... has a 133Mbps interface'. Samsung 2022 and 2024 footnotes also list 1.0 = 133Mbps. The 1.0 introduction date is not stated on any page opened, so 'published' is null. Vendor-defined, not a JEDEC revision.
    Toggle 3.0ToggleSpec published800 MT/s800 MT/s, fastest modeNot datedSamsung 2022Rate only: Samsung editor note (Nov 2022) lists 3.0 = 800Mbps; repeated in the 2024 Korean footnote. No page opened gives the date Toggle 3.0 was announced, so 'published' is null. Samsung's VLSI 2020 F-chip paper (Table 1, with its earlier F-chip as prior work) lists 1.333 Gb/s/pin for Toggle 3.0 and 1.8 Gb/s/pin for Toggle 4.0. Those are retimed multi-chip-package rates through a buffer chip, not the per-die standard rate, so max_mts stays.

    DRAM and HBM34 rows

    JEDEC’s DRAM interfaces, DDR, LPDDR, GDDR and HBM, and the module parts around them, such as power chips and data buffers. The DRAM and HBM timelines draw the DDR and HBM speeds as their dashed lines.

    200020052010201520202025JEDEC DRAM2000: JEDEC, DDR SDRAM standard, JESD79January 2005: JEDEC, DDR2 SDRAM, JESD79-2BJanuary 2006: JEDEC, DDR2 SDRAM, JESD79-2CJanuary 2007: JEDEC, DDR2 SDRAM, JESD79-2DJune 26, 2007: JEDEC, DDR3April 2008: JEDEC, DDR2 SDRAM, JESD79-2ENovember 2009: JEDEC, DDR2 SDRAM, JESD79-2FSeptember 25, 2012: JEDEC, DDR4October 2013: JEDEC, HBM (JESD235)January 12, 2016: JEDEC, HBM2 (JESD235A)January 19, 2016: Samsung, Samsung, the first 4 GB HBM2 package, in mass productionFebruary 19, 2019: JEDEC, LPDDR5July 14, 2020: JEDEC, DDR5January 27, 2022: JEDEC, HBM3March 5, 2024: JEDEC, GDDR7, the first JEDEC DRAM standard with PAM signalingApril 16, 2025: JEDEC, HBM4 (JESD270-4)July 9, 2025: JEDEC, LPDDR6July 13, 2026: JEDEC, SPHBM4: HBM4-class bandwidth on organic substrates

    Swipe the timeline sideways to reach the years since 2015.

    • Spec published
    • Sample
    • Shipping
    • Context, not a first
    Each marker is one milestone. Hover or tap a marker for its date and maker; it links to its row in the table.

    Data rate per pin (Gb/s)

    • HBM
    • DDR
    • LPDDR
    0246820082010201220142016201820202022202420262022: HBM3, 6.4 Gb/s per pin6.42025: HBM4 (JESD270-4), 8 Gb/s per pin82007: DDR3, 1.6 Gb/s per pin1.62012: DDR4, 3.2 Gb/s per pin3.22020: DDR5, 4.8 Gb/s per pin4.82019: LPDDR5, 6.4 Gb/s per pin6.4
    Gb/s per pin, linear scale. Each point is the headline rate its own source prints for that spec or part.

    StandardWhoStageMeasureHeadline speedDateSourceNote
    JESD82-543 DDR5MRCD03 multiplexed rank registering clock driverJEDECPublishedSeptember 2026JEDEC pageA DDR5 registering clock driver with parity and CRC that drives the address and control nets on MRDIMMs.
    JESD239F GDDR7JEDECPublishedAugust 2026JEDEC pageGDDR7 graphics memory.
    SPHBM4: HBM4-class bandwidth on organic substratesJEDECSpec publishedJESD330-4July 13, 2026JEDEC 2026
    JESD328 SOCAMM2 common standard (LPDDR5/5X), v1.00JEDECPublishedJune 2026JEDEC pageModule standard built on LPDDR5 and LPDDR5X.
    CAMM2 Raw Card E annex (JESD318 F0 RCE), v2.00JEDECPublishedMay 2026JEDEC pageAnnex to the CAMM2 module standard.
    JESD82-552 DDR5MDB02 multiplexed rank data bufferJEDECPublishedApril 30, 2026JEDEC pageDDR5 multiplexed rank data buffer, announced with other parts of the DDR5 MRDIMM ecosystem.
    JESD406-5D LPDDR5/5X SPD contentsJEDECPublishedMarch 24, 2026JEDEC pageUpdated LPDDR5 and LPDDR5X SPD contents, with enhanced mode-switching support.
    JESD301-5 PMIC5030 (DDR5 module power-management chip), v1.00JEDECPublishedJanuary 2026JEDEC pagePower-management chip spec for DDR5 modules.
    JESD270-4A (HBM4)JEDECPublishedDecember 2025JEDEC pageVersion 1.1 on the catalog page.
    JESD79-5D (DDR5)JEDECPublishedNovember 2025JEDEC pageVersion 1.41, the current DDR5 edition on the catalog page.
    LPDDR6JEDECSpec published2 sub-channels of 12 data linesJuly 9, 2025JEDEC 2025
    JESD209-6 (LPDDR6)JEDECPublishedJuly 2025JEDEC pageJEDEC’s LPDDR page says LPDDR6 was published in July 2025.
    HBM4 (JESD270-4)JEDECSpec published8 Gb/s, 2,048-bit, up to 2 TB/s8 Gb/s per pinApril 16, 2025JEDEC 2025
    JESD238B.01 (HBM3)JEDECPublishedApril 2025JEDEC pageHBM3 DRAM.
    DDR5 JESD79-5CJEDECSpec published8,800 MT/s8,800 MT/s, fastest modeApril 2024JEDEC 2024Release dated 2024-04-17: timing parameters defined up to 8800 Mbps per pin. JESD79-5D (Version 1.41) followed in November 2025; its public landing page prints no speed, so none is recorded.
    GDDR7, the first JEDEC DRAM standard with PAM signalingJEDECSpec publishedPAM3 signalingMarch 5, 2024JEDEC 2024
    JESD209-5C (LPDDR5 and LPDDR5X)JEDECPublishedJuly 2023JEDEC pageCurrent LPDDR5 and LPDDR5X edition on the catalog page.
    HBM3JEDECSpec published6.4 Gb/s per pin, 819 GB/s per device6.4 Gb/s per pinJanuary 27, 2022JEDEC 2022
    DDR5 JESD79-5AJEDECSpec published6,400 MT/s6,400 MT/s, fastest modeOctober 2021JEDEC 2021Release dated 2021-10-26: timing definitions up to 6400 MT/s for DRAM core timings and 5600 MT/s for IO AC timings, to support an ecosystem up to 5600 MT/s.
    JESD235D (HBM and HBM2)JEDECPublishedMarch 2021JEDEC pageCatalog page for the first two HBM generations.
    DDR5JEDECSpec publishedLaunch at 4.8 Gb/s4.8 Gb/s per pinJuly 14, 2020JEDEC 2020
    LPDDR5JEDECSpec published6,400 MT/s6.4 Gb/s per pinFebruary 19, 2019JEDEC 2019
    JESD235BJEDECSpec published307 GB/s per stack2.4 Gb/s per pinDecember 2018JEDEC 2018Press release dated 17 December 2018. It states 2.4Gb/s per pin, up to 307GB/s and up to 24GB from 12-high stacks.
    Samsung, the first 4 GB HBM2 package, in mass productionSamsungFirst shipping (maker’s claim)4 GB packageJanuary 19, 2016Samsung 2016Samsung’s own claim.
    HBM2 (JESD235A)JEDECSpec published256 GB/s per device, 1,024-bit256 GB/s per stackJanuary 12, 2016JEDEC 2016
    HBM (JESD235)JEDECSpec published (secondary date)JESD235, the first HBM standardOctober 2013Cadence 2025Date from secondary sources, not JEDEC: a 2025 Cadence blog and the Ramulator paper’s reference list. JEDEC’s own pages do not date the first edition.
    DDR4JEDECSpec published1.6 to 3.2 GT/s per pin3.2 Gb/s per pinSeptember 25, 2012JEDEC 2012
    DDR2 SDRAM, JESD79-2FJEDECLatest editionDDR2-400 to DDR2-800November 2009JEDEC 2009A context row: the edition JEDEC lists today, a revision of JESD79-2E. The first DDR2 publication date is not sourced.
    DDR2 SDRAM, JESD79-2EJEDECEarlier editionApril 2008JEDEC 2009Edition dated April 2008, as JESD79-2F names it in its annex of changes between editions.
    DDR3JEDECSpec published800 to 1,600 MT/s1.6 Gb/s per pinJune 26, 2007JEDEC 2007
    DDR2 SDRAM, JESD79-2DJEDECEarlier editionJanuary 2007JEDEC 2009Edition dated January 2007, as JESD79-2F names it in its annex of changes between editions.
    DDR2 SDRAM, JESD79-2CJEDECEarlier editionJanuary 2006JEDEC 2009Edition dated January 2006, as JESD79-2F names it in its annex of changes between editions.
    DDR2 SDRAM, JESD79-2BJEDECEarlier editionJanuary 2005JEDEC 2009Edition dated January 2005, as JESD79-2F names it in its annex of changes between editions.
    DDR SDRAM standard, JESD79JEDECSpec publishedJESD792000JEDEC 2026

    NVMe, drive features and management13 rows

    The commands a drive answers, the features added to them over the years, such as zoned namespaces and flexible data placement, and SNIA’s Swordfish for managing storage.

    200020052010201520202025NVMeMarch 1, 2011: NVM Express, NVM Express 1.0 ratifiedJune 3, 2021: NVM Express, NVMe 2.0: the base spec split into separate command setsAugust 1, 2025: NVM Express, NVMe Base 2.3 ratifiedJuly 31, 2026: NVM Express, NVMe Base 2.4, the newest revisionFirmware featuresSeptember 4, 2019: Samsung, Samsung builds the first standards-based key value SSD prototype, on SNIA’s KV APIJune 2020: NVM Express, NVMe Zoned Namespace (ZNS) Command Set 1.0November 9, 2020: Western Digital, Western Digital says it is sampling a ZNS SSD, the Ultrastar DC ZN540June 3, 2021: NVM Express, Key Value Command Set, in the NVMe 2.0 librarySeptember 2021: Western Digital, Western Digital’s Ultrastar DC ZN540 data sheet lists ZNS part and model numbers, the earliest dated product document foundDecember 2022: NVM Express, Flexible Data Placement (TP4146) ratifiedAugust 2023: Samsung and Meta, Samsung and Meta demonstrate Flexible Data Placement at FMS 2023, cutting write amplification

    Swipe the timeline sideways to reach the years since 2015.

    • Spec published
    • Sample
    • Shipping
    • Context, not a first
    Each marker is one milestone. Hover or tap a marker for its date and maker; it links to its row in the table.

    StandardWhoStageMeasureHeadline speedDateSourceNote
    NVMe Base 2.4, the newest revisionNVM ExpressLatest revisionRevision 2.4July 31, 2026NVM Express 2026A context row: the current revision, not a first.
    NVMe over PCIe Transport Specification, Revision 1.4NVMePublishedJuly 31, 2026NVMe pageRatified 31 July 2026.
    Swordfish v1.2.9, published as a SNIA standardSNIAPublishedJuly 2026SNIA pageDate shown is that of SNIA’s blog post announcing it.
    NVMe Base 2.3 ratifiedNVM ExpressSpec publishedRevision 2.3August 1, 2025NVM Express 2025
    Samsung and Meta demonstrate Flexible Data Placement at FMS 2023, cutting write amplificationSamsung and MetaDemonstrated (earliest found)FDP with CacheLibAugust 2023Samsung 2023The earliest FDP drive demonstration found; no source found names a first shipping FDP drive.
    Flexible Data Placement (TP4146) ratifiedNVM ExpressSpec publishedTP4146December 2022NVM Express 2023The month comes from the date in the ratified archive’s file name.
    Western Digital’s Ultrastar DC ZN540 data sheet lists ZNS part and model numbers, the earliest dated product document foundWestern DigitalDatasheet, part numbers (earliest found)ZNS NVMe SSD, 2 TB and 4 TBSeptember 2021Western Digital 2021Earliest found, not a claimed first. Western Digital announces no volume shipping date, and the data sheet calls its figures sample specifications.
    NVMe 2.0: the base spec split into separate command setsNVM ExpressSpec publishedRevision 2.0June 3, 2021NVM Express 2021
    Key Value Command Set, in the NVMe 2.0 libraryNVM ExpressSpec publishedKV Command SetJune 3, 2021NVM Express 2021
    Western Digital says it is sampling a ZNS SSD, the Ultrastar DC ZN540Western DigitalSamplingZNS NVMe SSDNovember 9, 2020Western Digital 2020Western Digital does not call it the first.
    NVMe Zoned Namespace (ZNS) Command Set 1.0NVM ExpressSpec publishedZNS Command Set 1.0June 2020NVM Express 2022NVM Express’s own deck dates the ratification to June 2020 and gives no day.
    Samsung builds the first standards-based key value SSD prototype, on SNIA’s KV APISamsungPrototype (maker’s claim)SNIA KV APISeptember 4, 2019Samsung 2019Samsung’s own claim of a first, dated 4 September 2019 by Samsung’s US newsroom. A prototype, not a shipping drive; it predates the NVMe KV Command Set.
    NVM Express 1.0 ratifiedNVM ExpressSpec publishedRevision 1.0March 1, 2011NVM Express 2011

    Data center hardware and form factors28 rows

    The Open Compute Project’s data center SSD spec, SNIA’s form factors and connectors, and the wider data center hardware the OCP publishes.

    200020052010201520202025OCP SSD specMarch 18, 2020: Open Compute Project, NVMe Cloud SSD Specification 1.0May 18, 2021: Open Compute Project, Datacenter NVMe SSD 2.0: latency monitoring, power states, SPDMSeptember 22, 2023: Open Compute Project, Datacenter NVMe SSD 2.5: telemetry data areas and FDP

    Swipe the timeline sideways to reach the years since 2015.

    • Spec published
    • Sample
    • Shipping
    • Context, not a first
    Each marker is one milestone. Hover or tap a marker for its date and maker; it links to its row in the table.

    StandardWhoStageMeasureHeadline speedDateSourceNote
    SFF-TA-1039 PCIe active module/cable supplemental specification 1.0SNIAPublishedOctober 16, 2026SNIA page
    SFF-TA-1048 compression mount high-speed cable interconnect 1.0SNIAPublishedSeptember 29, 2026SNIA page
    SFF-8614 mini multilane 4/8X shielded cage/connector (HDsh) 3.6SNIAPublishedJuly 20, 2026SNIA page
    SFF-8419 SFP+ power and low-speed interface 2.0aSNIAPublishedJuly 10, 2026SNIA page
    SFF-TA-1008 enterprise and datacenter standard form factor (E3) 3.0aSNIAPublishedJuly 10, 2026SNIA pageThe E3 form factor spec.
    SFF-8613 mini multilane 4/8X unshielded connector (HDun) 3.6SNIAPublishedJune 22, 2026SNIA page
    SFF-TA-1038 low-profile high-density flexible cable connector 1.0SNIAPublishedJune 7, 2026SNIA page
    SFF-8024 module management reference code tables 4.14SNIAPublishedJune 4, 2026SNIA page
    SFF-8636 management interface for 4-lane modules and cables 2.12SNIAPublishedApril 29, 2026SNIA page
    SFF-TA-1041 ULP Gen 7 PCIe connector 1.0SNIAPublishedApril 7, 2026SNIA page
    SFF-TA-1044 hybrid orthogonal EDSFF connector system 1.0SNIAPublishedMarch 27, 2026SNIA page
    SFF-TA-1045 hybrid orthogonal EDSFF connector pin and signal definition 1.0SNIAPublishedMarch 13, 2026SNIA page
    GOV-TA-0001 SFF TWG process guide 3.0SNIAPublishedJanuary 30, 2026SNIA page
    SFF-9400 Universal 4/8X pinouts 1.1SNIAPublishedJanuary 19, 2026SNIA page
    SFF-8472 SFP+ management interface 12.5aSNIAPublishedJanuary 16, 2026SNIA page
    BoW.Flexi V1.0.0OCPPublished2026OCP page
    Enhanced Telemetry Optics Product Software Specification V1.0.0OCPPublished2026OCP page
    Foundation Chiplet System Architecture (FCSA) V1.1.0OCPPublished2026OCP page
    MGX Accelerated Computing Rack and Trays Specification V1.2.0OCPPublished2026OCP page
    MQD/MQDB OCP Design Specification V1.0.0OCPPublished2026OCP page
    Open Boot and Management Framework Interface Consolidation Protocol (OBMF-ICP) V1.0.0OCPPublished2026OCP page
    Scale-Up Ethernet Transport (SUE-T) Base Specification v1.0.0OCPPublished2026OCP page
    Single-Phase Direct-to-Chip Cold Plate Test Specification V1.0.0OCPPublished2026OCP page
    Transparent Remote Optical Transceiver Messaging with ePPS Design Specification V0.9.0OCPPublished2026OCP page
    Universal Quick Disconnect (UQD) Specification V2.0.0OCPPublished2026OCP page
    Datacenter NVMe SSD 2.5: telemetry data areas and FDPOpen Compute ProjectSpec publishedVersion 2.5September 22, 2023Open Compute Project 2025
    Datacenter NVMe SSD 2.0: latency monitoring, power states, SPDMOpen Compute ProjectSpec publishedVersion 2.0May 18, 2021Open Compute Project 2025
    NVMe Cloud SSD Specification 1.0Open Compute ProjectSpec publishedVersion 1.0March 18, 2020Open Compute Project 2020The revision table of the later 2.6 specification prints 03/16/2020 for the same release.

    Mobile and embedded storage8 rows

    UFS, the flash interface in phones, cars and other embedded devices, is explained in the UFS guide.

    200020052010201520202025UFSFebruary 24, 2011: JEDEC, UFS 1.0, the first Universal Flash Storage standardSeptember 18, 2013: JEDEC, UFS 2.0 (JESD220B)January 30, 2018: JEDEC, UFS 3.0 (JESD220D)January 30, 2020: JEDEC, UFS 3.1 (JESD220E) adds Write Booster, DeepSleep and HPBAugust 17, 2022: JEDEC, UFS 4.0 (JESD220F)January 8, 2025: JEDEC, UFS 4.1 (JESD220G)February 26, 2026: JEDEC, UFS 5.0 (JESD220H), on MIPI M-PHY 6.0

    Swipe the timeline sideways to reach the years since 2015.

    • Spec published
    • Sample
    • Shipping
    • Context, not a first
    Each marker is one milestone. Hover or tap a marker for its date and maker; it links to its row in the table.

    Rate per lane (Gb/s)

    • UFS
    248163264201220142016201820202022202420262011: UFS 1.0, the first Universal Flash Storage standard, 2.9 Gb/s per lane2.92013: UFS 2.0 (JESD220B), 5.8 Gb/s per lane5.82018: UFS 3.0 (JESD220D), 11.6 Gb/s per lane11.62022: UFS 4.0 (JESD220F), 23.32 Gb/s per lane23.322026: UFS 5.0 (JESD220H), on MIPI M-PHY 6.0, 46.6 Gb/s per lane46.6
    Gb/s per lane, log scale. Each point is the headline rate its own source prints for that spec or part.

    StandardWhoStageMeasureHeadline speedDateSourceNote
    UFS 5.0 (JESD220H), on MIPI M-PHY 6.0JEDECSpec publishedHS-G6 46.6 Gb/s per lane46.6 Gb/s per laneFebruary 26, 2026JEDEC 2026
    JESD220H Universal Flash Storage (UFS) 5.0JEDECPublishedFebruary 2026JEDEC pageUniversal Flash Storage 5.0. The catalog page offers it for purchase.
    UFS 4.1 (JESD220G)JEDECUpdateUpdate to UFS 4.0January 8, 2025JEDEC 2025A context row: an update to UFS 4.0, not a first.
    UFS 4.0 (JESD220F)JEDECSpec publishedAbout 4.2 GB/s23.32 Gb/s per laneAugust 17, 2022JEDEC 2022MIPI Alliance 2025 (speed)
    UFS 3.1 (JESD220E) adds Write Booster, DeepSleep and HPBJEDECUpdateWrite BoosterJanuary 30, 2020JEDEC 2020A context row: an update that adds features and no new link rate.
    UFS 3.0 (JESD220D)JEDECSpec publishedHS-G4 11.6 Gb/s per lane11.6 Gb/s per laneJanuary 30, 2018JEDEC 2018
    UFS 2.0 (JESD220B)JEDECSpec publishedHS-G3 5.8 Gb/s per lane (optional)5.8 Gb/s per laneSeptember 18, 2013JEDEC 2013JEDEC 2013 (speed)
    UFS 1.0, the first Universal Flash Storage standardJEDECSpec published300 MB/s2.9 Gb/s per laneFebruary 24, 2011JEDEC 2011

    External and legacy drive links12 rows

    The links outside the box and before NVMe: USB and Thunderbolt for external drives, SATA and SAS for drives inside it.

    200020052010201520202025USBNovember 2008: USB 3.0 Promoter Group, USB 3.0 released, ten times the rate of USB 2.0March 4, 2019: USB Promoter Group, USB4 announced ahead of publicationSeptember 3, 2019: USB-IF, USB4 specification published, up to 40 Gb/s over two lanesOctober 18, 2022: USB-IF, USB4 Version 2.0 published: USB 80Gbps over USB Type-CThunderboltFebruary 24, 2011: Intel, Thunderbolt launched, first on Apple’s new MacBook ProJuly 8, 2020: Intel, Thunderbolt 4 detailed, always 40 Gb/sSeptember 12, 2023: Intel, Thunderbolt 5 announced with a prototype laptop and dockSATAMay 27, 2009: SATA-IO, SATA Revision 3.0 released, the last SATA speed stepMarch 2021: SATA-IO, SATA Revision 3.5a, the newest revisionSASAugust 8, 2017: SCSI Trade Association, 24G SAS specification development complete2019: INCITS T10, SAS-4 published as INCITS 534-2019September 2026: INCITS T10, SAS-5 in public review

    Swipe the timeline sideways to reach the years since 2015.

    • Spec published
    • Sample
    • Shipping
    • Context, not a first
    Each marker is one milestone. Hover or tap a marker for its date and maker; it links to its row in the table.

    Rate per lane (Gb/s)

    • SATA
    01.534.56200920102009: SATA Revision 3.0 released, the last SATA speed step, 6 Gb/s per lane6
    Gb/s per lane, linear scale. Each point is the headline rate its own source prints for that spec or part.

    Total link rate (Gb/s)

    • Thunderbolt
    • USB
    481632641282008201020122014201620182020202220242011: Thunderbolt launched, first on Apple’s new MacBook Pro, 10 Gb/s102023: Thunderbolt 5 announced with a prototype laptop and dock, 80 Gb/s802008: USB 3.0 released, ten times the rate of USB 2.0, 5 Gb/s52019: USB4 specification published, up to 40 Gb/s over two lanes, 40 Gb/s402022: USB4 Version 2.0 published: USB 80Gbps over USB Type-C, 80 Gb/s
    Gb/s, log scale. Each point is the headline rate its own source prints for that spec or part.

    StandardWhoStageMeasureHeadline speedDateSourceNote
    SAS-5 in public reviewINCITS T10Public reviewSAS-5 draftSeptember 2026INCITS T10 2026A context row: the next SAS standard, not yet published.
    Thunderbolt 5 announced with a prototype laptop and dockIntelPrototype shownThunderbolt 5, 120 Gb/s Bandwidth Boost80 Gb/sSeptember 12, 2023Intel 2023
    USB4 Version 2.0 published: USB 80Gbps over USB Type-CUSB-IFSpec publishedUSB4 Version 2.0, PAM380 Gb/sOctober 18, 2022USB-IF 2022
    SATA Revision 3.5a, the newest revisionSATA-IOLatest revisionSerial ATA Revision 3.5aMarch 2021SATA-IO 2021A context row: the current revision, not a first.
    Thunderbolt 4 detailed, always 40 Gb/sIntelAnnouncedThunderbolt 4, 8000-series controllersJuly 8, 2020Intel 2020A context row: the same top rate as Thunderbolt 3, with stricter minimum requirements.
    USB4 specification published, up to 40 Gb/s over two lanesUSB-IFSpec publishedUSB4, two lanes40 Gb/sSeptember 3, 2019USB-IF 2019
    USB4 announced ahead of publicationUSB Promoter GroupAnnouncedUSB4, pending releaseMarch 4, 2019USB Promoter Group 2019A context row: the announcement; the published spec is the next row.
    SAS-4 published as INCITS 534-2019INCITS T10Standard publishedINCITS 534-20192019INCITS T10 2019A context row: the formal standard behind 24G SAS.
    24G SAS specification development completeSCSI Trade AssociationSpec complete24G SAS (SAS-4 and SPL-4)August 8, 2017SCSI Trade Association (SNIA) 2017
    Thunderbolt launched, first on Apple’s new MacBook ProIntelFirst shippingThunderbolt10 Gb/sFebruary 24, 2011Intel 2011
    SATA Revision 3.0 released, the last SATA speed stepSATA-IOSpec publishedSerial ATA Revision 3.06 Gb/s per laneMay 27, 2009SATA-IO 2009
    USB 3.0 released, ten times the rate of USB 2.0USB 3.0 Promoter GroupSpec publishedUSB 3.0 SuperSpeed5 Gb/sNovember 2008Intel 2013

    Reliability, test and security2 rows

    Test and qualification rules from JEDEC that apply across the parts above.

    StandardWhoStageMeasureHeadline speedDateSourceNote
    JESD264 silicon photonics qualification and reliability requirementsJEDECPublishedOctober 1, 2026JEDEC pageDescribed by JEDEC as the first industry-wide silicon photonics reliability standard.
    JEP203 and JEP204 (SiC short-circuit guideline; stress-procedure catalog)JEDECPublishedJune 3, 2026JEDEC pageReliability guidelines for silicon-carbide power devices.

    Download the standards and their sources: CSV or JSON. Each row is one sourced value with the source it was read from, and the D and T marks as columns.

    What it will not tell you

    This is a list of published specs, dated firsts and this year’s documents, not every revision of every standard. A step nobody dated in public is not here, and a missing row is not a late one. Still open, with no dated public source saved yet:

    • The first edition of the JEDEC DDR2 standard (JESD79-2). JEDEC’s own pages show only later editions. The first HBM standard (JESD235) has a row, but its date comes from a secondary source, not JEDEC.
    • The first shipping drives for zoned namespaces, key value and flexible data placement. The dated drive rows are a ZNS sampling announcement, a key value prototype and an FDP demonstration; none is a shipping drive.
    • The 2026 documents come from the public lists of JEDEC, NVM Express, PCI-SIG, SNIA and the Open Compute Project. ONFI’s and the CXL Consortium’s 2026 releases are not in that list, and a spec behind a members-only login appears only when a public page announces it.

    Rates are the headline figure each source prints, not what a real drive or module delivers. For the dies and controllers behind these interfaces, see the NAND die timeline, the DRAM die timeline, the HBM timeline and the controller timeline.

    The guides behind this data