Working Memory, Part 6: CAMM2, LPCAMM2 and SOCAMM2

For decades a laptop had two ways to carry memory. It could take a SO-DIMM that is pushed into a slot the owner can swap, or it could have low-power DDR (LPDDR) packages soldered straight onto the board. Soldering saves power and space but fixes the capacity for the life of the machine. A compression-attached memory module (CAMM) is a third way. The module is a flat board pressed down onto a connector on the motherboard instead of slid into a slot, and that change lets low-power DRAM become a replaceable part.

CAMM began at Dell. Slides from Tom Schnell, chair of JEDEC’s CAMM task group and a listed CAMM inventor, in a Dell-copyrighted deck presented in May 2024, label the original CAMM the Dell version and CAMM2 the JEDEC version. They add that Dell shipped DDR5 CAMM in its Precision 7000 workstation notebooks before JEDEC’s CAMM2.

Three names need keeping apart. CAMM2 is the JEDEC standard, and it covers modules built from either DDR5 or LPDDR5/5X. LPCAMM2 is what the makers call the LPDDR5/5X version, and it is the one in laptops. SOCAMM2 is a compact, small-outline LPDDR5/5X module built for the CPU memory in SI servers, and it has its own JEDEC standard.

This part of Working Memory is about the module, meaning the board, the connector, and the bus between the DRAM packages and the processor. Part 5 lists the DRAM parts that go onto these modules. The DRAM cell and the DDR bus are in Working Memory, Part 2, and stacked DRAM is in Working Memory, Part 4: High Bandwidth Memory. The standards facts come from JEDEC’s own text where this guide has it. The DDR5 SO-DIMM standard (JESD309A) gives the SO-DIMM baseline, the DDR5 SPD contents standard (JESD400-5D.01) gives CAMM2’s SPD data, and the PMIC5200 standard (JESD301-3) covers its power chip.

This guide has the CAMM2 and SOCAMM2 standards themselves, JESD318B and JESD328, only from JEDEC’s public pages, so the module outlines and pin counts they hold are not on this page. Every maker figure is measured against a baseline that maker chose, and this page names the baseline each time.

Slot, solder or compression

A DDR5 SO-DIMM is defined by JESD309A. It has 262 pins on 0.5mm centers along one edge of a 69.6mm by 30.0mm board. It runs its DRAM at 1.1V. Its data bus is 64 bits wide, organized as two 32-bit channels, and the standard allows capacities from 8GB to 128GB. Its edge fingers slide into a socket, and the module can come out again.

Soldered LPDDR has no connector at all. Its packages sit on the motherboard on solder balls, as close to the processor as the layout allows. Laptop designers accept that for reasons Micron sets out. LPDDR is built to save power in every state, not only at idle, and an LPDDR package can stack up to 16 DRAM die, where DDR5 manages at best two die per package with wire bonding or four with through-silicon vias, both of them expensive to make. In exchange, the memory is fixed. A package that fails in manufacturing can take the motherboard with it, and the buyer picks a capacity once for the life of the laptop.

The figure shows the trade the CAMM was built to break. A SO-DIMM is replaceable but carries half the bus in each module, and its slot and edge fingers sit between the DRAM and the processor. Soldered LPDDR is compact and frugal but cannot be serviced. A CAMM2 keeps the module and changes the joint. The flat board’s contact pads are pressed onto a connector, and the whole 128-bit bus sits on one dual-channel module. Micron calls its LPCAMM2 the industry’s first, and the first new form factor for client PCs since the SO-DIMM arrived in 1997.

What JEDEC standardized, and when

JEDEC published JESD318 on December 5, 2023, as the Compression Attached Memory Module (CAMM2) Common Standard. One document covers two memory types. DDR5 CAMM2s are aimed at performance notebooks and mainstream desktops, and LPDDR5/5X CAMM2s at a wider range of notebooks and some servers. Both share the connector design, but the pinouts differ, and JEDEC made the mounting deliberately different between the two so a module cannot be fitted to a board it does not belong on.

JEDEC’s standard also lets the connector stack. A dual-channel CAMM2 uses the whole connector. Split lengthwise, it becomes two single-channel halves, and JEDEC’s example puts one DDR5 channel at 2.85mm height and a second at 7.5mm so that one module steps over the other. As of October 2026 the current revision is JESD318B at Version 1.14. JEDEC published it in November 2025, and it comes from the JC-45 committee. In the SPD standard JESD400-5D.01, JC-45 is named as the committee for DRAM modules.

Two things stand out in the timeline. The laptop module and its standard arrived together. JEDEC’s CAMM2 standard was out a month before Micron’s first LPCAMM2. The server module went the other way. Micron’s first SOCAMM was built with NVIDIA and was in volume production in March 2025, and the JEDEC SOCAMM2 standard followed in June 2026. JEDEC’s page for JESD328 draws the line itself. “SOCAMM” is the general name for the module category, and SOCAMM2 is the JEDEC version. Its connector is a compression connector on a 1.60mm by 0.93mm contact pitch, with its own registered outline, SO-033.

JEDEC also folded the new modules into the DDR5 serial presence detect (SPD)Serial presence detect is a small nonvolatile memory on a module that describes it, so the BIOS can read it and set up the memory channels correctly. standard, which defines the data a module reports about itself at boot. JESD400-5D.01 gives CAMM2 and SOCAMM2 their own base module type codes, 1000 and 1001, in the same list as SODIMM, RDIMM and solder down. It also notes that a CAMM2 is not technically a dual in-line memory module, but treats it as one for documentation.

One module, both channels

Width is the biggest electrical difference, and JESD400-5D.01 lists the bus widths side by side. A SO-DIMM carries two 32-bit sub-channels, 64 bits. A dual-channel DDR CAMM2 carries four 32-bit sub-channels, 128 bits. A laptop processor with a 128-bit memory bus therefore needs two SO-DIMMs to fill it, or one CAMM2. The LPDDR5/5X version reaches the same 128 bits another way. JEDEC’s Raw Card E annex, Version 2.00 of May 2026, builds it from four 315-ball dual-channel LPDDR5/5X packages with eight 16-bit sub-channels between them, so each package carries 32 bits.

That width changes the parts count, as Micron spells out. A notebook’s 128-bit SO-DIMM bus can carry up to 32 DRAM die. LPCAMM2 fills the same bus with four LPDDR5X placements, and capacity comes from how many die are stacked in each package, not from how many packages there are, so Micron builds every LPCAMM2 capacity on one PCB and claims simpler motherboard routing than SO-DIMM. It changes what the system builder pays for as well. Each SO-DIMM carries its own set of support parts, so a second channel means buying them twice, while one CAMM2 carries one set for both channels.

Splitting the connector, as described above, is the other way to grow. A second single-channel module sits on the same connector, stepped over the first.

Power and signals on the module

A CAMM2 is more than DRAM packages on a board. JEDEC’s PMIC5200 standard (JESD301-3) describes the power management IC (PMIC) designed for a typical LPDDR5 CAMM2. It takes a single input between 3.0V and 5.5V and makes the module’s rails itself, with four step-down switching regulators and two linear regulators at 1.8V and 1.0V. It reports its own output current, power and temperature, keeps an error log, and can scale the voltage of the DRAM I/O rail.

Putting the regulators on the module means the motherboard hands over one supply and the module does the rest. A DDR5 RDIMM already makes the same split with the PMIC that JESD301-1A defines for memory modules. DDR5 SO-DIMMs carry a PMIC as well, and JESD309A runs it in single-phase regulator mode. The standard names that part as the PMIC5100. For the DDR5 version of CAMM2, the SPD standard reserves bytes for up to two clock drivers on the module, each reported as a DDR5CKD01 part.

On the signal side the makers say least. In SK hynix’s account, the SOCAMM2 compression connector enhances signal integrity and makes the module easy to replace, and Micron’s LPCAMM2 page claims simpler motherboard routing than SO-DIMM. Neither publishes the measurement behind it, and the electrical limits sit in JESD318B and JESD328, which this page does not quote. JEDEC’s own SOCAMM2 announcement is careful in the same way. The standard is forecast to support the full LPDDR5X data rate, including configurations up to 9.6Gb/s per pin where platform signal integrity allows. The public numbers do show LPDDR5X on a module reaching rates the DDR5 SO-DIMM baseline does not.

LPCAMM2 in laptops

Micron announced LPCAMM2 on January 9, 2024, in capacities from 16GB to 64GB, sampling then and in production in the first half of the year. Its comparisons are all against a DDR5 SO-DIMM and give up to 9,600MT/s against 5,600MT/s, up to 61% lower active power per 64-bit bus at the same speed, up to 80% lower system standby power, and 64% less space. The space figure is a volume comparison between a dual-stacked DDR5 SO-DIMM setup of 32,808mm³ and an LPCAMM2 of 11,934mm³, each counting board, socket, and memory, as Micron’s May 2024 release spells out. Samsung measures mounting area instead, and puts LPCAMM2 at 60% smaller than two x64 SO-DIMMs.

In May 2024 the first laptop followed. Micron released Crucial LPCAMM2 in 32GB and 64GB at up to 7,500MT/s, and Lenovo called its ThinkPad P1 Gen 7 the first laptop on the market to use the form factor. Lenovo’s spec sheet lists one LPCAMM2 connector, dual-channel, up to 64GB, and adds that the LPDDR5X-7500 modules run at 7,467MT/s because of platform limits. In September 2025 Crucial LPCAMM2 moved to speeds up to 8,533MT/s in densities up to 64GB, for mobile workstations from Lenovo and Dell.

Micron’s first release gave 9,600 as the top LPDDR5X rate it forecast in January 2024, against 8,800MT/s for DDR5. Modules on sale have climbed toward it. They reached up to 7,500 at launch, ran at 7,467 in the first laptop, then reached up to 8,533. Even the first step is a third faster than the DDR5 SO-DIMM baseline of 5,600. Because one LPCAMM2 carries the whole 128-bit bus, Micron also points out that a single module gives a laptop dual-channel support, where SO-DIMMs need a pair.

Upgrading is the point for the owner. Crucial sells LPCAMM2 as a retail part, and Micron calls user upgrades an industry first for low-power memory. For desktop kits on ordinary DIMMs, see the Best RAM picks.

SOCAMM and SOCAMM2 in servers

Servers got a version built to replace the RDIMM. Micron announced SOCAMM in March 2025, built with NVIDIA for the GB300 Grace Blackwell Ultra Superchip and already in volume production. It is 14mm by 90mm, which Micron calls one-third the size of a standard RDIMM, the server module whose register chip relays address and command signals from the memory controller to the DRAM. Four placements of 16-die LPDDR5X stacks make a 128GB module. Micron claims more than 2.5 times the bandwidth of an RDIMM at the same capacity. Its footnote compares a 64GB SOCAMM at 8,533MT/s with a 64GB RDIMM at 6,400MT/s. At those speeds, this guide calculates that a 128-bit SOCAMM peaks at 136.5GB/s and a 64-bit RDIMM at 51.2GB/s, so most of the gain is bus width. Those widths come from Micron’s first footnote, which compares one 64GB SOCAMM with two 32GB RDIMMs. Its one-third power figure compares one 128GB SOCAMM with two DDR5 RDIMMs.

JEDEC then wrote the standard. In October 2025 it said JESD328 was nearly complete. It described a compact, serviceable LPDDR5X module for data center SI, forecast to support up to 9.6Gb/s per pin where platform signal integrity allows, and adding an SPD device for module identification and telemetry. JESD328 Version 1.00 was published in June 2026, for main memory in data center and SI servers.

Capacity is what moved fastest. Micron’s 192GB SOCAMM2, sampled in October 2025 on its 1-gamma process at up to 9,600MT/s, holds 50% more than its SOCAMM in the same footprint. In March 2026 Micron sampled a 256GB SOCAMM2 built on a monolithic 32Gb LPDDR5X die, which it says allows 2TB of low-power DRAM on an eight-channel server CPU. In April 2026 SK hynix began mass production of a 192GB SOCAMM2 on its 1cnm LPDDR5X process for NVIDIA’s Vera Rubin platform. Samsung’s tech blog said on September 4, 2026 that customer samples of its own SOCAMM2 were already being supplied, and Samsung puts each module at up to 153.6GB/s.

The server makers’ baselines are all RDIMMs, but each picks its own, so the percentages do not line up. SK hynix claims more than double the bandwidth and more than 75% better power efficiency than a conventional RDIMM, without saying which. Samsung’s product page claims up to 2.6 times the bandwidth and more than 70% better power efficiency than DDR5 RDIMM, while its tech blog puts it at more than twice the bandwidth at over 55% less power. Micron claims one-third the size and power. Samsung adds a mechanical point. An RDIMM stands upright and SOCAMM2 lies flat, which frees room for heatsinks and airflow around the processor.

The processor on the other end shows what that buys. NVIDIA’s Vera CPU is the host processor in Vera Rubin systems. It has 88 Olympus cores and an LPDDR5X subsystem on detachable SOCAMM modules, with up to 1.2TB/s of memory bandwidth and up to 1.5TB per socket. In NVIDIA’s words, SOCAMM replaces soldered memory with modules that can be upgraded. LPCAMM2 made the same move in laptops. Full racks can hold more than 50TB of this CPU-attached memory, by Micron’s count.

For a 2026 white paper written with Meta, Micron ran Meta’s DCPerf benchmarks on two ARM servers with 72 cores per socket and LPDDR5X. One had 512GB per socket at 6,400MT/s and the other had 256GB per socket at 8,533MT/s. During a memory-copy test, DRAM drew 6.8% of total system power. Micron’s own test on those two configurations showed 13% more bandwidth and 11% more throughput on that test for the server with faster memory, and about 9% lower 99th-percentile memory read latency in a MediaWiki web-serving test. Rank count and capacity also differ between the two servers, so speed is not the only difference. A Spark analytics test run at a standard load and at a heavier one put the server with 512GB per socket about 2.82 to 3.45 times ahead in queries per hour, because the smaller one fell back to SSD. The paper does not say which form factor the test servers used.

Micron’s October 2026 webinar slides describe LPDDR6 as a data-center-class memory architecture that combines Meta’s platform and application expertise with Micron’s memory, and they target more than 35% better power than LPDDR5. They give no date and no product. Part 5 covers LPDDR6 among the other memory parts.

Side by side

Bandwidth per module is the cleanest way to compare the three, because it follows from two published numbers. Those are the data rate and the bus width. A DDR5-5600 SO-DIMM on its 64-bit bus peaks at 44.8GB/s. An LPCAMM2 on its 128-bit bus at 7,467MT/s peaks at 119.5GB/s, and at 8,533MT/s at 136.5GB/s. A SOCAMM2 at 9,600MT/s reaches 153.6GB/s, and Samsung gives the same figure per module.

A single LPCAMM2 at the rate the first laptop ran already beats two DDR5-5600 SO-DIMMs together, because it carries the same 128 bits at a higher rate. The server module is the same 128-bit width as the laptop one, with room for the higher per-pin rate JEDEC’s SOCAMM2 announcement forecasts. These are peaks, what the bus could move if every transfer were used, and real workloads see less. Every maker percentage above deserves the same caution.

A CAMM is not a new kind of DRAM. JEDEC defines CAMM2 as a module of DDR5 or LPDDR5/5X, and SOCAMM2 as a module of LPDDR5/5X. Their chips are the same families that go into phones, laptops, and servers, and the standards cover the module’s electrical and mechanical rules. Nor is a CAMM HBM. SOCAMM2 is main memory beside the CPU, while the HBM stacks on an accelerator’s package are a separate tier, covered in Working Memory, Part 4 and charted on the HBM Timeline.

On the Memory and Storage Hierarchy, a CAMM does not change where DRAM sits, because DRAM stays main memory. The change is in how that memory is built and serviced. In a laptop, LPDDR no longer has to be soldered down. In an SI server, low-power DRAM becomes a part a technician can replace. For the dies that go onto these modules, by maker and year, see the DRAM Die Timeline.

Part 7 moves DRAM one link further from the processor, onto a CXL link.