HBM Timeline

How to read it

Each point is one HBM stack that a vendor release or datasheet describes. It sits at the date of the earliest public source cited for that stack, which is the date of the announcement or production news and not the date the stack reached a shipping accelerator. The chart shows 29 stacks from 29 public sources (53 with the accelerators below), not every stack ever made, running from 2013 to 2026, and a stack with no stated value for the chosen measure is left off.

The values are what the vendor states for the shipping stack. A speed a vendor tested a stack to, above what it sells, is not on the chart. Where a vendor prints a lower limit, such as more than 11Gb/s, the marker is hollow and the table shows a sign in front of the number. Bandwidth in the table is the figure the source states. A figure worked out from two the source prints, such as bandwidth from pin speed and interface width, pin speed from bandwidth, or die density from capacity and layer count, carries a D.

The dashed line is the highest value any JEDEC HBM revision had defined by each date. Each revision is dated and read from JEDEC's own public page or press release. A vendor can ship a stack above the standard, so a marker above the line is not an error.

Accelerators that used HBM

Each accelerator sits at the date of its announcement, dated by the vendor's own release, and is drawn at the total memory bandwidth the vendor states for the product, in TB/s. It is a different number from the stack chart: it adds every stack on the package, so a part with more stacks can beat one with a faster stack.

What it will not tell you

A stack sits at the date of its release, not the date it shipped in volume. Vendors do not all publish the same numbers, so a stack with no stated bandwidth is not on that chart even when its pin speed is. The standard line follows the JEDEC revisions that have a public page.

Custom HBM outside the JEDEC line is not charted either. NVIDIA’s NVHBM, announced in August 2026 for NVLink Fusion partners, moves NVIDIA’s memory controller into the HBM base die. NVIDIA claims up to 30% more memory bandwidth, 15% lower HBM power and up to 25% more free compute-die area than standard HBM4E, but it states no stack bandwidth or capacity to plot.

For the physical build of a stack, the layers, the base die and the thermal path, see HBM in the Atlas. For how stacks are joined to the processor, see CoWoS in full and the rest of advanced packaging. The other timelines are on the timelines page.