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    Technical guide

    Working Memory

    The memory a processor reads and writes while it runs, from the SRAM cache on the die to the HBM stack beside it.

    A series on working memory, in six parts. Part 1 opens the SRAM cell and the processor cache built from it. Part 2 opens one DRAM cell and follows it out to a DIMM, a phone and a graphics card. Part 3 looks at the cells that could follow DRAM and what refresh costs. Part 4 stacks DRAM dies beside the processor as High Bandwidth Memory. Part 5 maps the DDR5, LPDDR, GDDR and HBM parts that ship today, and Part 6 covers the CAMM2, LPCAMM2 and SOCAMM2 modules they ship on. The memory map places these memories beside flash and the others; the non-volatile memories are in Beyond NAND, and the memory built for SI in Memory and Storage for SI.

    The series

    Read in order

    Each part builds on the one before, so start with Part 1.

    Working Memory, Part 1: a six-transistor SRAM cell, three cache levels, and a die stacked on a dieA three-panel schematic. Left: a six-transistor SRAM cell between two bitlines, with a wordline above it. Center: three horizontal bars of growing width for the cache levels, the shortest in copper. Right: a logic die with a smaller cache die stacked on top of it and a row of bonds between them.GUIDE / WORKING MEMORY, PART 1The memory inside the processorCELL · LEVELS · STACKED DIE01 CELLSix transistors02 LEVELSLarger and slower03 STACKA second die on topL1L2L3SRAM AND THE PROCESSOR CACHE

    Part 1

    SRAM and the Processor Cache

    How a six-transistor SRAM cell holds a bit, why it is fast, large and leaky, and why processor caches are built from it, some on a stacked die.

    Read Part 1
    Working Memory, Part 2: a DRAM cell, a bit-line voltage curve, and a grid of banksA three-panel schematic. Left: one transistor with a capacitor and a bit line, the one-transistor one-capacitor DRAM cell. Center: a bit-line voltage curve through precharge, share, sense and restore. Right: a grid of bank groups with one group highlighted.GUIDE / WORKING MEMORY, PART 2Cell, read cycle, banks1T1C · BIT LINE · BANKS01 CELL1T1C cell02 BIT LINEShare, sense, restore03 BANKSGroups of banksDRAM FROM THE INSIDE

    Part 2

    DRAM From the Inside

    How a DRAM cell is read and refreshed, how banks and ranks organize it, what DDR timing numbers measure, and how one cell serves three buses.

    Read Part 2
    Working Memory, Part 3: a cell with a capacitor, a cell with two transistors and no capacitor, and a charge topped up by refreshA three-panel schematic. Left: one transistor with a tall capacitor above it, the one-transistor one-capacitor DRAM cell. Center: two transistors side by side, a write transistor feeding the gate of a read transistor, with no capacitor. Right: a charge that drains along a curve and jumps back to the top at evenly spaced refresh ticks.GUIDE / WORKING MEMORY, PART 3Capacitor, no capacitor, refresh1T1C · 2T0C · REFRESH01 1T1CA transistor,a capacitor02 2T0CTwo transistorsand no capacitor03 REFRESHCharge leaks,is topped upchargetime

    Part 3

    What Could Follow DRAM

    Why the DRAM cell is hard to shrink, what refresh costs, and what capacitorless, stacked and ferroelectric cells trade, with labs kept apart from roadmaps.

    Read Part 3
    A stack of DRAM dies beside a processor on a silicon interposerSide view: a stack of ten DRAM dies on a base die stands beside a processor die. Both sit on a silicon interposer on a package substrate, and a dense band of wires in the interposer joins the base die to the processor. Vertical through-silicon vias run up through the dies.GUIDE / WORKING MEMORY, PART 4The stack beside the dieSIDE VIEW · NOT TO SCALEPACKAGE SUBSTRATESILICON INTERPOSERPROCESSORBASE DIEDRAM DIES ON A BASE DIEWIDE BUS

    Part 4

    High Bandwidth Memory

    What an HBM stack is, why its bus is wide rather than fast, why the chip edge limits bandwidth, and how a stack differs from a DIMM and from a new cell.

    Read Part 4
    Four copper DRAM packages on one baselineFour memory packages on one baseline, drawn in copper: a DDR5 chip, a thin LPDDR5X package, a taller GDDR7 chip, and an HBM stack of dies on a base die. Gold dots mark contacts. No scale and no numbers.GUIDE / WORKING MEMORY, PART 5Four DRAM packagesDDR5 · LPDDR5X · GDDR7 · HBMDDR5PCs, serversLPDDR5XphonesGDDR7graphicsHBMacceleratorsNOT TO SCALE

    Part 5

    Current Memory ICs

    A sourced guide to the DRAM chips in use now: DDR5, LPDDR5X, GDDR7 and HBM3E and HBM4, what is shipping, what is only sampling, and what is still research.

    Read Part 5
    A CAMM2 module screwed flat onto a compression connectorSide view: a flat memory module with four memory packages on top lies on a compression connector on the motherboard, held down by two screws instead of standing in a slot; its pads press onto the connector's spring contacts.GUIDE / WORKING MEMORY, PART 6A memory module pressed flatSIDE VIEW · NOT TO SCALECAMM2 MODULEmotherboardCOMPRESSION CONNECTOR

    Part 6

    CAMM2, LPCAMM2 and SOCAMM2

    What CAMM2, LPCAMM2, and SOCAMM2 are, the JEDEC standards behind them, how they differ from SO-DIMMs and soldered LPDDR, and who makes them.

    Read Part 6
    A processor linked to a CXL memory expanderA processor package on the left is joined by a two-lane link, labeled CXL.io and CXL.mem, to a memory expander on the right: a board carrying a controller chip and four memory packages. The memory sits a link away from the processor instead of in a DIMM slot beside it.GUIDE / WORKING MEMORY, PART 7DRAM one link further outPROCESSOR · LINK · EXPANDERPROCESSORCXL.ioCXL.memMEMORY EXPANDER

    Part 7

    CXL Memory Explained

    How CXL memory works: the three device types, what each release from 1.0 to 4.0 added, how the OS sees it, and the modules and controllers on sale.

    Read Part 7

    All 7 parts

    1. Part 1SRAM and the Processor CachePublished
    2. Part 2DRAM From the InsidePublished
    3. Part 3What Could Follow DRAMPublished
    4. Part 4High Bandwidth MemoryPublished
    5. Part 5Current Memory ICsPublished
    6. Part 6CAMM2, LPCAMM2 and SOCAMM2Published
    7. Part 7CXL Memory ExplainedPublished

    Short on time

    Start with your question

    Each card jumps to the section of a guide that answers it.

    Memory in the data

    DRAM and HBM, sourced and dated

    The same records the timelines chart. Every point links to the paper, release or datasheet it came from.

    Die density, Gb, log scale0.1110200020102020

    Runs in your browserSourced chart

    DRAM Die Timeline

    SDR, DDR, LPDDR and GDDR dies by vendor, dated by the earliest public source, with the JEDEC DDR data rate line and every value linked.

    Try this: Switch to data rate, watch the JEDEC line step up, then click a die to see the release or datasheet behind it.

    Open DRAM Die Timeline
    dies
    88
    sources
    87
    first source
    1998
    Stack bandwidth, GB/s02k4k201520202025

    Runs in your browserSourced chart

    HBM Timeline

    HBM stacks by vendor and the accelerators that used them, charted by the date of the earliest public source, with the JEDEC standard line and each value linked.

    Try this: Compare stack bandwidth by vendor, then see which accelerators used each generation.

    Open HBM Timeline
    records
    44
    sources
    53
    first source
    2013

    Firsts

    The memory firsts in the data

    The earliest charted part to meet each test, dated by the earliest public source cited for it. It is not a claim about the whole industry.

    1. First DDR2 die, 2003

    3. First DDR4 die, 2011

    5. First HBM2 stack, 2016

    8. First DDR5 die, 2018

    9. First HBM2E stack, 2019

    10. First HBM3 stack, 2021

      Read: Atlas

    11. First DRAM die at 24 Gbit or more, 2021

    13. First DRAM die at 32 Gbit or more, 2023

    14. First HBM4 stack, 2025

      Read: Atlas

    15. First HBM4E stack, 2026

    The timelines page marks these on one strip with the storage firsts, and filters every record by maker and era. Open the timelines

    Hands-on

    Explore alongside

    The guides link these tools where they explain something you can try yourself.

    Interactive 3D reference

    Atlas

    Try this: Take an SSD or an HBM stack apart, from the package down to one cell.

    Open

    Simulator

    Parallelism Lab

    Try this: Scroll through the five presets, from one die to a mismatched controller and die, and watch which of the three bars is lowest.

    Open

    Continue on this site

    The memory map Beyond NAND Current memory ICs Timelines