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    Technical guide

    Photolithography

    How a chip is printed with light, why the light keeps getting shorter, what that means for DRAM and 3D NAND, how each die is tested before it is used, and how the dies are joined again in CoWoS and other advanced packages.

    A series in six parts that follows a memory chip from printing through test to packaging, starting with the step that decides how small a chip can be. Part 1 walks through one layer of the process: the wafer and the resist, the mask, the steppers and scanners that project it, the light they use, and how each layer is lined up on the last. Part 2 takes the resolution equation apart term by term, from mercury lamps and immersion lenses to multi-patterning and the tin-plasma light of EUV. Part 3 covers High-NA EUV and its half-size field, nanoimprint, and why DRAM took EUV while 3D NAND scaled by stacking instead. Part 4 tests the printed die: wafer sort, the known good die that stacking depends on, burn-in, final test and qualification. Part 5 is CoWoS in full: the reticle limit, the interposer and its three variants, the build steps, the lithography inside the package, HBM, and the capacity squeeze. Part 6 covers the rest of advanced packaging: InFO fan-out, Intel’s EMIB bridges and Foveros, hybrid bonding and SoIC, bonded 3D NAND and HBM, panels and glass substrates, and co-packaged optics. The stop motion below walks one layer through all 16 steps, from cleaning to the next film. The dated history of the tools lives in the lithography section of Fab Tracker; these guides explain how they work.

    Stop motion

    One layer, start to finish, as stop motion

    Before the layer

    Before: the wafer as it arrives

    Before: the wafer leaves storage with every earlier layer built and nothing yet on the new one.

    The wafer arrives from storage carrying every layer built so far, polished flat, with copper lines set into an insulating layer on top of the silicon. This pass adds one more layer on top of it. Wafers travel between machines in sealed pods called FOUPs, carried by vehicles on a rail in the ceiling, while filtered air falls from the ceiling and leaves through the floor.

    1. Leave storage. A robot lifts the sealed carrier out of the stocker.
    2. Set out for the line. The carrier is loaded onto the transport that runs between the machines.
    All 16 steps, before and after, as text
    1. Before: the wafer as it arrives. Before: the wafer leaves storage with every earlier layer built and nothing yet on the new one. The wafer arrives from storage carrying every layer built so far, polished flat, with copper lines set into an insulating layer on top of the silicon. This pass adds one more layer on top of it. Wafers travel between machines in sealed pods called FOUPs, carried by vehicles on a rail in the ceiling, while filtered air falls from the ceiling and leaves through the floor.
      • Leave storage. A robot lifts the sealed carrier out of the stocker.
      • Set out for the line. The carrier is loaded onto the transport that runs between the machines.
    2. Arrive and clean. The wafer arrives carrying the layers already built, and its surface is cleaned before anything new goes on. The RCA clean, first published in 1970, is still the pattern for wet cleans: one hot bath for oil and particles, a second for metal ions, and a rinse between them. A speck or an ion left here becomes a defect in every layer above it.
      • Lift off oil and particles. An alkaline peroxide bath, called SC-1, lifts organic films and particles off the surface.
      • Remove metal ions. An acid peroxide bath, called SC-2, strips the metal ions that SC-1 leaves behind.
      • Rinse and dry. Deionized water carries the chemicals off, and the wafer is spun or blown dry.
    3. Deposit the film. A thin film of the material this layer needs is deposited across the whole wafer. Each layer starts as a blanket film over the whole wafer. Sputtering suits metals, chemical vapor deposition builds dense insulators, and atomic layer deposition grows a film one atomic layer at a time when the surface is deep and narrow.
      • Load the chamber. The wafer goes onto a heated chuck and the chamber is pumped down.
      • Feed the source. A gas, a vapor, or a plasma-struck target supplies the atoms of the new film.
      • Film grows. Atoms settle on every exposed surface until the film reaches its target thickness.
    4. Dehydration bake. A few minutes at 130 to 160°C drives moisture off the surface; on most metal surfaces this bake is the whole preparation. A clean wafer still carries a thin film of water. Resist bonds poorly to a wet surface, so the wafer is heated first, and on most metal surfaces this bake is the whole preparation.
      • Heat on a hot plate. The wafer sits on a hot plate for a few minutes.
      • Moisture leaves. The water film evaporates and the surface is ready for resist.
    5. Prime. On silicon, oxide and nitride, HMDS (hexamethyldisilazane) vapor on a wafer heated to typically 120 to 150°C turns the surface water-repellent, so the resist sticks. Silicon, oxide and nitride hold water and shrug off resist. A vapor of HMDS reacts with the surface and leaves it water-repellent, which gives the resist something it can grip.
      • Hold at temperature. The wafer is heated inside a closed chamber.
      • HMDS vapor flows in. The vapor reacts with water bound to the surface.
      • Surface repels water. The primed surface now bonds to resist instead of water.
    6. Spin coat. Resist is dispensed at the center, spread at 500 to 1,000 RPM and thinned at 1,000 to 6,000 RPM. Spin coating sets the resist thickness. The film thins with the inverse square root of spin speed, so doubling the speed makes it about 1.4 times thinner. The spin usually takes 10 to 20 seconds, and right after it the film is still wet with solvent, which the soft bake drives out.
      • Dispense. A small puddle of liquid resist lands at the center of the wafer.
      • Spread. A slow first spin pushes the puddle outward over the whole surface.
      • Thin. A fast spin flings the excess off the rim and the film thins to its target.
      • Dry. Solvent evaporates as the wafer spins, and the film stops thinning.
    7. Edge bead removal. Spinning piles extra resist at the rim, and a solvent jet clears it from the edge. Resist piles up at the rim as it is thrown off. A raised ridge there would stick to handling hardware and shed flakes, so a solvent jet dissolves a narrow band at the edge.
      • Ridge at the rim. The spin leaves a raised bead of resist around the edge.
      • Solvent jet. A nozzle aimed at the rim dissolves the bead as the wafer turns.
      • Clean edge. The wafer is left with a narrow bare ring and resist across the rest.
    8. Soft bake. A few minutes at 90 to 120°C takes the film from 20 to 40% solvent by weight down to about 3 to 8%. The coat is wet enough to flow and smear. A short bake drives most of the solvent out, which locks the film in place and makes its response to light predictable.
      • Heat on a hot plate. The wafer is baked for a few minutes.
      • Solvent leaves. Most of the solvent evaporates out of the film.
      • Film firms up. The resist is now solid enough to handle and to expose.
    9. Load the reticle and align. The reticle goes into the scanner, which measures the alignment marks left by the layer below so the new pattern lands on top of it. Every layer must land on the one below it. The scanner reads small alignment marks printed on earlier layers, fits a map of the wafer’s position and distortion, and moves the stage so the new pattern falls where it belongs.
      • Load the reticle. The reticle for this layer is loaded into the scanner.
      • Read the marks. A sensor reads the alignment marks the layer below left on the wafer.
      • Fit the map. The scanner fits the wafer’s position, tilt and stretch from those marks.
      • Move to position. The stages shift so the reticle image lands on the old pattern.
    10. Expose (deep ultraviolet, DUV). A lens projects the reticle’s pattern onto the wafer four times smaller. The reticle sweeps through a slit of light while the wafer moves the other way; the reticle moves farther and faster. Then the wafer steps to the next field. Light passes through the clear parts of the reticle and a lens shrinks the image onto the resist. Where light lands, the resist chemistry changes, leaving a hidden latent image that is not yet visible.
      • Light through the slit. A narrow slit of deep ultraviolet light shines down through the reticle.
      • Stages scan opposite ways. The reticle and the wafer move in opposite directions under the slit.
      • Lens shrinks the image. The lens reduces the pattern before it reaches the resist.
      • Step to the next field. The wafer steps over and the scan repeats until every field is printed.
    11. Or expose with EUV. Increasingly, the most critical layers go to an extreme ultraviolet (EUV) scanner instead. It does the same job with mirrors instead of lenses and a reflective reticle, all in a vacuum, because EUV light is absorbed by everything, even air. EUV light is absorbed by glass and by air, so the whole optical path is mirrors in a vacuum. The reticle is a mirror too, with an absorber pattern that decides where light is reflected onto the wafer.
      • Tin plasma makes light. A laser vaporizes tin droplets, and the hot plasma gives off EUV light.
      • Mirrors gather it. A chain of curved mirrors collects the light and shapes the beam.
      • Reflect off the reticle. The reflective reticle sends back only the light the pattern allows.
      • Project onto the wafer. More mirrors shrink the image and place it on the resist.
    12. Post-exposure bake. Chemically amplified resists need a bake after exposure to finish the reaction the light started. In a chemically amplified resist, a photon makes one acid molecule, and heat lets that acid move a short distance and cut many bonds. The bake sharpens the latent image but, if it runs too hot or long, lets the acid blur the edges.
      • Heat the wafer. The wafer goes onto a hot plate right after exposure.
      • Acid spreads a little. The acid made by light moves a short way and triggers many reactions.
      • Solubility flips. The exposed resist can now dissolve in the developer.
    13. Develop. In a positive resist the exposed areas dissolve in the developer and wash away, leaving the pattern. The standard developer is 2.38% TMAH in water. It dissolves only the resist that light has made soluble, and a rinse and spin-dry stop the reaction before anything else can change.
      • Wet the surface. A first splash wets the wafer so the developer spreads evenly.
      • Developer puddle. A layer of developer sits on the wafer without spilling off.
      • Exposed resist dissolves. The soluble regions wash away and leave open channels.
      • Rinse and spin dry. Water stops the reaction and the wafer is spun dry.
    14. Inspect. Metrology checks the pattern, including overlay: how accurately this layer lines up with the one below. This is the last cheap place to catch an error. If the lines are the wrong width or the layer sits off its target, the resist can still be stripped and the wafer redone. After etch there is no going back.
      • Scan the pattern. A measuring tool images test structures across the wafer.
      • Measure line width. The width of printed lines is compared with the design.
      • Measure overlay. Marks on this layer and the layer below show how far they are offset.
      • Pass or redo. Wafers within tolerance move on; others have the resist stripped and redone.
    15. Etch or implant. The resist is now a mask. Etching removes the film wherever the resist is open. Or ions are driven into the silicon through the openings, while the resist protects the rest. The resist now works as a stencil. In a plasma etcher, chemistry and ion bombardment together cut straight down, while a thin film on the sidewalls keeps them from eroding. Process settings tune the shape: in a published DRAM etch simulation, raising simulated oxygen flow through 2, 3 and 4.5 sccm made the fin sidewalls steadily more tapered.
      • Plasma forms. A gas is energized into a plasma of reactive atoms and ions.
      • Ions hit the open floor. Ions strike the bottom of each opening and the chemistry removes what they loosen.
      • Sidewalls are protected. A thin film forms on the walls, which the ions barely touch.
      • Profile sets. The opening ends with straight or slightly tapered walls, depending on the recipe.
    16. Strip. The leftover resist is removed, for example in an oxygen plasma asher, where oxygen radicals turn it into gases that are pumped away. The resist has done its job and now has to go without harming what lies underneath. An oxygen plasma burns most of it away, and a wet clean removes the leftover residue.
      • Oxygen plasma ashes it. Oxygen atoms turn the resist into gases.
      • Gases are pumped out. The byproducts leave through the chamber exhaust.
      • Wet clean for residue. A chemical bath removes what the plasma left behind.
    17. Next layer. The patterned layer is done. Chips are built from dozens of layers, so the loop starts again with the next film and the next reticle. A finished chip has dozens of layers, and each one repeats this loop with a new film, a new reticle and new alignment marks. The pattern just made becomes the layer below for the next pass.
      • Clean again. The patterned wafer goes back through a wet clean.
      • Deposit the next film. A new film fills the gaps and covers the pattern.
      • Polish it flat. Chemical mechanical planarization polishes the new film back to a flat surface.
      • Coat and expose again. New resist goes on and the next reticle is aligned to this pattern.
    18. After: one layer patterned. After: one layer is patterned, and the wafer returns to storage to wait for its next trip around the loop. The layer is done: the film now has the shape the reticle drew, lined up with the layer below, and the resist is gone. The wafer goes back to the stocker to wait for its next trip, and the loop starts again.
      • Layer complete. The film is cut into the drawn pattern and aligned to the layer below.
      • Back to storage. The carrier returns the wafer to the stocker until the next layer.
    The 8 machines as text
    1. Wafer stocker. Holds sealed carriers of wafers between layers and hands each one to the transport that moves it from machine to machine. Racks of sealed carriers and a robot that loads and unloads them.
    2. Wet clean bench. Baths and rinses strip oil, particles and metal ions off the wafer before anything new goes on. An SC-1 bath, an SC-2 bath, a rinse tank and a dryer.
    3. Deposition chamber. Lays down the blanket film that this layer will be cut into. A heated chuck in a vacuum chamber, a gas box that feeds it, and a load lock.
    4. Coater and developer track. Spins resist on, bakes it, and later develops it. The scanner docks to its side, so the wafer passes straight through. A spin coater, a stack of hot plates, a developer module and a robot arm between them.
    5. DUV scanner. Aligns each field to the layer below and projects the reticle pattern onto the resist, one slit at a time. A reticle stage, a reduction lens, a wafer stage and alignment sensors.
    6. EUV scanner. Does the same job for the finest layers, using mirrors in a vacuum and light made from tin plasma. A tin-droplet light source, a mirror column, a reflective reticle stage and a wafer stage, all under vacuum.
    7. Metrology. Measures line width and overlay on the patterned resist, before it is committed to the film below. A measuring head over a precise stage, and a library of test structures to look at.
    8. Etch chamber. A plasma cuts the pattern down through the film wherever the resist is open. A plasma chamber with radio-frequency power, a gas box, pumps and an endpoint sensor.
    9. Plasma asher. Burns the used resist off in an oxygen plasma, ready for a wet clean. A plasma chamber, an oxygen supply and an exhaust pump.

    Schematic, not to scale: layer thicknesses are exaggerated. Drawn in the style of the Eyes on Flash fab floor.

    The series

    Read in order

    Each part builds on the one before, so start with Part 1.

    Light through a mask and a lens onto a waferA vertical light path: light falls on a mask with openings, a lens shrinks the mask's image, and the light converges onto a wafer where the pattern is printed smaller.PHOTOLITHOGRAPHY / PART 1Printing a chip with lightLIGHT · MASK · LENS · WAFERLIGHTMASKLENSWAFER

    Part 1

    How a Chip Is Printed With Light

    How a chip is printed with light: resist, masks, steppers and scanners, the wavelengths from mercury lamps to EUV, and how layers line up within a nanometer.

    Read Part 1
    An EUV light source: laser, tin droplet and collector mirrorA stream of tin droplets falls past a laser beam. Where the laser hits a droplet it turns into a glowing plasma, and a curved collector mirror behind it gathers the extreme ultraviolet light and focuses it to the right.PHOTOLITHOGRAPHY / PART 2Light from a drop of tinLASER · TIN · COLLECTORLASERTIN DROPLETSEUV LIGHTcollector mirror

    Part 2

    Resolution, From Mercury Lamps to EUV

    Why chips need ever shorter light: Rayleigh’s equation, immersion lenses, k1 tricks, multi-patterning, resist limits, and how EUV makes 13.5nm light.

    Read Part 2
    A full exposure field beside a High-NA half fieldTwo exposure fields drawn to the same scale. On the left a full field from a standard EUV scanner; on the right the High-NA field, the same width but half the height, with the full field outlined behind it.PHOTOLITHOGRAPHY / PART 3Half the field, finer linesFULL FIELD · HIGH-NA HALF FIELDFULL FIELDHIGH-NA HALF FIELD

    Part 3

    High-NA EUV and What It Means for Memory

    High-NA EUV’s anamorphic optics and half field, what comes after it, nanoimprint, and why DRAM took EUV while 3D NAND scaled by stacking instead.

    Read Part 3
    A GPU and HBM stacks on an interposer wider than one exposure fieldCross-section of a CoWoS package: a GPU die in the middle and a stack of HBM dies on each side sit on a silicon interposer on a package substrate. A dashed bracket shows one exposure field above the GPU, narrower than the interposer.PHOTOLITHOGRAPHY / PART 5Wider than one exposure fieldGPU · HBM · INTERPOSERONE EXPOSURE FIELDHBMHBMGPUINTERPOSERSUBSTRATE

    Part 5

    CoWoS in Full

    How CoWoS gets past the reticle limit: the interposer, the S, R, and L variants, the build steps, HBM beside the GPU, and the capacity squeeze.

    Read Part 5
    Two dies hybrid-bonded face to faceCross-section of two dies stacked face to face. Copper pads in the top die meet copper pads in the bottom die directly at the bond line, set flush in silicon oxide, with no solder bumps and no gap between the dies.PHOTOLITHOGRAPHY / PART 6Dies bonded face to faceCOPPER TO COPPER · NO BUMPStop diebottom die

    Part 6

    The Rest of Advanced Packaging

    InFO, EMIB and Foveros, hybrid bonding and SoIC, bonded NAND and HBM, panels and glass, and co-packaged optics: how chip scaling moved into the package.

    Read Part 6

    All 6 parts

    1. Part 1How a Chip Is Printed With LightPublished
    2. Part 2Resolution, From Mercury Lamps to EUVPublished
    3. Part 3High-NA EUV and What It Means for MemoryPublished
    4. Part 4How NAND Is Tested Before It ShipsPublished
    5. Part 5CoWoS in FullPublished
    6. Part 6The Rest of Advanced PackagingPublished

    On this site

    Where it connects

    The guides link these pages where they lean on them.

    • Fab Tracker

      Every lithography step by date, from KrF to High-NA EUV, with who bought each tool, and the EUV systems ASML sold.

    • Flash Foundations

      How 3D NAND is built, and why its hard part is etch rather than printing.

    • High Bandwidth Memory

      The DRAM stack that sits beside the GPU in a CoWoS package.

    • Glossary

      Chipmaking terms in plain words, filed by industry.

    Continue on this site

    Flash Foundations Beyond NAND Timelines