Photolithography, Part 5: CoWoS in Full

In the Photolithography series, Part 3 ended on a limit. A scanner prints one field at a time, and no single die can be bigger than that field. SI accelerators hit that wall years ago. Their answer is to build one product from several dies and connect them so closely that they behave almost like one chip. TSMC’s chip-on-wafer-on-substrate packaging, CoWoS, is the leading way to do that, and it puts the accelerator’s HBM in the same package. Part 4 showed for NAND why known good die testing matters here, because the yield of a stacked package is the product of the yields of the dies inside it. Market researcher TrendForce expects its CoWoS-L version to remain the mainstream packaging for SI chips through 2028. TrendForce figures on this page are its own reports, not TSMC’s.

The reticle limit

A scanner’s exposure field is 26mm by 33mm, as Part 1 showed, or 858mm². That is the largest die a front-end scanner can print in one exposure. High-NA halves the field. Large GPUs have run close to it since at least 2016. NVIDIA’s Tesla P100 of 2016 used a 610mm² die. Its Blackwell GPUs go past the limit by building one GPU from two dies, and every Blackwell product is two reticle-limited dies joined by a 10TB/s chip-to-chip link, 208 billion transistors in all, working as one GPU.

Splitting the work across dies only helps if they can talk as fast as one die’s parts talk to each other, and the memory has to be just as close. NVIDIA explained the move when it launched the P100, the first GPU with HBM2. Stacked memory gave more bandwidth, more than twice the capacity, and higher energy efficiency than off-package GDDR5. So the memory moved into the package as stacks of DRAM dies, connected to the GPU through a 4,096-bit memory interface and a passive silicon interposer, giving 720GB/s of peak bandwidth from 16GB. Wiring that wide and that short needs more than a circuit board can offer. Both chips need a piece of silicon underneath them, and that piece of silicon is the interposer.

What an interposer is

An interposer is a thin slab, usually silicon, that sits between the chips and the package substrate. Its top surface carries layers of very fine copper wiring that connect one die to another sideways, called redistribution layers (RDL). Copper-filled holes through the slab carry power and signals down to the substrate. These are through-silicon vias (TSVs). Tiny solder microbumps hold the dies on the interposer, and larger C4 (controlled-collapse chip connection) bumps hold the interposer on the substrate. An organic laminate substrate fans everything out to the board. Because the dies sit side by side rather than stacked, the arrangement is often called 2.5D.

Interposer wiring is far finer than anything a circuit board or package substrate can carry, and that is what lets a 4,096-bit memory interface be routed at all. An early CoWoS product shows the scale. A 2013 paper by John Lau and colleagues at Taiwan’s Industrial Technology Research Institute (ITRI) describes a Xilinx field-programmable gate array (FPGA) built from several dies. The interposer had four RDL layers at a minimum 0.4µm pitch, dies sat on copper-pillar microbumps at 45µm pitch, the interposer was about 100µm thick, and its TSVs were 10µm across. CoWoS entered volume production at TSMC in 2012. It is passive and carries only wires, though TSMC also builds deep-trench capacitors into it to steady the power supply.

Building one, step by step

Its name gives the order, with the chip going on the wafer first and then on the substrate. TSMC makes the interposer as a whole wafer and attaches the dies while it is still a wafer. Lau’s 2013 paper describes two TSMC flows, and this is the one without a temporary carrier. Current lines may differ by product. First the interposer wafer gets its TSVs, its top-side RDL layers, and the pads for the microbumps. Next the dies are bonded onto it, underfill fills the gaps under them, and the whole wafer is overmolded, with stress-relief walls between the dies to limit warping. Only then is the interposer ground down from the back, from more than 700µm to about 100µm, until the copper of the TSVs shows. C4 bumps go on the back, dicing splits the wafer into individual modules, and each module is attached to its package substrate and underfilled.

That order protects a fragile part. A 100µm silicon wafer is hard to handle on its own, and conventional TSV flows bond it to a temporary carrier wafer to thin it. In the carrier-free flow, the dies and the mold compound on top stiffen the wafer instead, so the temporary carrier is skipped, and the mold is also ground back from the top to expose the backs of the dies. Lau’s other TSMC flow removes the mold over the chips and bonds a temporary carrier before grinding. Testing matters for a related reason. A module with a GPU and several HBM stacks is only as good as its worst die. For HBM stacks, assembling only known-good dies is an important defense, and the same logic applies to the dies placed on an interposer.

Lithography comes back

An interposer is made in a fab, and it is made with lithography. Its TSVs are patterned in resist and then etched, its RDL layers are patterned like the upper wiring of a chip, and its bump pads are patterned too. Its features are coarse by front-end standards. ASML’s NXE EUV systems print features with a resolution of 13nm, and a 0.4µm pitch on the 2013 Xilinx interposer means lines and spaces of about 0.2µm, roughly fifteen times that. Interposers do not need the newest scanners. The silicon bridges in TSMC’s CoWoS-L carry several layers of sub-micron copper lines. Their metal types, layer counts, and pitches match those of CoWoS-S, according to TSMC. The RDL interposer of CoWoS-R uses a minimum 4µm pitch, 2µm lines and spaces.

Packaging’s harder lithography problem is size, not resolution. A silicon interposer of 3.3 reticle sizes is bigger than a standard scanner’s field, so a front-end tool cannot print it in one shot. Today’s packages of 3.3 reticle fields are mostly patterned on steppers with 4x reduction, according to the 2025 lithography chapter of the International Roadmap for Devices and Systems (IRDS). Steppers and scanners with a larger field, equal to four standard reticle fields, are ready for production with lines below 1µm. Anything bigger still needs several reticles stitched together, with the reticle management that brings. These packaging tools are derived from mature projection systems for front-end chips. For direct-write electron beam lithography, which needs no mask, the roadmap lists 150nm lines on a 300nm pitch with 45nm overlay in 2024 and projects 72nm lines by 2027.

CoWoS-S, -R, and -L

TSMC now offers three versions, and they differ in what the interposer is made of. CoWoS-S is the original and has been in production since 2012. It uses a full silicon interposer up to 3.3 reticle sizes, about 2,700mm². CoWoS-R has been in volume production since 2023 and replaces the silicon with an RDL interposer. That interposer is polymer and copper, which TSMC calls relatively flexible and says improves the integrity of the C4 joints. By TSMC’s account, the RDL and underfill layers buffer the different thermal expansion of chip and substrate, which greatly reduces strain in the C4 bumps. TSMC’s first CoWoS-L, at 3.5 reticle sizes, has been in volume production since 2024. TSMC recommends CoWoS-L or CoWoS-R for interposers above 3.3 reticle sizes. CoWoS-L builds on an RDL-based interposer and embeds local silicon interconnect (LSI) bridges in it. TSMC uses those bridges for high-density die-to-die links. The interposer itself is molded, with wide-pitch RDL layers on both sides.

Each of the three trades wiring density against size. A full silicon interposer gives the densest wiring everywhere, but a slab of silicon several reticles across is expensive, and TrendForce says manufacturing it is nearing its physical limits as chips grow and more HBM is added. An RDL interposer avoids the large silicon slab, but its wiring is coarser. CoWoS-L keeps silicon only for the bridges where a die meets its neighbor or its memory, so the package can keep growing. NVIDIA and AMD accelerators have already moved to CoWoS-L, according to TrendForce. CoWoS-S can hold two compute dies and eight HBM stacks, and TrendForce expects it to stay in use for custom chips such as Microsoft’s Maia 200.

HBM beside the GPU

Memory stacks on a CoWoS package are packages in their own right. Each HBM stack is a base logic die with DRAM dies stacked on top, connected vertically by TSVs and microbumps. NVIDIA said in 2016 that one 8Gb HBM2 die held more than 5,000 TSVs. Semiconductor Engineering’s 2026 reporting puts current stacks at 12 dies high, on their way to 16. Each die is now 30 to 50µm thick. The microbump pitch has been about 40µm and is moving closer to 10µm with HBM4.

The GeForce RTX 5090 runs on NVIDIA’s GB202 chip. The full GB202 has a 512-bit memory interface built from sixteen 32-bit memory controllers. That is half the width of a single HBM3E stack with its 1,024 data pins. Micron rates its own HBM3E at more than 9.2Gb/s per pin and more than 1.2TB/s per stack. NVIDIA’s Blackwell Ultra puts eight 12-high stacks around one GPU, with 288GB on an 8,192-bit interface at 8TB/s. Part 6 shows how each stack is built.

Height is the constraint. JEDEC had capped an HBM stack at 720µm, which was not high enough for 16 dies. It raised the limit to 775µm, enough room for HBM4 to keep using microbumps. Hybrid bonding joins copper pads directly with no bump, which removes the gap between dies. HBM4 was widely expected to need it for 16 dies, and the JEDEC change made that unnecessary for this generation. HBM5 and its successors are now expected to use it. The packaging company ASE told Semiconductor Engineering that it gives an order of magnitude lower energy per bit than microbumps. It also makes testing harder, because a probe can damage the pristine pad surface the bond needs.

HBM4 changes the base die too. With HBM4, companies are expected to specify custom base dies, according to Semiconductor Engineering. Some large companies, such as AMD and NVIDIA, plan to build more functionality into the base die. This guide reads that as making the memory stack partly the accelerator designer’s own product. That base die is a logic chip made with front-end lithography, sitting in a stack whose DRAM dies came from the processes Part 3 described, on an interposer made by the processes above.

Bigger every generation

CoWoS has grown in steps measured in reticle sizes. TrendForce’s November 2024 report, relaying TSMC’s 2024 European Open Innovation Platform forum, traces it from about 1.5 reticle sizes in 2016 to 3.3, with room for up to eight HBM3 stacks. As of that report, TSMC had committed to a 5.5-reticle version in 2025 to 2026 with up to twelve HBM4 stacks. A 9-reticle version, giving up to 7,722mm² for dies, was due for qualification in 2027. TSMC’s own page confirms the first CoWoS-L at 3.5 reticle sizes in volume since 2024.

Size brings its own problems. TrendForce reports that a 5.5-reticle package needs a substrate larger than 100mm by 100mm and a 9-reticle package one larger than 120mm by 120mm. Substrates that large affect power delivery and cooling, and it adds that liquid and immersion cooling will be needed for these processors. As package sizes grow, the wasted edge of a round wafer becomes a real cost, according to the IRDS, which is why companies are exploring rectangular panels instead of wafers. The roadmap also expects interposers to scale toward a full wafer. The same report says TSMC expects customers to stack 1.6nm-class dies on 2nm-class dies in the 9-reticle package with its SoIC bonding, which Part 6 covers.

The capacity squeeze

Demand for CoWoS jumped with the arrival of generative SI in late 2022, by TSMC’s account. TrendForce’s April 2026 report says CoWoS has been short since 2023. The shortage has spread upstream to production equipment and downstream to substrates and packaging materials. NVIDIA secured CoWoS capacity early along with wafers, HBM, and other parts. TrendForce expected the shortage to start easing slightly by 2027, helped by order spillover and TSMC’s plan to expand CoWoS capacity by more than 60% by 2027.

Pricing is the newest pressure, though so far only a report. Taiwan’s Commercial Times said on October 27, 2026, citing supply-chain sources, that foundry and packaging-house suppliers are preparing another CoWoS price increase, estimated at 10% to 20%. It also quoted industry sources saying equipment lead times have stretched from three to six months to six to eight. The report cites no confirmation from TSMC.

The squeeze has pushed alternatives forward. SPIL and Amkor, outside packaging houses that assemble chips for others, have taken overflow work, according to TrendForce. Interest in Intel’s EMIB, its embedded multi-die interconnect bridge for connecting chips side by side, has grown, in TrendForce’s analysis, as CoWoS-L’s larger interposer raises costs and TSMC’s capacity stays tight. By relying less on a costly large interposer, EMIB could lower packaging costs, though substrate wiring density limits its performance. Intel’s EMIB-T adds TSVs to the bridge to shorten signal paths. TrendForce expects Google to adopt EMIB-T in 2027. It still expects CoWoS-L’s maturity and yield to keep it the mainstream packaging for SI chips through 2028.

The scanner no longer decides how big an SI chip gets. In this guide’s reading, the reticle field caps each die, and the package decides how many dies sit together and how much memory they share. Part 6 covers the rest of that toolbox, including TSMC’s InFO and SoIC, Intel’s EMIB and Foveros, hybrid bonding, and the move from round wafers to panels.