Technical guide

Flash in Devices

The flash that ships inside a phone, a card, a car or a small board instead of an SSD: how each one talks to its host, what each version added, and what the device asks of it.

A series on the flash storage built into devices rather than sold as a drive. Part 1 covers UFS, the flash storage inside a phone: its layers, how it differs from eMMC and NVMe, the link gears, each version up to UFS 5.0, command queueing, how a read reaches the flash, and UFS cards and cars. Part 2 covers eMMC, the managed NAND on a parallel bus that phones used before UFS: its eleven wires, speed modes up to HS400, partitions, command queueing, real parts and why makers still sell it. Part 3 covers SD and microSD cards: the capacity families, bus modes from Default Speed to UHS-III and SD Express, speed classes, what is inside a card, endurance cards and fake-capacity cards. Part 4 covers automotive and industrial flash: temperature grades and AEC qualification, retention, endurance under constant logging, health and power-loss protection, the Tesla eMMC recall, and the move from eMMC to UFS and BGA SSDs in cars. Part 5 covers flash in phones and tablets: PoP, ePoP and uMCP packages, storage tiers that come with fixed RAM, and what Android’s memory manager, F2FS and file-based encryption do with the flash. Part 6 covers flash in small devices: SPI NOR and SPI NAND in routers, cameras, smartwatches and microcontroller boards, how a chip is split into partitions, and how bad blocks, wear and power loss are handled without a controller. How a flash cell stores a bit is in Flash Foundations; these guides start at the package and the interface.

The series

Read in order

Each part stands on its own; later parts compare back to UFS.

A host and a UFS device joined by serial lanesTwo blocks, the phone's host processor on the left and the UFS flash device on the right, joined by four serial lanes: two carry data to the device and two carry data back.GUIDE / MEMORY AND STORAGELanes that read and write at onceHOST · LANES · UFS DEVICEHOSTUFStwo lanes each way

Part 1

UFS Explained

How Universal Flash Storage works: its layers, eMMC and NVMe compared, M-PHY gears, versions 1.0 to 5.0, queueing, cards, cars and real parts.

Read Part 1
A host and an eMMC package joined by a parallel busTwo blocks, the host processor on the left and the eMMC package on the right, joined by a clock line, a command line and eight data lines. The data lines carry data in one direction at a time.GUIDE / MEMORY AND STORAGEOne shared bus, one way at a timeHOST · PARALLEL BUS · eMMCHOSTcontrollereMMCCLKCMDD0D1D2D3D4D5D6D7eight data lines, one direction at a time

Part 2

eMMC Explained

How eMMC works: a controller and NAND in one package on an eight-bit parallel bus, speed modes up to HS400, partitions, command queueing and real parts.

Read Part 2
A full-size SD card and a microSD card with their rows of pinsA full-size SD card and a smaller microSD card. The full-size card shows a first row of pins along its bottom edge and a second row above it, which UHS-II and SD Express cards add.GUIDE / MEMORY AND STORAGEOne row of pins, then a secondSD · MICROSD · PINSsecond rowfirst rowfull sizemicroSD

Part 3

SD and microSD Cards

How SD and microSD cards work: capacity families, bus modes from Default Speed to UHS-III and SD Express, what speed classes promise, and how to test for fakes.

Read Part 3
A soldered flash package between a vibration mark and a temperature scaleA ball grid array flash package with a controller and three NAND dies is soldered to a board. Zigzag lines on its left mark vibration. A bar of five steps on its right runs from cold at the bottom to hot at the top.GUIDE / FLASH IN DEVICESFlash that has to survive the carBGA PACKAGE · HEAT · COLD · SHOCKBOARDvibrationhotcold

Part 4

Automotive and Industrial Flash

Why cars and factories need different flash: AEC-Q100 and AEC-Q104 grades, retention, endurance under logging, power-loss protection and the Tesla eMMC recall.

Read Part 4
A phone processor with a DRAM package stacked on it and a flash package beside itA side view of a phone board. A processor package sits on the board with a DRAM package stacked on top of it. A separate flash package sits beside them. Copper solder balls join each package to the board.GUIDE / FLASH IN DEVICESDRAM on top, flash beside itLPDDR · FLASH · PoP · ePoP · uMCPBOARDLPDDRprocessorflash

Part 5

Flash in Phones and Tablets

How phone and tablet flash is packaged with LPDDR, from PoP to ePoP and uMCP, and what Android’s memory manager, F2FS and encryption do with it.

Read Part 5
Two bare flash chips on a board with a partition bar below eachTwo flash chips sit on a board, a small one on the left and a larger one on the right, each with gold pins along its top and bottom edges. Below each chip is a bar split into partitions: a small boot segment, teal segments for the kernel and root, and a copper segment for writable data.GUIDE / FLASH IN DEVICESFlash on the smallest boardsSPI NOR · SPI NAND · UBI · littlefsBOARD

Part 6

Flash in Small Devices

What routers, cameras, smartwatches and IoT boards boot from: SPI NOR and SPI NAND, partitions, bad blocks, UBI and power-loss handling.

Read Part 6

All 6 parts

  1. Part 1UFS ExplainedPublished
  2. Part 2eMMC ExplainedPublished
  3. Part 3SD and microSD CardsPublished
  4. Part 4Automotive and Industrial FlashPublished
  5. Part 5Flash in Phones and TabletsPublished
  6. Part 6Flash in Small DevicesPublished

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