Memory and Storage for SI, Part 4: Storage-Next and the 512-Byte Read

An SSD built for databases does the wrong amount of work for SI. NVIDIA announced Storage-Next on August 4, 2026, at the Future of Memory and Storage (FMS) conference in Santa Clara, California. Public talk of it goes back at least to NVIDIA’s GTC conference in 2025, according to StorageReview. By NVIDIA’s count, more than 40 storage and flash vendors are in it, among them Kioxia, Micron, and the storage-system maker DDN. Together they are working out how storage should behave when a GPU, not a CPU, asks for the data. The goal is the most 512-byte reads per second per GPU within power and tail-latency limits, in StorageReview’s account of the initiative.

This series covers memory and storage built for that demand. Its first three parts are about devices. Part 1 starts from memory as a synapse. Stacked flash meant to sit beside the GPU is in Part 2, and flash inside the processor’s own package is in Part 3. This part starts on storage, with the reads themselves and the drives meant to serve them. Beyond NAND, Part 2 explains the low-latency flash in those drives.

The memory stacked beside the GPU

Over 20 years, peak server compute grew about 60,000 times while DRAM bandwidth grew about 100 times, by Gholami and colleagues’ count. Accelerators close part of that gap with HBM stacked right beside the processor, and the amount of it is fixed for each GPU. Part 2 covers that limit in detail. NVIDIA’s Blackwell Ultra holds 288GB of HBM3E in eight 12-high stacks at 8TB/s, enough for models of more than 300 billion parameters to stay entirely on the GPU in NVIDIA’s account.

Adding more is costly at the wafer. Micron chief executive Sanjay Mehrotra told investors in March 2024 that HBM3E takes about three times the wafer supply of DDR5 to make the same number of bits on the same process, Tom’s Hardware reported. Photolithography Part 6 shows the extra steps behind that. Holes are etched through each die and filled with copper, the wafer is thinned, and then the dies are stacked and the gaps filled. Longer conversations and more of them at once outgrow that fixed space.

Why inference reads 512 bytes at a time

Data center SSDs are tuned for the 4KB random read. StorageReview reports that enterprise drives have been built around it for about a decade, to match databases and virtual machines, and that most controllers do roughly the same work to serve 512 bytes as to serve 4KB.

Inference asks for small pieces. Embeddings run a few hundred bytes and blocks of the key-value (KV) cache well under a kilobyte. That cache holds the attention state for every token a model has already processed, so it grows with each conversation’s length and with the number of conversations a GPU serves at once. In the standard design, the cache spills from GPU memory to system memory and then to flash, and because reading an evicted entry back costs less GPU time than recomputing it, it comes back as a stream of small random reads.

Serving a 512-byte request from a drive that works in 4KB units reads eight times the data the GPU wanted, since 4,096 / 512 = 8. That is 8x read amplification. At small sizes the count of operations runs out long before the drive’s bandwidth does, so Storage-Next measures input/output operations per second (IOPS) at 512 bytes rather than GB/s.

Taking the CPU out of the read

Every storage read has two parts. The data path moves the bytes, and the control path builds the request, submits it, and handles completion. GPUDirect Storage, which StorageReview says was introduced in 2019 and has been available since 2021, took the CPU off the data path through NVIDIA’s cuFile programming interface. It left the control path with the CPU, where for a 1MB read the cost disappears into the transfer. At 512 bytes the fixed cost of each request dominates and the CPU saturates before the drives do.

SCADA is short for scaled accelerated data access, and it moves the control path onto the GPU. NVIDIA describes it as a framework that lets GPUs pull only the data an application needs straight from storage into their own memory. Each GPU builds and completes its own requests and keeps many of them in flight at once, the same way it hides memory latency.

Direct access has a cost. Done carelessly, an application that talks straight to a drive can write over other programs’ memory, in NVIDIA’s account. NVIDIA’s answer, as it describes SCADA, is to give the fast path no special privilege, and to have a separate trusted component grant each application its approved storage at setup, through standard Linux security. DDN is integrating SCADA into its Infinia data platform for SI, according to NVIDIA.

NVIDIA is also opening the software. At FMS 2026 it said it is open-sourcing the cuFile interfaces and the storage stack beneath them, with Google, Intel, NVIDIA, and Meta as the first maintainers. The code is to live in a new GitHub organization, xio-sig. In a September 30, 2026 developer post, NVIDIA said it is expanding xio-sig to include its cuObject interface alongside cuFile. It also introduced a SCADA Server software development kit, so storage makers can build servers that answer requests sent by GPUs. The same post says the headers and library code will be published once the stack passes its conformance tests.

Storage-Next, the initiative and the name

Storage-Next sits alongside that software. NVIDIA calls it an initiative of storage makers, controller vendors, thermal and cooling groups, orchestration operators, and standards bodies. Their task is to agree how GPU-driven storage should behave, then turn that into open industry standards. Whether it becomes a neutral standard is still open. RCRTech points out that NVIDIA controls the core interfaces, the branding, the reference designs, and the certification programs behind it.

The name also covers a drive in some reporting. TweakTown reported on December 19, 2025, citing the Korean outlet Chosun, that “Storage Next” is NVIDIA’s name for an SSD from SK hynix. SK hynix, which is developing it with NVIDIA, calls it AI-N P. NVIDIA’s own pages use Storage-Next for the whole initiative, and this series follows NVIDIA.

A reference point: Micron’s 230 million IOPS

Micron showed one server at the SC25 supercomputing conference in St. Louis, Missouri, and invited visitors to its booth during the show, November 18 to 20, 2025. It reached 230 million 512-byte random reads per second under the SCADA programming model. Inside were 44 Micron 9650 PCIe 6.0 SSDs and three NVIDIA H100 GPUs, with linear scaling from 1 to 44 drives in Micron’s result.

Micron rates the 9650 at up to 28GB/s sequential read, and the 7.68TB model used in the demo at 5.4 million random read IOPS in its standard test rather than at 512 bytes. By that rating the demo reached about 97% of the drives’ combined figure, since 44 × 5.4 million = 237.6 million and 230 / 237.6 = 0.97. In bytes the result is modest. At 512 bytes each, 230 million reads come to about 118GB/s, and a little over four of those drives move that much reading sequentially (118 / 28 = 4.2). This server’s strength was the count of reads, and its single CPU was essentially idle, per StorageReview.

It took 44 drives, each rated at about 5.4 million reads per second, to get there. I think that’s the real lesson of the result. A server’s count of reads is set by its drives, so the next gains have to come from the drive.

Drives built for the small read

As of October 2026, Kioxia has rated one such drive and announced a faster demo, and SK hynix has a plan known through press reports. Three sources name 100 million IOPS per drive for later generations. Kioxia’s GP1 release gives it as an “up to” target, TrendForce has it for SK hynix, and StorageReview puts it on NVIDIA’s roadmap.

Source: Kioxia releases of August 3 and October 8, 2026; TrendForce, December 11, 2025, citing ZDNet and Hankyung; StorageReview, “NVIDIA SCADA Puts Storage Control on the GPU as cuFile Goes Open Source.” The enterprise range is Hankyung’s, and the PCIe 6.0 Micron 9650 in the previous section is rated higher, at up to 5.5 million at a standard block size. Only the GP1 rating and the GP demo state a 512-byte block size, and blank cells are not published.

Kioxia GP Series and XL-FLASH

Kioxia announced the GP1 Series on August 3, 2026, and FMS opened the next day. GP1 is a PCIe 6.0, NVMe 2.2 drive rated at up to 10 million random reads per second at a 512-byte block size. Its endurance rating is up to 50 drive writes per day (DWPD), and it comes in E3.S and E1.S form factors. Its pitch is a flash tier that extends HBM, so SI systems can reach larger datasets for less than the cost of more HBM. Kioxia expects evaluation samples for select customers by the end of 2026, and says the design is meant to scale to future generations targeting up to 100 million IOPS.

By Kioxia’s account, those numbers rest on the flash, and GP1 uses XL-FLASH generation 2. XL-FLASH is Kioxia’s low-latency flash, sold as a 128Gb die storing one bit per cell (single-level cell, SLC) and a 256Gb die storing two (multi-level cell, MLC). Kioxia’s figures give the family a 4KB page, 16 planes, and a read latency under 5µs, without saying which generation each belongs to. The 16-plane layout is there to cut latency, in Kioxia’s words, with shorter wordlines and bitlines than conventional flash.

Kioxia’s October 8 release said it would show an enhanced GP Series SSD on XL-FLASH generation 3 at more than 20 million 512-byte random reads per second. The demo was set for its booth at the Open Compute Project (OCP) Global Summit in San Jose, California, October 12 to 15, 2026, and no result from the show is published yet. That is at least twice the GP1 rating, from the next flash generation. It was announced as a technology demonstration rather than a product with a date.

SK hynix AI-N P

SK hynix’s drive is known only through reporting. TrendForce reported on December 11, 2025, citing the Korean outlets ZDNet and Hankyung, that SK hynix is building AI-N P on a redesigned NAND and controller architecture. It also reported a joint proof of concept with NVIDIA. Sample drives are due at 25 million IOPS over PCIe 6.0 by late 2026, in TrendForce’s report, which cites SK hynix Vice President Kim Cheon-sung. It says SK hynix aims to mass-produce 100 million IOPS versions by the end of 2027, with no block size for either.

What to watch

The end of 2026 is the first date to check, because Kioxia expects GP1 samples by then and SK hynix is reported to sample AI-N P. Per Kioxia, its samples are for functional checks only and may differ from production drives, so whether one drive can hold its rate under the tail-latency limits Storage-Next cares about waits for production hardware.

NVIDIA calls the cuObject libraries generally available, but until the cuFile and cuObject source is published on xio-sig, “open source” describes a plan.

My read is that Storage-Next will be judged less by its membership count than by whether drives from several makers behave the same way under SCADA. That’d also be the plainest answer to the neutrality question. The next part of the series follows the KV cache once it leaves the GPU. It covers where context memory lives between HBM and flash, and what NVIDIA’s storage designs put in that tier.