Flash Foundations, Part 4: 3D NAND Stacking

Planar NAND was running out of room to shrinkPlanar NAND stopped shrinking when cells grew so close that neighbors interfered and too few electrons stayed on each gate to tell levels apart.. Reliability fixes carried it to the 15nm node, after which the conventional scaling path could no longer be followed. At the time, the consensus had put the end of planar near 10nm. Planar NAND reached volume at 15nm and 16nm. After that the industry stopped shrinking horizontally and started building vertically.

Part 3 built the NAND hierarchy from cell to die. Cells wire into strings, strings share wordlines to form pages, and pages aggregate into blocks. This part covers how those strings are physically built once they stand on end, and what the third dimension cost. Every layer added since the first 24-layer stacks in 2013 has raised density and firmware complexity together.

A taller stack asks more of the firmware. String resistance and per-layer variationIn a tall stack the hole is narrower at the bottom than at the top, so cells on different layers differ in size and behave differently. get harder to manage as stacks get taller, and temperature shifts threshold voltageThreshold voltage, Vt, is the gate voltage at which a flash cell starts to conduct. The stored charge shifts it, and the controller reads data from it. (Vt) at every layer count.

The wall

Transistor geometries had been shrinking for decades, from 50nm to 34nm to 25nm to 19nm to 16nm. Each shrink packed more cells into the same silicon area, which drove down cost per gigabyte.

Physics set the limit. Neighbor interference grew with every shrink because electrons stored in one floating gate capacitively coupled with adjacent gates, shifting Vt.

Figure 4.1 draws the same 152nm of silicon width at three nodes. Five gates fit in the 15nm row where the 25nm row fits three, and every gap between neighbors is narrower. To see the effect, program the cells around a victim in the NAND Cell Lab’s neighbor coupling panel, first as a planar floating gate and then as a 3D charge-trap cell.

Each floating gate held so few electrons that losing a handful shifted the stored voltage state. The consensus put the end of planar near 10nm.

A few numbers show how fast the room ran out. Toshiba’s first NAND cell, published in 1987, measured 6.43µm². A 16nm cell reported by Micron in 2013 measured about 0.0013µm², nearly 5,000 times smaller (derived as 6.43 divided by 0.0013).

Along the way the cell passed through three isolation eras, starting with local oxidation of silicon (LOCOS) at 6 to 8F², then self-aligned shallow trench isolation with a wing on the floating gate at 5F², and ending with trench isolation without the wing at the 4F² ideal. Generations came roughly every 1.5 years.

Electrons per cell fell with the area. A NAND floating gate held about 500 electrons at the 45nm node, and each 100mV of threshold shift took about 40 electrons at 90nm against about 3 at 16nm. Compagnoni and colleagues reported single-electron charging of a NAND floating gate in 2015.

While the cell shrank, the films and voltages around it stopped scaling. The tunnel oxide stuck near 7nm, the interpoly dielectric near 10nm, MLC operating voltages near 25V, and the field between neighboring wordlines climbed past 10MV/cm. For a wrap-around cell, the control-gate fill became a trench with an aspect ratio above 10 at 15nm (an approximate reading from a published figure).

Figure 4.2 puts both trends on log axes. On the left, cell area fell with the square of the feature size, from 6 to 7F² in 1987 to about 5F² for the 16nm cell, a little above the dashed 4F² ideal. On the right, the electrons that move the threshold by 100mV fell from about 40 at 90nm to about 3 at 16nm. A 3D cell holds about 25 electrons per 100mV, about as many as a planar cell did at 70nm (27 on the chart).

Neighbor interference was the other cost, and an air gap between wordlines was the last tool against it. Total coupling to the eight neighbors fell from about 37% to about 25% at 25nm when an air gap was added, and a thin planar floating gate read about 28% at 20nm (approximate readings from a published figure). Micron shipped the thin-gate cell at 20nm. It had about 10nm of floating gate under a high-k dielectric and a metal gate, a window of ±8V and a program slope near 1.

Figure 4.3 shows the air gap buying about one node, since a wrap-around cell with a gap at 20nm matches the interference of the same cell without one at 25nm.

3D NAND arranges cells in vertical layers instead of spreading them across a flat plane. Rather than shrink the cell, manufacturers stack identical layers on top of each other. Toshiba presented BiCS, an early vertical-string design, in 2007. Its pipe-shaped successor stacked 16 layers, and one early cost estimate put the break-even of vertical NAND against planar near 32 layers. Production layer countsThe layer count is the number of cell layers in a vertical stack. More layers means more bits per unit of die area. began at 24 (Samsung’s first V-NAND), then climbed through roughly 32, 48, 64, 96, 128, 176 and 232, and the newest production generations run into the 300s (the vendor section lists them, as of October 2026).

In planar NAND, strings of cells ran horizontally across the silicon surface. In 3D NAND, strings run vertically through the stack, and a single string may pass through 232 layers in a two-deck die. Each layer holds a wordline that accesses the cells at that depth across all strings in that block. In Figure 4.4, standing the string on end fits eight cells in the footprint of one.

Adding layersAdding layers costs more deposition and etch steps per wafer, so the cost per bit falls only if the extra bits outweigh the extra process cost. raises density without requiring smaller cells. A 232-layer die holds roughly 3.7 to 3.9 times the data of a 64-layer die in the same footprint (derived from the ranges in the die density table). Cells in a vertical string are also larger and separated by deposited oxide rather than by lithography-limited lateral spacing, which eased the interference problem. Density comes mainly from adding layers, with smaller gains from tighter hole pitch and thinner layers. Cost moves from lithography to manufacturing, because every added layer must be deposited, etched and contacted.

How the stack is built: string formation

Tall-stack failure modes start with how the stack is made. A 3D string is not a planar cell tilted up. It comes from a different process, built around a channel holeThe channel hole is a tall narrow hole etched through the stack and filled to form a vertical string of cells. Etching it straight gets harder in tall stacks. through hundreds of layers. Planar NAND never had that structure.

Figure 4.5 gives the order. Deposition of alternating silicon oxide and silicon nitride layers comes first, one layer at a time. A 232-layer stack takes hundreds of these cycles before a single cell exists. Nitride layers are sacrificial placeholders, later replaced by metal wordlines, and oxide layers insulate between wordlines. Variation in layer thickness propagates through the stack, and the error rate of each layer ends up very different.

Next the fab etches vertical holes through the structure with a high-aspect-ratio etch, one deck at a time in today’s tall multi-deck stacks. Each hole becomes the channel for one NAND string, a narrow cylinder punched through hundreds of layers from the top of the stack to the source layer at its base. Lam Research puts the aspect ratio of 3D NAND holes above 40:1, against about 10:1 for planar NAND holes, and calls the channel hole etch one of the most challenging processes. Keeping a straight profile through each deck of a 300-layer stack, and aligning the decks, remains a central manufacturing challenge. Holes that bow, taper or lose their circular cross-section give strings inconsistent cells along their length.

Once the holes are etched, the inner wall of each receives the storage film. A blocking oxide layer against the hole wall keeps charge from escaping the nitride toward the gate. Then come a silicon nitride charge-trap layer and a thin tunnel oxide layer, through which charge moves during programming and erasure. This ONO (oxide-nitride-oxide) film covers the entire inner surface of the hole. A thin polysilicon liner forms the conducting channel, with an oxide core filling the center. Last, the fab removes the nitride placeholders and replaces them with metal in the replacement-gateIn the replacement-gate process the stack is first built with sacrificial layers, then those layers are etched away and replaced with metal wordlines. process. That metal wraps around the polysilicon channel at each level and forms the control gate of every cell in the string. This gate-last order is the one Samsung’s TCAT (Terabit Cell Array Transistor) process introduced in 2009. Toshiba’s original BiCS formed its polysilicon plates first, before the holes were etched.

Each new layer-count record takes more than extra deposition cycles. At greater depths the fab has to hold hole-profile integrity, coat an increasingly long and narrow channel with uniform ONO film, and form the metal wordlines without disturbing string structures already in place. These tolerances are why each new layer-count generation needs an extended yield ramp before die densityDie density is the bits stored per unit of die area, usually in gigabits per square millimeter. It is a better comparison across vendors than layer count. advantages translate into cost reduction.

Reaching every layer: the staircase

A string is a vertical channel, but every wordline layer is a flat plate, and every plate needs its own wire. Nothing at the top of the stack touches layer 37 directly. Cutting the edge of the stack into a staircaseThe staircase is the stepped edge of the stack where each wordline layer ends in a ledge, so a contact can reach it from above. solves it. Each layer has an exposed step, and one contact lands on it. Toshiba’s BiCS patent steps the ends of its lower plate layers so that each meets its own contact, and cuts the top layer into line-shaped bitline select gates.

Eight layers show the result in the upper panel of Figure 4.6. The fab makes the steps by trim-and-etch. It etches the stack, trims back the photoresist, etches again, and repeats, exposing one more layer each cycle. In theory one mask can make many steps, but the resist trim limits how far that goes, and the area the staircase takes grows in proportion to the number of layers. That area holds contacts and no cells, so every added layer costs die area. One proposal for vertical-gate 3D NAND contacts layers through a binary-sum scheme called minimal incremental layer cost (MiLC). Each mask etches through a different set of layers, so 8 layers need 3 masks instead of 8, and doubling the layers adds one.

Every layer’s wire has to leave the block within the width of the pillar rows that share one set of plates. Routing 16 layers within the pitch of two pillar rows is a different job from routing them across eight rows, and the lower panel of Figure 4.6 shows the job getting worse as layers are added. BiCS shares each wordline plate across a block of pillar rows. Program and read disturb spread along the plate in proportion to the pillars it carries, so the slits that cut plates into blocks trade density against disturb and block size. One 2008 proposal skipped the staircase. A review of 3D NAND architectures describes its VRAT structure, which exposes every wordline on one plane through chemical-mechanical planarization, so the wordlines need no layer-by-layer etching and no extra lithography step after stacking. The same review says the later VSAT design was aimed at the fabrication difficulties of VRAT.

How big is a cell?

Bigger than most people expect. A 3D NAND cell is larger than the planar cell it replaced. Density came from stacking a bigger cell once shrinking had run out.

Planar NAND ended with 15nm and 16nm parts from Toshiba and SanDisk, Samsung, SK hynix and Micron. A planar NAND cell ideally takes 4F² of silicon, where F is the feature size. At 15nm that is a square about 30nm on a side, roughly 0.0009µm² per cell.

Picture a 3D NAND cell as a ring of charge-trap film wrapped around a vertical channel hole, one wordline tall. In Samsung’s 32-layer V-NAND, TechInsights measured channel holes 120nm across before the films went in, lined with 22nm of ONO and 11nm of polysilicon channel. Each cell’s height is the wordline pitchVertical pitch is the thickness of one wordline layer plus its insulator. A smaller pitch fits more layers into the same stack height.. TechInsights measured it on eight production TLC dies from Samsung, SK hynix, Micron and Yangtze Memory Technologies Co. (YMTC), and it ran from 43nm to 58nm:

Figure 4.7 ranks the eight dies by pitch. The 176-layer and 232-layer dies from Samsung, SK hynix and YMTC have shorter cells than the same maker’s 128-layer dies, while Micron’s two dies tie at 56nm.

So each cell stands roughly 43nm to 58nm tall, depending on the vendor and generation. Its footprint is far larger than the planar cell’s. For Micron’s 176-layer die, TechInsights measured 0.020µm² per cell position, shared by 176 active wordlines, against about 0.0009µm² for one planar cell at 15nm.

Figure 4.8 puts both footprints at one scale. Footprint grew more than 20 times. Stacked cells now share it. In Micron’s 176-layer die, 176 active wordlines sit over each footprint. Micron’s 176-layer 512Gb die, at 10.27Gb/mm², holds about 18 times the data per square millimeter of the 19nm two-bit planar die in the density table (0.567Gb/mm², from 64Gb on 112.8mm²). The 3D die stores three bits per cell against two, and with that factor divided out the gain is about 12 times (derived as 18.1 divided by 1.5). The planar baseline is the 19nm die, an older generation than the 15nm cell in the footprint comparison. Periphery, wiring and the staircase take area that the cell footprintCell footprint is the die area one cell occupies. Planar cells are measured in F squared, while 3D cells share their area across the vertical stack. alone leaves out, so the die gains less than the cell stack suggests.

Hole layout matters as much as cell size. Holes on a square grid waste area, and staggering the rows into a honeycomb shortens the row pitch by 1 − cos 30°, about 13.4% (derived). Samsung’s first V-NAND used honeycomb holes at a 160nm pitch, about 120nm across at the top, with bitlines at a 20nm half-pitch. Staggering the bitline contacts as well put two bitlines on each pillar pitch in the second generation, which reportedly let it run a 16KB page, up from 8KB.

A bigger cell holds more charge per state and sits farther from its neighbors, and that is where 3D NAND got back the voltage margin planar NAND was losing at 15nm and 16nm. Density now comes from layer count and from squeezing the wordline pitch, which is why pitch keeps coming up in the problems of tall stacks. To watch one cell program, read and wear out, try the NAND Cell Lab.

Charge trap adoption: why most 3D NAND dropped floating gate

As of October 2026, nearly all 3D NAND produced uses charge-trap technology, with Solidigm the lone floating-gate holdout. That is a complete break from planar NAND, where floating gate dominated. Part 2 covers the mechanism. Charge-trap cells hold electrons in discrete sites in an insulating nitride instead of on a conductive polysilicon gate, so one oxide defect cannot drain the whole charge. Samsung’s V-NAND white paper and SK hynix’s 96-layer 4D NAND release both describe charge trap flash, and Micron moved to charge trap with its 176-layer generation. Kioxia’s release on a semicircular floating-gate cell compares the new design with its conventional circular charge trap cell, so that release confirms Kioxia’s standard BiCS cell is charge trap. Background text in a SanDisk Technologies patent describes the BiCS memory hole as filled with materials including a charge-trapping layer.

Two causes lower interference in 3D, geometry and process. Cell-to-cell interferenceCell-to-cell interference is the shift in one cell threshold caused by the charge of its neighbors, through capacitive coupling between the gates. falls in 3D mainly because the control gate wraps around the cell and shields it from its neighbors, and because the cell is physically larger. Floating-gate 3D cells show the same drop, so the insulating nitride is not the main cause. Samsung’s V-NAND white paper from 2014 marks 84% less coupling interference and 33% tighter natural threshold distributions than 1xnm planar NAND, and lists a page program time of 0.6ms against 2.0ms for a 21nm planar part. Process is the other cause. The nitride storage layer goes down as one continuous film on the hole sidewall, where a floating gate must be recessed and filled tier by tier.

Figure 4.9 shows the difference on the hole wall. At right, one deposition lays the charge-trap film for every wordline level. At left, floating gates are built separately at every level, and each tier adds an etch-back and a fill. That gap widens with every layer, and it is one reason charge trap scales vertically better than floating gate in the dimensions that matter for 3D production.

Charge trap had been tried in planar NAND first, and it did not reach volume there. Micron’s engineers report that in planar arrays the nitride and nanodot storage layers shared charge sideways between cells, so the immunity to stress-induced leakage, the main reason to want charge trap, was hard to realize. Erase also saturates. Electrons injected back from the gate meet the electrons being removed, so a charge-trap cell stops erasing about 5V higher than a floating-gate cell, and detrapping the nitride takes fields above 15MV/cm. Micron shipped a thin planar floating gate instead, as the wall section describes.

Three dimensions change that arithmetic, as Part 2 explains. The curved channel moves field from the blocking oxide to the tunnel oxide, and the wrap-around gate shields neighbors. A tunnel barrier built in layers lets holes cross at lower fields, as in the BE-SONOS stack. V-NAND pairs a SiON tunnel layer with a thin aluminum oxide, titanium nitride and tungsten gate.

Figure 4.10 plots the two fields against channel radius. Narrowing the channel from a 100nm radius to 5nm lifts the tunnel-oxide field from about 12 to about 26MV/cm and drops the blocking-oxide field from about 10 to about 6MV/cm. A channel under 40nm across enhances the field by more than 1.6, so a 7V pass voltage acts like 11V on a planar cell. That enhancement also worsens pass-voltage disturb. Ishiduki and colleagues report for pipe-shaped BiCS that a 90nm hole could not erase below 0V, while a 66nm hole reached −3V at a 22V erase bias.

Retention is the trade. A charge-trap cell loses charge by thermal emission, trap-assisted tunneling, sideways diffusion along the nitride and a fast initial loss in the first seconds after programming, and after cycling at high temperature it retains less than a floating-gate cell. One reason charge trap won anyway is that the film is simpler to build.

Some lateral charge migration along the shared nitride remains. Random telegraph noise (RTN) in a charge-trap string comes mainly from traps at polysilicon channel grain boundaries, and measured growth with cycling is modest (Part 2 covers RTN). Charge trap’s different retention and read disturb behavior also required firmware re-characterization across the industry.

One producer kept floating gateMost vendors moved from floating gate to charge trap when going to 3D, because the trap layer scales to vertical holes and tolerates defects better.. Solidigm now operates under SK hynix ownership after starting as the Intel NAND business, and it still builds 192-layer floating-gate NAND for quad-level cell (QLC) data center drives while its parent builds charge trap. Solidigm argues that floating gate suits QLC, a vendor position the vendor section covers.

Wordline metal: from tungsten to molybdenum

A wordline is a thin plate that runs the full width of the array, and its resistance sets how fast a program pulse reaches the far cells. Some early 3D NAND, notably Intel and Micron floating-gate designs, used polysilicon wordlines like planar designs. Polysilicon resistance was manageable at lower layer counts. As layer counts rose, Micron moved to a metal control gate. Micron’s reasons are unpublished, so the two constraints below are this page’s own reading of why.

The first constraint is wordline resistance, which grows with every added layer. A thin polysilicon wordline running the full width of the array in a tall stack accumulates enough resistance that the signal reaches far-end cells slowly, which hurts program time (tPROG). The second is wordline coupling. At high density, tighter wordline spacing increases the capacitive coupling between adjacent wordlines, which shifts Vt in cells that were not the programming target.

Replacement gate is the answer from the build sequence above, with metal where the sacrificial nitride was. Metal wordlines have far lower resistance than polysilicon, which restores tPROG at tall layer counts. Metal gates plus charge trap is what modern high-layer-count 3D NAND is. Samsung used a tungsten replacement gate from its first V-NAND generation in 2013, the gate-last flow of its TCAT process, which lowered wordline resistance against the polysilicon plates of the original BiCS. Micron followed with what it markets as Replacement Gate at its 128L and 176L generations. Samsung, SK hynix, Kioxia and Sandisk all build charge-trap NAND, and Goda writes that tungsten wordlines are commonly used in 3D charge-trap NAND. The vendor table below gives each maker’s wordline metal as reported.

Metal choice has become its own engineering frontier. Tungsten has been the dominant wordline metalWordline metal carries the gate voltage along each layer. Tungsten is standard, and molybdenum is being introduced because it has lower resistance in thin films., with lower resistance than polysilicon, compatibility with the gate replacement process and manufacturability at scale. Samsung’s 9th generation reportedly applies molybdenum in its wordline metallization instead of tungsten. Molybdenum has lower effective resistivity than tungsten in very thin films and needs no barrier layer, which allows thinner wordline layers for equivalent conductance.

Figure 4.11 draws two stacks with the same number of levels. Dropping the barrier film thins each level, so the molybdenum stack stands lower. TheElec reported that molybdenum can lower the layer heights by a further 30% to 40%. A shorter stack for a given layer count lowers the aspect ratio of the channel holes etched through it. Narrower and deeper holes are harder to keep straight without tilting or collapse, so a lower stack should help etch geometry, cell uniformity and yield (this page’s inference).

What layer counts don’t tell you

Layer count is the number every launch slide leads with, and it is a rough one. Vendors do not count the same things, and three more misconceptions about 3D NAND come up often enough to name directly.

Figure 4.12 shows what one string contains. Every vendor counts the data wordlinesVendors count layers differently, including dummy layers, decks and select gates, so a bigger layer number does not by itself mean higher density.. Some also count select gate and dummy layers in the total. Samsung’s first V-NAND shows the difference. Each string held 24 data wordlines, 2 dummy wordlines and 2 select gates, and the die was sold as a 24-layer part. Cell pitch and block architecture vary too, so two 176-layer parts can differ in storage density and manufacturing complexity. Layer number is a useful rough signal, but not a precise cross-vendor benchmark.

Not a pile of planar layers

Vertical channel NAND needs a completely different cell design, process flow and firmware calibration than planar. Piles of planar layers were built, though. Samsung built TANOS cells on stacked single-crystal silicon layers in 2006, Macronix stacked thin-film transistor layers the same year, and Samsung followed with a double-stacked 4Gb part. Each layer needed about three critical lithography steps, so cost grew with every layer added. Punch-and-plug processing, which etches and fills all layers at once, holds the critical lithography count constant.

Not automatically faster

Layer count sets potential die density. Read and write speed per layer, string resistance, and the controller’s ability to exploit parallelism across planes and channels set actual drive performance.

Not a node

For a CPU or GPU, a 5nm node is a generation label rather than a literal gate length, but it still implies transistor density and power scaling. For 3D NAND no equivalent single-dimension number exists. When a NAND vendor cites a node, it usually names a layer-count generation, as when Micron called its 176-layer NAND a node. A lithography dimension of the array is rarely what the word means. Die density in Gb/mm² at the same bits per cell is the directly comparable metric across vendors.

Die density and silicon economics

Layer count drives headlines, but die density tells the economic story. Gigabits per square millimeter (Gb/mm²) is the metric that matters, measuring how much storage capacity fits on a given area of silicon.

Figure 4.13 plots the table values below, with TLC, QLC and PLC separated. Density rises about 1.9 times from 128 layers to 232. The figure is derived from the table midpoints of 6.96 to 8.47 and 14.6 to 15.03, which are 7.7 and 14.8, and then 14.8 divided by 7.7. The QLC dies sit above the TLC dies at nearby layer counts. Vendors differ across the pairs, so the gap is more than the fourth bit. At 232 layers, 20.62 against 14.6 to 15.03 is about 1.4 (derived as 20.62 divided by the 14.8 midpoint). Layers can outweigh the fourth bit, as the 332-layer TLC die at 29 is denser than the 280-layer and 321-layer QLC dies at 28.5 and 28.8. The 332-layer QLC die at 37.6 tops the chart and the table, with both the extra layers and the fourth bit. Intel’s 192-layer floating-gate part is the one penta-level cell (PLC) die in the table, storing five bits per cell against three for TLC, so its density is not comparable with TLC dies at similar layer counts. It reaches 23.3Gb/mm², about level with the 321-layer TLC die at 23.52Gb/mm² with 129 fewer layers. Part 2 covers bits per cell. Layer count means different things at different vendors, so read the x axis as a rough guide.

The table lists the values behind the figure. A row without a QLC value has no QLC die in this table, though QLC dies may still be in production.

Die density determines cost per gigabyte, die size for a given capacity, dies per wafer and package capacity. A 300mm wafer at 14.6Gb/mm² carries about 130 terabytes of raw capacity before edge and yield loss (derived as 70,686mm² times 14.6Gb/mm², divided by 8). NAND economics come down to maximizing good bits per wafer.

This is why new NAND generations start expensive and become cheaper over time. Early production of any layer count has lower yields as engineers optimize the process. Mature production hits target yields, and cost per gigabyte drops. Semiconductor Engineering quoted analyst Mark Webb in 2020 saying vendors typically added 10% to 15% to wafer cost with each new generation.

How tall a stack can get

Layer count multiplies against layer pitch, and the product is the height a channel etch has to cut. Stack height is about the layer count times the wordline pitch, divided by the number of decks (derived). At a 55nm pitch, 350 layers stand about 19µm tall in one etch and about 9.6µm per deck with two decks. At 45nm the figures are about 16µm and 8µm. TechInsights measured production dies 6.6 to 12.4µm tall.

Figure 4.14 draws the four cases. Splitting the stack, thinning the pitch or doing both keeps each etch inside a depth the process can already hold, which is one reason deck counts rose with layer counts (this page’s inference).

Pitch has room to thin. Planar NAND reached a wordline pitch near 30nm, while the 3D stacks in that review sat at 50 to 60nm (Goda), so the plates could get thinner. Thinner plates worsen lateral charge migration in a nitride that is one continuous film, and one remedy is to confine the nitride to a separate piece for each cell. Taller strings also lose cell current, so channel mobility has to rise. Monocrystalline silicon channels, grown by epitaxy or by metal-assisted crystallization, have been demonstrated, and integrating them is still hard. A cell can also be cut in half sideways, into two half-wrapped cells, at the cost of some of the 3D size and shielding benefit. A smaller die leaves less area under the array for the CMOS, which is the second pressure toward bonded wafers.

Temperature, variation and resistance

3D NAND solved the density wall but introduced failure modes that planar NAND never produced. Each jump in layer count brings a predictable manufacturing problem, and firmware has to absorb the constraint the stack geometry adds. The table pairs the two by layer range, and the sections below take the physics behind each row. Firmware responses are illustrative, since vendors do not publish them. Read the rows as a progression. Early generations fight hole shape, middle generations fight film uniformity and resistance, and the tallest stacks fight alignment between decks and wafers.

Temperature

Temperature matters at every layer count, and firmware handles it alongside per-layer variation. During writes, the die generates heatTemperature differs across a die and between dies in a package. Simulations model a hotter end of the string, but any gradient inside the stack is unproven., mostly in its charge pumps and peripheral circuits. TechInsights measured stacks 6.6 to 12.4µm tall. Established gradients sit across the die and between dies in a package, driven by peripheral circuits and airflow. Simulation studies of designs with the peripheral circuits bonded against the array model a hotter end of the string, but they assume the gradient and do not measure it. A 2026 perspective preprint that has not been peer reviewed states that tall stacks show gradients of several kelvins across their height, hottest near the middle of a string, so treat that size as a claim to check. The field section covers what temperature does to Vt.

Process variation

Each layer in a 3D stack is deposited in sequence, then the channel holes are etched through the whole deck at once. Despite precise manufacturing, cells at different depths show different electrical characteristics, because oxide thickness varies, hole profiles taper and twist differently, and small alignment offsets build up across the stack. That shows up as per-layer electrical variation. Read reference voltages get tuned per layer or per wordline group, through NAND trim tables and firmware read offsets, rather than one threshold for the entire die. For programming, Samsung’s 48-layer die used a variable program pulse to cope with wordlines that differ.

Figure 4.15 exaggerates one cause. A hole that narrows toward the bottom gives the lower wordlines a stronger field at the same voltage, and the NAND Cell Lab’s taper panel shows how much lower their threshold voltage can start. In a model by Coventor, a Lam Research company, the sidewall of each layer has to stay steeper than 88° or the etch does not reach the bottom of the channel. That is why reads and programs use offsets per layer group instead of one setting for the die.

Taper also reaches the program side. Top cells are larger than bottom ones, and the smallest cell, at the bottom, sets the minimum. Yanagihara and colleagues report a workable layer pitch near 40nm, with 20nm of gate length and 20nm of spacing. Because the hole interrupts the wordline plate, wordline resistance and program transients differ by layer. Dies therefore trim programming as well as reads. A vertical-gate design (Hung and colleagues) used layer-aware program and read schemes against cross-layer process variation.

String resistance

String resistance increases directly with layer count. Reading a cell at any depth requires biasing every other cell in the string to conduct, so current has to traverse the full string length from drain to source. More layers mean more material and more resistance. Samsung’s ISSCC 2021 paper lists this as the first problem of scaling a NAND as the wordline stack grows. Cell-string current falls as string resistance rises, so reads need adjusted timing and voltage levels for reliable sensing. A string of n cells saturates at about the bitline voltage divided by (n − 1) times one cell’s on-resistance, so read current falls roughly as 1/n, and block size at a fixed page size grows with layer count. Published sensing studies put the sense target near 200nA, and a 24-layer 3D cell delivered about 20% of the current of a floating-gate cell. Vendors do not publish how each die compensates. Read timing, bias levels and per-die trim settings are the likely levers.

Wordline coupling

Wordline coupling is a well-documented constraint, and it is central to why firmware for tall-stack NAND is more complex than for earlier generations. When a wordline is programmed, the applied voltage stress extends to adjacent wordlines through capacitive coupling. With a wordline pitch of 43 to 58nm, part of it oxide, that coupling is substantial. Programming adjacent wordlines repeatedly accumulates stress that shifts Vt in cells that were not the target of the write. Die and controller manage this together, through a vendor-specified wordline program order (Part 5 covers it), multi-pass programming and on-die program pulse control. None of it is visible to the host.

String ends and deck junctions

Edge wordline disturbWordlines at the top or bottom of a stack, or next to a deck junction, see different fields than the rest and tend to show higher error rates. is the main string-end failure mode in 3D NAND. Cells at the top and bottom of a vertical string do not behave like the interior ones. Published work traces this to program disturb (Part 3 lists which cells take program and pass-voltage stress), a few channel effects, and the structures built into the string to contain them. Part 2 covers how gate-induced drain leakage (GIDL) erase began with Toshiba’s BiCS, whose channel pillars have no direct p-well contact. Lue and colleagues report a vertical-gate test chip that erased with about 13V on its source and bitline sides and about 6V on the select gates. Erase hole injection also shifted the select gates’ own thresholds, which a select gate free of traps was proposed to fix.

GIDL disturbs the first wordline

Part 2 explains the boosted-channel GIDL mechanism. At the string end, the select transistor beside the first wordline is off with a high voltage across its edge, and the hot electrons GIDL makes there can program the neighboring cell by accident. Edge wordline disturb has been analyzed in charge-trap NAND arrays since the planar days.

Dummy wordlines are the fix

A dummy cell sits between each select gate and the first data wordline and holds no data. It gives the die bias flexibility at the string edge and keeps the data cells away from the hot carriers. A review of program disturbance in 3D NAND explains why dummy layers are needed. With the floating channel boosted high, hot carriers at the string edge discharge it when the first wordline programs. Some designs also build the select transistor out of ordinary cells, so its threshold can be programmed instead of fixed by the process.

The channel floats, and it can go negative

After a read on a string with programmed cells, the wordlines fall from several V down to 0V. Once they drop below the programmed cells’ thresholds, the string cuts off and the floating channel couples down to about -5V. Planar NAND never sees this, because its channel sits on a p-well that supplies holes. A negative channel disturbs cells through the extra voltage across them, and the lateral field at the edge of the negative region injects hot electrons.

The polysilicon channel remembers

Positive gate bias during program and read traps charge in the poly channel, so Vt rises for a while. During idle the charge de-traps over time and temperature, which gives a Vt that depends on recent history. A thin channel that is fully depleted during read holds fewer traps. That logic also favors the hollow polysilicon channel with an oxide core.

Neither of the last two effects is confined to the string ends. They add history-dependent error everywhere, and the edges simply get the most of it.

Multi-deck string stacking is the manufacturing response to the practical limit on single-etch depth. Once the hole aspect ratio exceeds what a given process can reliably etch and coat with uniform ONO film, adding more layers and etching deeper becomes untenable. First the fab builds a set of layers, etches and fills the strings for that deckA deck is one tier of a multi-tier stack. Building two or more decks, one over another, keeps each etch shorter than a single very tall one., then deposits the next set above it and etches the strings for the second deck. Despite being formed in separate process stages, the two decks connect electrically to form a continuous string. Micron’s G8 at 232 layers etches its strings in two decks, one built on top of the other, as do Samsung’s 7th and 8th generations. Each deck junction adds an interface region where cell behavior can differ from the bulk of the stack, and per-layer voltage calibration is harder there.

Figure 4.16 marks where each pattern lives. In the field, edge disturb shows up as an error pattern that concentrates at the top and bottom of the strings, next to the select gates. If a drive shows systematic per-layer error elevation at string endpoints instead of spread evenly or centered on a mid-stack deck interface, the pattern is consistent with edge disturb. If errors cluster at one depth within the strings and do not spread uniformly across the block, the pattern is consistent with deck-interface process variation. Edge wordlines differ from interior ones by design, so location alone does not prove a problem. Telling disturb from those built-in differences means correlating the error depth with string position geometry and program/erase (P/E)A program/erase cycle is one write of a block followed by its erase. Each cycle wears the oxide, and the cell type sets how many cycles it tolerates. history, detail that only the drive vendor’s diagnostics can provide, so request it when escalating an anomalous error pattern.

Bonded interface architecture: the next structural step

CMOS-under-array (CuA) and periphery-under-cell (PUC)CMOS under array, called CuA or periphery under cell, places the control circuits beneath the memory array instead of beside it, saving die area. designs address the area-efficiency problem by placing the NAND’s peripheral circuits below the array on the same wafer instead of beside it. That uses the array footprint more efficiently than the original side-by-side arrangement. Intel and Micron’s floating-gate 3D NAND was the first CuA die, followed by a 768Gb 3-bit floating-gate die in 2016 (both appear in Goda’s review). It moved the page buffers and string drivers under the array, which let the polysilicon wordlines be cut into shorter segments. A deeper limitation persists. Array and circuits go through the same process flow on the same wafer, which forces compromises. Because the CMOS is built first, the thermal budget of forming the array above it restricts CMOS performance, according to Kioxia. Building both on one substrate means neither is fully optimized.

Bonded interface architecture is the answer, called CMOS bonded to array (CBA) by Kioxia and Xtacking by YMTCIn a CMOS bonded array the memory array and the control circuits are built on separate wafers and joined face to face. Xtacking is one such design.. Fabs build the CMOS wafer and the NAND array wafer separately, each on its own optimized process. Then they join the two with wafer-to-wafer hybrid bonding, using a dense array of copper-to-copper contact pads at the interface. The same bonding is being weighed for high-bandwidth memory (HBM), where reports forecast 16-high HBM4E as its earliest adoption; the last part of the Photolithography series covers it across advanced packaging.

Figure 4.17 compares the three placements. In the bonded design, the CMOS is the NAND die’s own peripheral circuitry: page buffers, decoders and charge pumps. It is not the SSD controller, which is a separate chip on the drive board and is never part of the NAND die. Only the placement of the die’s own logic moves.

The manufacturing advantages are real. CMOS can be fabricated on a more advanced, separately optimized process, free of the array’s thermal budget, which gives faster transistors for the circuits that control read and write operations. Meanwhile the array can be fabricated on a process optimized purely for cell storage density, without co-integrating logic devices in the same thermal and doping environment. They join through bonding, with bond pads at a pitch of a few microns spread across the full die area. Wafer-to-wafer bonding also carries a known-good-die cost. Wafers are joined whole, without sorting the dies first, so known-bad dies cannot be skipped and a bad die on either wafer kills its good partner on the other, and the yield of the pair is the product of the two yields (derived). Die sizes and pad layouts must match as well. Bonding sorted dies onto a wafer avoids that loss and lets die sizes differ.

Bonding is now being tried on the cell arrays too, which makes it an answer to the etch limit as well as to the periphery problem. A perspective preprint describes wafer-on-wafer bonding that stacks two complete cell arrays over one peripheral CMOS wafer. Each array is etched on its own, so capacity roughly doubles without a deeper channel etch. That matters because the paper puts channel etch aspect ratios above 60:1 in today’s tall stacks. It points to two lab demonstrations. One is a 900-layer die made by bonding two 450-layer cell wafers, and the other bonds two 218-layer arrays. It has not been peer reviewed, so it reads as a statement of where the research is heading and not as a product; Part 10 files it under research.

Bonded interfaces can add a distinct class of failure mode at the bond. Wafer bonding already sat in image sensors. TechInsights compared the likely DBI bonded interface in YMTC’s 3D NAND with the one in Sony’s IMX260 stacked image sensor, which uses that process. Applying direct wafer bonding to the cost and volume requirements of NAND storage only began with YMTC’s 64-layer Xtacking parts, which TechInsights found in 2020, and Kioxia’s 8th-generation BiCS. Field data on long-term reliability of high-density bonded interfaces in consumer and enterprise NAND is still accumulating. Bond-interface failures may not look like classic monolithic 3D NAND failures, and host-side telemetry alone may not reliably separate a bond-interface delamination event from a string-formation defect or a CMOS peripheral fault. That takes vendor-level diagnostics. Which vendors build bonded NAND today is in the vendor section.

In the field: thermal failure patterns

Temperature differences across the NAND dies and packages in a drive produce failure patterns that can appear anomalous without context. A drive running a sustained sequential write workload may show elevated error rates on specific logical address ranges while the rest of the drive stays healthy. That pattern may not indicate a defective block in the traditional sense. It may indicate that the flash translation layer (FTL)The flash translation layer is the firmware that maps host addresses to physical flash locations and hides the rules of erase blocks and wear. placed that data on physical blocks, on hotter dies or packages, that took disproportionate thermal stress during the write session. This reading is an inference from the cross-temperature results below.

Cross-temperature effects are the mechanism. Data written hot and read cold, or the reverse, shows a shifted Vt, and temperature also affects charge retention and error rates (Part 2 covers the physics). Firmware that ignores temperature sees a higher raw bit error rate (RBER)Raw bit error rate is the fraction of bits read from the NAND that are wrong before error correction is applied. on some dies and in some read conditions, with no physical defect to explain it.

Figure 4.18 orders the first checks. Well-implemented firmware stripes writes across dies and channels for parallelism and wear leveling, which also keeps heat from concentrating. When that distribution works, wear and temperature exposure are spread evenly enough that no region drifts past what error-correcting code (ECC)Error-correcting codes add parity bits to each block of data so the controller can find and fix bit errors on read. and read retryRead retry rereads a failed page with the read reference voltages shifted, trying a table of offsets until the data decodes. can absorb. When garbage collection (GC)Garbage collection copies the valid pages out of mostly stale blocks and erases those blocks, so there is always free space for new writes. runs continuously during heavy random-write workloads, write amplification rises and the drive runs hotter overall, so wear and heat build faster in whatever blocks stay active. Over time, data written in those hot regions loses charge faster during retention and reads worse when checked back at a different temperature, which shows up as higher RBER.

Typically a drive looks healthy under light or idle conditions but shows progressively elevated media error counts tied to sustained write sessions, often surfacing later when that hot-written data is read back or relocated by GC. If Percentage Used is moderate (the vendor’s endurance estimate is not exhausted) and media errors climb during write sessions, thermal effects are one possible cause alongside a weak die or plane. Investigation starts with workload characterization, and drive replacement can wait. Part 8 lists the SMART fields these checks read.

Knowing which NAND is in a drive tells a field engineer the firmware’s baseline assumptions about cell behavior. Two drives with the same layer count from different vendors may show different read retry sequences and different RBER baselines at equivalent P/E cycle counts. Thermal throttle behavior comes mostly from the controller firmware and the drive’s cooling design. Cell physics differs by vendor, and so does the firmware calibrated to it.

The manufacturer landscape and supply concentration

As of October 2026, Samsung, Kioxia (in a joint development partnership with Sandisk, spun off from Western Digital in 2025), Micron and SK hynix account for most 3D NAND sales. YMTC is a significant and growing factor but carries geopolitical constraints that affect its availability in certain markets.

This concentration has direct implications for procurement and supply chain risk. A drive OEM sourcing NAND from any one of these suppliers is exposed to that supplier’s production ramp timelines, yield events, pricing dynamics and allocation priorities. TrendForce reports Samsung at 29.3% of NAND revenue in Q2 2026 and Kioxia at 13.6%. Dividing the other brands’ reported revenue by the market size that Samsung’s share implies gives about 18% for SK Group (SK hynix plus Solidigm), 15% for Micron and 11% for Sandisk.

Figure 4.19 shows those shares. YMTC does not appear in TrendForce’s branded revenue tables, and revenue share is not the same as wafer capacity. These figures shift with pricing cycles. An OEM tied to a single supplier absorbs that vendor’s allocation and pricing swings with no alternative to lean on.

Each vendor takes a distinct architectural approach that matters beyond layer count. The table sets them side by side, and the sections below add what the table cannot hold.

Samsung

Samsung’s V-NAND uses its charge-trap flash (CTF) structure in a TCAT vertical string design, with peripheral logic beneath the array in its COP (Cell-on-Peri) layout. Samsung’s vertically integrated model, with fab, controller and SSD assembly in-house, allows tight co-optimization between the NAND and the firmware that manages it. Samsung’s 8th generation is reported at 236 layers, with Toggle DDR 5.0 at 2,400MT/s. Toggle is a NAND interface family (Part 5 covers it), and megatransfers per second (MT/s)NAND bus speed is the transfer rate between controller and die, in megatransfers per second. It sets a ceiling on per-channel throughput. is its I/O speed.

Samsung’s 9th generation entered mass production in 2024 with Toggle DDR 5.1 at 3,200MT/s, and a QLC model was to follow in the second half of the year. Samsung’s mass-production announcements give no layer count. Its ISSCC 2024 paper on a 1Tb QLC die in this generation is titled as a 280-layer part, at 28.5Gb/mm². Samsung unveiled its 10th generation V10 BV-NAND at FMS 2026, with more than 400 layers and a wafer-bonding architecture.

Kioxia and Sandisk

Kioxia’s BiCS (Bit Cost Scalable) is the result of a long-running joint development with Western Digital, now Sandisk. Its 218-layer generation uses the bonded design from the bonded interface section, with the CMOS and array fabricated on separate wafers and then bonded. The 332-layer BiCS10 generation began sampling in July 2026 with a Toggle DDR 6.0 interface at 4,800MT/s, and mass production is targeted for 2027.

That joint model means both Kioxia-branded and Sandisk-branded products use the same underlying NAND. Kioxia NAND is also available to third-party drive OEMs, which makes it common in drives built on Phison and Silicon Motion (SMI) controllers.

Micron

Micron moved to metal wordlines late, with Replacement Gate at its 128L and 176L generations, as the wordline metal section describes. Its 176L and 232L generations pair that gate with a CuA layout, which recovers die area that side-by-side placement wastes. Micron’s current G9 generation has 276 layers and continues the same architecture. Micron’s NAND is available to third-party OEMs and widely used in drives across consumer and enterprise segments.

Micron’s next generation is bonded. At its October 2026 technology webinar, Micron described G11 as more than 400 layers made by wafer-on-wafer bonding, without saying which wafers it joins (the bonded interface section covers both kinds). Micron puts G11 at about twice G9’s bit density, up to 1.5 times its I/O speed and more than 25% less energy per bit moved, and targets the volume ramp for the second half of 2027. For the generations after G11, it named a breakthrough high-mobility material and a denser cell architecture without giving dates.

SK hynix

SK hynix markets its 3D NAND as 4D NAND, reflecting a PUC design that places peripheral circuitry beneath the array rather than alongside it, which increases active array area on the die. SK hynix says it has made 238-layer NAND since June 2023, as the industry’s first 238-layer provider. Its 321-layer NAND entered mass production in November 2024, with customer shipments planned for the first half of 2025, and a 2Tb QLC variant followed in August 2025. SK hynix says this made it the first 300+ layer NAND in mass production. It has also demonstrated a wafer-bonded 375-layer NAND slated for enterprise SSD mass production in 2027.

YMTC

YMTC (Yangtze Memory Technologies Co.) is the fifth major NAND producer and the only one operating outside the established Japan-U.S.-South Korea supply chain. Its Xtacking architecture places CMOS peripheral logic on a separate bonded wafer, similar in principle to Kioxia’s CBA but developed independently. Its X3 generation reached 232 layers. Among YMTC’s milestones is a consumer SSD launch under the Zhitai brand. TechInsights wrote that the commercial market for YMTC’s 3D NAND is mostly limited to mainland China. Tom’s Hardware reported a target of 15% of the NAND market by late 2026, which is a target and not a measurement.

Solidigm

Solidigm is the floating-gate exception among the vendors, and it has operated under SK hynix ownership since SK hynix acquired the Intel NAND business. Solidigm points to three decades of floating-gate experience and frames floating gate as a deliberate fit for QLC, citing a strong voltage threshold window and strong cell isolation. Those are the vendor’s claims. It still uses SK hynix charge-trap NAND for some drives while it keeps developing floating gate for high-capacity QLC, including its planned 245TB-class SSD.

Die grading and substitution

Fabs sort every die by quality, and two drives with one model number can carry different NAND. Part 3 covers die grades, and The Field Practicalities covers a real case.

What the stack hands to the controller

3D stackingInstead of shrinking cells sideways, 3D NAND stacks layers of cells vertically, so capacity grows by adding layers rather than by smaller features. added a vertical dimension to the established hierarchy but did not change its fundamentals. Strings still connect cells in series through a shared vertical channel, a wordline still selects every cell at its layer in the block at once, and blocks still require full-block erasure.

On a real drive, the stack shows up as per-layer read offsets, errors that concentrate at string ends or at a deck junction, reads that depend on temperature, and NAND whose firmware baseline depends on the vendor. Page-block asymmetry makes GC necessary, and that is unchanged. Firmware now tracks far more state, and more complex state, than it did on planar parts.

Managing all of this takes a processing system that can run firmware algorithms across many NAND channels at once while holding up the host interface contract. Part 5 covers that controller SoC, including how it manages channel parallelism, processes NVMe commands, and runs the firmware that turns this three-dimensional medium into a reliable block storage device.