Glossary

A 1-2-4 coding assigns bits to voltage levels so the lower page needs one read reference, the middle two, the upper four. Gray code keeps neighbors one bit apart.

Taught in Part 3: From Cell to Die

3D DRAM stacks DRAM cells in layers on one die, the way 3D NAND does, instead of shrinking them further across a flat array.

Taught in Working Memory, Part 3: What Could Follow DRAM; also in Working Memory, Part 4: High Bandwidth Memory

Instead of shrinking cells sideways, 3D NAND stacks layers of cells vertically, so capacity grows by adding layers rather than by smaller features.

Taught in Part 4: 3D NAND Stacking

3D XPoint is the memory in Intel’s Optane products. Each cell stacks a phase change memory element on an ovonic threshold switch selector.

Taught in The Memory Map: What Comes After Flash

An SI accelerator is a processor built for the vector and matrix math of SI models, such as a GPU, which does far more of that math than a CPU.

Taught in Working Memory, Part 4: High Bandwidth Memory

An access trace is a record of the reads an application makes, which tells a defrag or caching tool which data matters.

Taught in Defrag Lab

An access transistor is the switch that connects one memory cell to its bit line when the cell’s word line rises, so only the selected row is read or written.

Taught in Working Memory, Part 1: SRAM and the Processor Cache; also in Working Memory, Part 2: DRAM From the Inside, Working Memory, Part 3: What Could Follow DRAM

An activate command opens one row of a DRAM bank, copying its cells into the sense amplifiers so columns can be read or written.

Taught in Working Memory, Part 2: DRAM From the Inside

An actuator is the arm assembly that moves a hard drive’s read and write heads across the platters. A dual-actuator drive splits the heads between two arms that can work at the same time.

Taught in How Storage Works, Part 2: How a Hard Drive Works

Adaptive firmware changes its behavior as the drive ages, for example by adjusting read voltages and refresh rates from measured conditions.

Taught in Part 10: The Future of Flash

AES encrypts data in fixed-size blocks, and a mode such as XTS decides how each block of a longer run is encrypted.

Taught in AES Engine Lab

AHCI, the Advanced Host Controller Interface, is the register-level interface that SATA drives use, built around a single command queue of 32 entries.

Taught in Part 1: Standards & Interfaces

Ambient temperature is the temperature of the air around a drive.

Taught in Throttle Lab

Anamorphic optics shrink the mask pattern more in one direction than the other, which lets High NA EUV keep standard-size masks but halves its exposure field.

Taught in Photolithography, Part 2: Resolution, From Mercury Lamps to EUV

Areal density is how much data a hard drive platter stores in a given area of its surface. Raising it is how makers fit more data on each platter.

Taught in How Storage Works, Part 1: The Memory and Storage Hierarchy; also in How Storage Works, Part 2: How a Hard Drive Works

An argon fluoride excimer laser is the deep ultraviolet light source behind the most advanced lithography before EUV, used both dry and with water immersion.

Taught in Fab Tracker

The Arrhenius equation relates temperature to the speed of charge loss, so a short bake at high temperature stands in for a long time at normal temperature.

Taught in Part 8: Error Correction & Integrity; also in Throttle Lab

ATA Security Erase Unit is a command a SATA drive runs on itself to erase its user data, with the drive deciding how.

Taught in A Secure Erase Does Not Make an Old SSD Like New; also in Secure Erase Lab

Available Spare is a health value showing the percentage of spare blocks remaining. The drive warns when it falls below a set threshold.

Taught in Part 7: Garbage Collection & Wear; also in Do SSDs Wear Out in a Couple of Years?, Does an SSD Fail With No Warning?

AWUN and AWUPF report the largest write the drive guarantees to complete entirely or not at all, for normal operation and after power failure.

Taught in Part 6: The Flash Translation Layer

Background garbage collection reclaims space during idle time, so that foreground writes do not have to wait for it.

Taught in Part 7: Garbage Collection & Wear

Blocks that fail at the factory or in use are recorded in a bad block table and replaced from spare blocks, so the drive keeps its capacity.

Taught in Part 6: The Flash Translation Layer; also in Secure Erase Lab

A bank is an independent array inside a DRAM die with its own sense amplifiers. Different banks can work on different rows at the same time.

Taught in Working Memory, Part 2: DRAM From the Inside; also in Working Memory, Part 4: High Bandwidth Memory

A bank group is a set of DRAM banks that share some internal circuits. Commands to different bank groups can follow each other faster than commands within one group.

Taught in Working Memory, Part 2: DRAM From the Inside

The base die sits at the bottom of an HBM stack and connects the DRAM dies above it to the processor. It holds the interface and test logic and can carry logic of its own.

Taught in Working Memory, Part 4: High Bandwidth Memory; also in Memory and Storage for SI, Part 2: High Bandwidth Flash, Atlas

BiCS FLASH is Kioxia’s name for its 3D NAND. It stacks control gate plates between insulator layers, punches holes through them in one step and fills them to form cells.

Taught in Memory and Storage for SI, Part 2: High Bandwidth Flash

A bipolar resistive cell sets with one voltage polarity and resets with the opposite one, as most oxide resistive cells do.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

A bit is a single binary digit, a zero or a one. Eight bits make a byte.

Taught in AES Engine Lab

Bit demand is how many memory bits buyers want in a period, the side of the market that bit growth has to meet.

Taught in The Memory Cycle

Bit growth is how much the total number of memory bits shipped rises from one period to the next. It measures supply in bits, not in chips or dollars.

Taught in The Memory Cycle

Bit slicing spreads one weight across several cells that each hold part of it, then adds the partial sums with shifts to get more levels than one cell can hold.

Taught in Crosspoint Lab

A bitline is the wire that runs across many strings and carries the sensed signal to the page buffer. Cells on one wordline share it in turn.

Taught in Part 3: From Cell to Die; also in Crosspoint Lab

A cell storing n bits needs 2 to the power n voltage levels: two for SLC, four for MLC, eight for TLC and sixteen for QLC.

Taught in Part 3: From Cell to Die; also in The Memory Map: What Comes After Flash, Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar

A block is the smallest unit that can be erased. It holds hundreds to thousands of pages, so one erase clears megabytes of data at once.

Taught in Part 3: From Cell to Die; also in Follow a Read

The block retirement rate is how quickly blocks are removed from service. A rise signals that the flash is wearing out faster than expected.

Taught in Part 7: Garbage Collection & Wear

Board power is the maker’s rated power draw for a whole graphics card, GPU and memory together, which sets the power supply and cooling it needs.

Taught in Best GPUs

BCH is an algebraic code that corrects a fixed number of bit errors per codeword. It was standard for flash until error rates outgrew it.

Taught in Part 8: Error Correction & Integrity

Burst length is how many data transfers one DRAM read or write command delivers back to back on the bus.

Taught in Working Memory, Part 2: DRAM From the Inside

Burst performance is what a drive does in the first seconds, helped by caches. Sustained performance is what it holds once those are used up.

Taught in Part 9: Performance & Endurance

A processor cache is a small SRAM memory on the processor die that copies main-memory data the processor will likely need soon. Each added level is bigger and slower.

Taught in Working Memory, Part 1: SRAM and the Processor Cache

The cache cliff is the sudden drop in write speed when the SLC cache is full. A fuller drive has a smaller cache, so the cliff comes sooner.

Taught in Part 9: Performance & Endurance; also in Once the Cache Fills, the Drive Stays Slow, QLC Is Junk

A cache line is the block of neighboring bytes a cache stores and moves as one unit. When the processor needs any of them, the whole line is loaded.

Taught in How Storage Works, Part 1: The Memory and Storage Hierarchy

A cache register holds the next page on a NAND die, so it can arrive over the bus while the previous page is still programming.

Taught in Parallelism Lab

Capacitorless DRAM stores its charge in a transistor instead of a separate capacitor, removing the storage capacitor’s area, one of the main obstacles to shrinking DRAM cells.

Taught in Working Memory, Part 2: DRAM From the Inside; also in Working Memory, Part 3: What Could Follow DRAM

Capital expenditure is money a company spends on fabs and tools that will produce for years. Memory makers raise it to add supply, which arrives only once the fabs are built.

Taught in The Memory Cycle

CAS latency is the number of clock cycles between a read command to an open row and the first data coming out of the DRAM.

Taught in Best RAM

Cell footprint is the die area one cell occupies. Planar cells are measured in F squared, while 3D cells share their area across the vertical stack.

Taught in Part 4: 3D NAND Stacking

Cell-to-cell interference is the shift in one cell threshold caused by the charge of its neighbors, through capacitive coupling between the gates.

Taught in Part 4: 3D NAND Stacking

The channel hole is a tall narrow hole etched through the stack and filled to form a vertical string of cells. Etching it straight gets harder in tall stacks.

Taught in Part 4: 3D NAND Stacking

Channel hot-electron injection programs a cell by accelerating electrons along the channel until some gain enough energy to jump the oxide. NOR flash uses it.

Taught in Part 2: The Physics of Flash

Most vendors moved from floating gate to charge trap when going to 3D, because the trap layer scales to vertical holes and tolerates defects better.

Taught in Part 4: 3D NAND Stacking

A charge-trap cell holds electrons in discrete traps in an insulating nitride layer instead of on a conductive gate, so one defect cannot drain the whole charge.

Taught in Part 2: The Physics of Flash

A checksum is a short value calculated from a block of data and stored apart from it, so a later read can show whether the data has changed.

Taught in Running a NAS, Part 2: Pools and Filesystems on a NAS

In a chemically amplified resist, each absorbed photon releases an acid that catalyzes many reactions instead of one, usually during a post-exposure bake. It was first developed for DUV.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

A channel is a bus from the controller to a group of dies. Chip enable lines select which die on the channel is addressed.

Taught in Part 5: The Controller; also in Follow a Read, Parallelism Lab

Packaging mounts finished dies on a substrate, connects them and seals them, turning bare silicon into a part a circuit board can hold. Advanced packaging joins several dies in one package.

Taught in Fab Tracker

Chip-off recovery removes the NAND chips from a drive and reads them directly, without the controller.

Taught in Secure Erase Lab

A chiplet is a small die made to be joined with other dies in one package, so a chip can be built from parts made on different processes or by different makers.

Taught in Photon Fabric

The CHIPS Act, the Creating Helpful Incentives to Produce Semiconductors for America Act, is the US law under which the Commerce Department funds new chip fabs in the United States.

Taught in The Memory Cycle

Ciphertext is data after encryption. Without the key it looks like random bytes; with the key it turns back into the original plaintext.

Taught in AES Engine Lab

A cleanroom is a room whose air is filtered so finely that dust too small to see cannot settle on a wafer and spoil the chips on it.

Taught in Fab Tracker

NIST’s media sanitization guideline names three levels: Clear uses normal writes, Purge goes beyond them with methods such as block erase or crypto erase, and Destroy makes the media unusable.

Taught in Secure Erase Lab

Clock scaling lowers a clock rate to save power, either the controller clock or the NAND interface rate.

Taught in Throttle Lab

In a CMOS bonded array the memory array and the control circuits are built on separate wafers and joined face to face. Xtacking is one such design.

Taught in Part 4: 3D NAND Stacking; also in Memory and Storage for SI, Part 2: High Bandwidth Flash

CMOS under array, called CuA or periphery under cell, places the control circuits beneath the memory array instead of beside it, saving die area.

Taught in Part 3: From Cell to Die; also in Part 4: 3D NAND Stacking

Co-packaged optics puts the parts that turn electrical signals into light inside the same package as a switch or processor, so the electrical path shrinks from inches to millimeters.

Taught in Photon Fabric

A codeword is a block of data bits plus the parity bits computed from them. The code rate is the share of the codeword that is data.

Taught in Part 8: Error Correction & Integrity

A complementary resistive switch puts two cells back to back so the idle pair always reads high resistance. Reading destroys the stored value, which must then be written back.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

Compliance current is a cap on the current a resistive cell may pass while it sets, which stops the filament growing and helps fix how low the resistance ends up.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

The composite temperature is the single temperature an NVMe drive reports for itself. The maker decides which sensors feed it and how.

Taught in Every NVMe SSD Needs a Heatsink; also in Throttle Lab

Computational lithography models how a mask will print, from tool and test-wafer data, and deforms the mask pattern on purpose so the wafer gets the intended shapes.

Taught in Photolithography, Part 2: Resolution, From Mercury Lamps to EUV

CXL runs over the same physical layer as PCIe but adds cache-coherent memory access, so it moves cache lines rather than blocks of storage.

Taught in Part 10: The Future of Flash; also in The Memory Map: What Comes After Flash, Working Memory, Part 3: What Could Follow DRAM

A condition number says how much a matrix magnifies small errors in the matrix or inputs into large errors in the answer. A large number means an ill-conditioned problem.

Taught in Crosspoint Lab

Conductance is the inverse of resistance, a measure of how easily a cell passes current. Current equals conductance times voltage.

Taught in Crosspoint Lab

A conductive filament is a thin path that forms through the insulating layer of a resistive cell when it sets and breaks when it resets.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

Content-addressable memory is searched by value instead of by address: every stored word is compared with the search word at once and the matching rows are reported.

Taught in Crosspoint Lab

A contract price is what large buyers such as PC, phone and server makers pay under negotiated memory deals, usually reset each month or quarter, as opposed to the spot price of single trades.

Taught in Market Board

A control loop measures a value such as temperature, compares it with a target and adjusts an output such as speed, over and over.

Taught in Throttle Lab

The controller and firmware can be read from the drive identify data, the vendor tools or the markings on the chip.

Taught in Part 5: The Controller

A controller reset restarts a drive’s controller while the host keeps running. The drive is unavailable until it finishes.

Taught in Throttle Lab

The controller is a system on a chip with CPU cores, hardware engines, memory and interfaces to both the host and the NAND.

Taught in Part 5: The Controller; also in Working Memory, Part 4: High Bandwidth Memory, Throttle Lab

Conventional magnetic recording writes a hard drive’s tracks side by side without overlap, so any track can be rewritten on its own.

Taught in How Storage Works, Part 2: How a Hard Drive Works; also in Running a NAS, Part 1: NAS Operating Systems Compared, Running a NAS, Part 9: NAS Problems Found Too Late

A core die is one of the DRAM dies stacked above the base die in an HBM stack.

Taught in Working Memory, Part 4: High Bandwidth Memory

The cost curve follows cost per gigabyte as die density rises, through more layers and more bits per cell. Public per-generation figures are scarce.

Taught in Part 10: The Future of Flash

CoWoS is TSMC’s packaging that places a processor and its HBM stacks side by side on a shared silicon interposer.

Taught in Working Memory, Part 4: High Bandwidth Memory; also in The Memory Cycle

The critical dimension is the size of the smallest feature a lithography system can print. The two main ways to reduce it are a shorter wavelength of light and a higher numerical aperture.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light; also in Photolithography, Part 3: High-NA EUV and What It Means for Memory

A critical shutdown is a drive stopping itself, with no further answers to the host, to avoid heat damage.

Taught in Throttle Lab

Cross-temperature effects appear when data is written at one temperature and read at another, which shifts the threshold voltages and raises the error rate.

Taught in Throttle Lab

A crossbar array is a grid of parallel word lines crossed by parallel bit lines, with one memory cell at every crossing.

Taught in Crosspoint Lab

Cryptographic erase destroys the media encryption key, which makes all data encrypted under it unreadable without erasing the flash itself.

Taught in Part 5: The Controller; also in A Secure Erase Does Not Make an Old SSD Like New, Secure Erase Lab

CrystalDiskMark is a simple disk benchmark program for Windows that measures sequential and random read and write performance.

Taught in DRAM-Less SSDs Are Slow; also in Storage and Memory in Practice, Part 3: SSDs for Builders, The Speed on the Box Is the Speed You Get

A CXL memory module is a Type 3 CXL device: a memory expander the host reaches over CXL.io and CXL.mem, without the CXL.cache link accelerators use.

Taught in Part 1: Standards & Interfaces

CXL carries three protocols on one link: CXL.io for device control, CXL.cache for coherent caching by a device, and CXL.mem for host access to device memory.

Taught in Part 1: Standards & Interfaces; also in Beyond NAND, Part 2: Phase-Change Memory and Optane

A cyclic redundancy check is a check value sent with data so the receiver can detect errors. On a PCIe link, a failed check makes the sender replay the data.

Taught in Networking for SI, Part 3: DPUs and SmartNICs as Storage Engines; also in UFS Explained: The Flash Storage Inside Your Phone

A deck is one tier of a multi-tier stack. Building two or more decks, one over another, keeps each etch shorter than a single very tall one.

Taught in Part 4: 3D NAND Stacking

Deep ultraviolet (DUV) lithography prints with ultraviolet light from krypton fluoride or argon fluoride excimer lasers, the generations before EUV, and focuses it with lenses rather than mirrors.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

Each added bit per cell halves the spacing between voltage levels, which raises capacity and lowers the number of program/erase cycles the cell survives.

Taught in Part 2: The Physics of Flash

Deposition coats the wafer with a thin film of conducting, insulating or semiconducting material, which lithography and etch then pattern into the next layer.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

Depth of focus is the range of focus error a lithography process can tolerate and still give acceptable results. In high-NA EUV it shrinks as numerical aperture rises, which makes the process more sensitive to focus errors.

Taught in Photolithography, Part 2: Resolution, From Mercury Lamps to EUV; also in Photolithography, Part 3: High-NA EUV and What It Means for Memory

Device variation is the spread between cells meant to hold the same value, both from cell to cell on one chip and from chip to chip.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

A die is one chip cut from a finished wafer by a diamond saw. Dies differ in size, so one wafer may hold a few dozen or thousands.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

A die collision happens when two commands need the same die and one has to wait. A deeper queue spreads work over more dies and so lowers collisions.

Taught in Part 5: The Controller

Die density is the bits stored per unit of die area, usually in gigabits per square millimeter. It is a better comparison across vendors than layer count.

Taught in Part 4: 3D NAND Stacking

The sequencer is a NAND die’s own control logic. It runs an operation from the command it holds, sets the die busy and drives the word and bit lines.

Taught in Follow a Read

A differential pair stores one signed weight in two cells and subtracts their currents, one cell for the positive part and one for the negative.

Taught in Memory and Storage for SI, Part 1: Memory as a Synapse; also in Crosspoint Lab

A diode selector sits in series with each cell and passes current one way only, so idle cells can be reverse-biased instead of held at a partial voltage.

Taught in Crosspoint Lab

Direct memory access lets a device such as an SSD read or write the host’s memory on its own, without the processor copying each byte.

Taught in How Storage Works, Part 1: The Memory and Storage Hierarchy

DirectStorage is a Windows API that lets games load data from storage with less CPU overhead. Later versions add GPU decompression, so the graphics card unpacks game assets.

Taught in A Gen5 SSD Loads Games Faster

DNA data storage writes data as sequences of synthetic DNA and reads it back by sequencing. It packs data very densely but is slow and costly to write.

Taught in How Storage Works, Part 3: Tape and Cold Archive

A doorbell is a register on an NVMe drive. Writing the new tail of a queue there tells the drive a command is waiting.

Taught in Networking for SI, Part 5: CXL and SDXI Where They Touch Storage; also in Follow a Read

Double data rate memory moves data on both the rising and the falling edge of the clock. DDR also names the line of PC memory standards, numbered by generation.

Taught in Working Memory, Part 2: DRAM From the Inside; also in Working Memory, Part 4: High Bandwidth Memory

DRAM stores each bit as charge on a tiny capacitor behind one transistor. The charge leaks away, so every cell must be refreshed many times a second, and the data is gone when power is removed.

Taught in Working Memory, Part 2: DRAM From the Inside; also in Working Memory, Part 3: What Could Follow DRAM, Memory and Storage for SI, Part 2: High Bandwidth Flash

An SSD’s DRAM is fast volatile memory beside the controller that holds the map and writes on their way to flash. It loses its contents when power drops.

Taught in Power Loss Lab

A DRAM cell is one access transistor and one storage capacitor. Reading it drains the capacitor onto the bit line, so every read is followed by a write back.

Taught in Working Memory, Part 3: What Could Follow DRAM; also in Working Memory, Part 4: High Bandwidth Memory

DRAM timings are the minimum waits between commands: tRCD from opening a row to reading it, tRP to close it, and tRAS for how long a row must stay open.

Taught in Working Memory, Part 2: DRAM From the Inside; also in Working Memory, Part 3: What Could Follow DRAM

A DRAM-less SSD has no DRAM of its own inside the drive. It can use the NVMe host memory buffer feature to borrow some of the computer’s memory instead.

Taught in DRAM-Less SSDs Are Slow

Drive writes per day is the number of times the full capacity can be written each day for the warranty period, which equals TBW divided by capacity and days.

Taught in Part 2: The Physics of Flash; also in Part 9: Performance & Endurance, Beyond NAND, Part 2: Phase-Change Memory and Optane

A DIMM is a memory module: a small board of DRAM chips that plugs into a slot on the motherboard.

Taught in Working Memory, Part 2: DRAM From the Inside; also in Working Memory, Part 4: High Bandwidth Memory

Dynamic range is the ratio between the highest and lowest conductance a cell can be set to, and it limits how many distinct weights one cell can hold.

Taught in Memory and Storage for SI, Part 1: Memory as a Synapse; also in Crosspoint Lab

ECC exhaustion is the order of recovery steps as errors grow: normal decode, read retry, soft decode, die-level parity, and finally an uncorrectable error.

Taught in Part 8: Error Correction & Integrity

Wordlines at the top or bottom of a stack, or next to a deck junction, see different fields than the rest and tend to show higher error rates.

Taught in Part 4: 3D NAND Stacking

Electrochemical metallization memory, also called conductive-bridge memory, builds and dissolves a metal filament from one electrode across an insulating layer.

Taught in Crosspoint Lab

Electronic codebook mode encrypts every block on its own with the same key, so equal blocks give equal ciphertext and patterns show through.

Taught in AES Engine Lab

An eMMC is managed NAND flash for mobile applications: flash memory and its controller in one embedded memory system. Its parallel interface sends data one direction at a time.

Taught in eMMC Explained: The Flash Storage Inside Cheap Devices; also in SD and microSD Cards: Classes, Bus Modes and SD Express, UFS Explained: The Flash Storage Inside Your Phone

An ePoP is a single memory package that holds mobile DRAM, eMMC flash and a controller, stacked directly on the mobile processor.

Taught in Flash in Phones and Tablets: One Board, Two Memories

An encryption key is the secret that steers a cipher. With AES the same key both encrypts and decrypts.

Taught in A Secure Erase Does Not Make an Old SSD Like New; also in AES Engine Lab

Energy per bit is the energy a link spends to move one bit, usually given in picojoules. Lower is better, since it sets how much bandwidth fits in a chip’s power budget.

Taught in Photon Fabric

ePMR is Western Digital’s perpendicular recording with an electrical current applied in the write head, which makes the head switch faster and more consistently, with no laser.

Taught in How Storage Works, Part 2: How a Hard Drive Works

EDSFF, the Enterprise and Datacenter Standard Form Factor, defines the E1.S, E1.L and E3 shapes built for dense, hot-swappable server storage.

Taught in Part 1: Standards & Interfaces

Flash cannot overwrite a page in place. The cells must first be erased to the lowest level, and erase works only on a whole block.

Taught in Part 3: From Cell to Die

Error-correcting codes add parity bits to each block of data so the controller can find and fix bit errors on read.

Taught in Part 2: The Physics of Flash; also in Part 3: From Cell to Die, Part 4: 3D NAND Stacking

Etch removes material from the wafer wherever the resist pattern leaves it open. Dry etch does it with gases, and wet etch with a chemical bath.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

An excimer laser energizes a mix of two gases until their atoms briefly join into excited molecules, which give up the energy as deep ultraviolet light.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

exFAT is the file system that SDXC and SDUC cards come formatted with, in place of the FAT file systems that smaller cards use.

Taught in SD and microSD Cards: Classes, Bus Modes and SD Express

The exposure field is the area of the wafer one exposure can pattern. A chip larger than the field has to be printed in sections and stitched together.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

An extent is the file system’s record of one fragment: where the run starts and how long it is.

Taught in Defrag Lab

EUV lithography prints with light of a far shorter wavelength than deep ultraviolet, made by striking droplets of tin with a laser. It needs mirrors and a vacuum instead of lenses, and ASML is its only maker.

Taught in Fab Tracker; also in What a Gigawatt Takes

A fab is a chip factory: cleanrooms full of tools that turn bare wafers into finished chips, step by step over weeks.

Taught in Fab Tracker

Fibre Channel is a network built for storage that links servers to disk and flash arrays over optical fiber or copper, the long-running backbone of data center storage networks.

Taught in Photon Fabric

A file fragment is one run of consecutive addresses holding part of a file. A file stored in three runs has three fragments.

Taught in Defrag Lab

The file table is the file system’s list of which files exist and where they live. Deleting a file removes its entry and leaves the data in place.

Taught in Secure Erase Lab

With file-based encryption, each Android user has Credential Encrypted storage, available only after unlock, and Device Encrypted storage, which is available during Direct Boot as well.

Taught in Flash in Phones and Tablets: One Board, Two Memories

A fiscal year is the twelve-month period a company reports on. It often differs from the calendar year, so the same quarter name can mean different months at two companies.

Taught in The Memory Cycle

The flash translation layer is the firmware that maps host addresses to physical flash locations and hides the rules of erase blocks and wear.

Taught in Part 3: From Cell to Die; also in Part 4: 3D NAND Stacking, Part 5: The Controller

F2FS is a log-structured file system built for NAND flash storage such as SSDs, eMMC and SD cards.

Taught in Flash in Phones and Tablets: One Board, Two Memories

Flexible Data Placement lets the host direct writes into separate groups of blocks by lifetime, which lowers garbage collection work without changing the block interface.

Taught in Part 10: The Future of Flash; also in Defrag Lab

FLIT mode, introduced with PCIe 6.0, sends data in fixed-size units protected by forward error correction instead of variable-length packets.

Taught in Part 1: Standards & Interfaces; also in Part 10: The Future of Flash

A flit is the fixed-size unit a newer PCIe link sends in place of packets of varying size, so error correction can work on blocks of one size. Several packets can share a flit, and one packet can span several flits.

Taught in How Storage Works, Part 4: PCIe Gen6 and Gen7 for Storage

A floating-gate cell stores data as charge on a conductive polysilicon layer that is fully insulated, so the charge stays after power is removed.

Taught in Part 2: The Physics of Flash

Force Unit Access makes one write reach stable media before completing. Flush makes all earlier writes stable, and both give the host a durability guarantee.

Taught in Part 6: The Flash Translation Layer; also in A Power Cut Does Not Wipe Your SSD, Follow a Read

Format NVM is the NVMe command that reformats a namespace. Its secure erase setting asks the drive to erase user data directly or by deleting an encryption key.

Taught in Secure Erase Lab

Forming is a one-time, higher-voltage pulse that creates the first conducting path in a fresh resistive cell. Afterwards the cell switches at lower voltages.

Taught in Crosspoint Lab

Forward error correction adds extra bits to data as it is sent, so the receiver can fix some bit errors itself without asking for the data again.

Taught in How Storage Works, Part 4: PCIe Gen6 and Gen7 for Storage

A foundry makes chips that other companies design, selling manufacturing rather than chips of its own.

Taught in Fab Tracker; also in The Memory Cycle, Market Board

Fowler-Nordheim tunneling is the quantum effect that lets electrons pass through the tunnel oxide when a strong electric field thins the barrier.

Taught in Part 2: The Physics of Flash; also in Beyond NAND, Part 1: NOR and Memory on the Processor Die

The free block pool is the set of erased blocks a drive keeps ready to take new writes.

Taught in Defrag Lab

fsync is the call an application makes to ask the operating system to make its writes durable. The operating system passes it to the drive as a Flush.

Taught in Power Loss Lab

FTL failures show up to the host as a drive that becomes read-only, reports the wrong capacity, stalls, or returns old or empty data.

Taught in Part 6: The Flash Translation Layer

After a power loss the FTL rebuilds its map from the last checkpoint by replaying a journal of later changes, or by scanning the flash.

Taught in Part 6: The Flash Translation Layer

The g-line and i-line are the blue and ultraviolet light of a mercury vapor lamp, the lithography light sources used before excimer lasers.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

Garbage collection copies the valid pages out of mostly stale blocks and erases those blocks, so there is always free space for new writes.

Taught in Part 1: Standards & Interfaces; also in Part 3: From Cell to Die, Part 4: 3D NAND Stacking

A gate-all-around (GAA) transistor has its gate wrapped completely around thin channel sheets. Nanosheet designs such as Intel’s RibbonFET are the successor to the FinFET in logic.

Taught in Working Memory, Part 3: What Could Follow DRAM

Gate-induced drain leakage erase raises the channel voltage at the end of a string until holes are generated that erase the cells above.

Taught in Part 2: The Physics of Flash; also in Part 3: From Cell to Die

GGUF is the single-file model format that llama.cpp and the runners built on it load, made for fast loading and holding the weights at a chosen quantization.

Taught in Understanding SI, Part 2: Running Language Models Locally on Windows

GPUDirect Storage is NVIDIA’s path that moves data straight between an NVMe drive and GPU memory, skipping a copy through the CPU’s memory.

Taught in Memory and Storage for SI, Part 5: Context Memory; also in How Storage Works, Part 1: The Memory and Storage Hierarchy, Networking for SI, Part 3: DPUs and SmartNICs as Storage Engines

GDDR is DRAM built for graphics cards. It trades capacity and power for a very high data rate per pin on a wide bus soldered around the GPU.

Taught in Working Memory, Part 2: DRAM From the Inside; also in Working Memory, Part 4: High Bandwidth Memory

A guard band is the gap kept between a read reference voltage and the nearest distribution, so ordinary drift does not turn into read errors.

Taught in Part 2: The Physics of Flash

Guidance is the outlook a company gives with its results for the coming quarter, often a revenue range. Actual results can land above or below it.

Taught in Earnings Desk

A half-selected cell sits on the selected row or column but is not the cell being accessed, so it sees part of the applied voltage.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

A hard error is a wrong bit read at the best voltage. Soft information adds how close each cell sat to the boundary, so the decoder can weigh bits.

Taught in Part 8: Error Correction & Integrity

Hardware engines are fixed circuits for the heavy, repetitive jobs such as error correction, encryption and data movement. They run faster than firmware could.

Taught in Part 5: The Controller

HAMR heats a tiny spot of a hard drive platter with a laser as the head writes, so media that holds its bits more firmly at room temperature can still be written, and bits can sit closer together.

Taught in How Storage Works, Part 2: How a Hard Drive Works

A helium-sealed hard drive is filled with helium instead of air. The thinner gas lets the platters spin with less drag and flutter, so more platters fit in the same case.

Taught in How Storage Works, Part 2: How a Hard Drive Works

Hexadecimal writes numbers in base sixteen, with ten digits and the letters a to f, so each byte takes two hex digits.

Taught in AES Engine Lab

High Bandwidth Flash stacks NAND dies the way HBM stacks DRAM and places them on the processor’s package, trading some speed for far more capacity beside the GPU.

Taught in Memory and Storage for SI, Part 2: High Bandwidth Flash

High Bandwidth Memory stacks DRAM dies on a base die and links them with thousands of vertical wires, giving a very wide, short path to a processor on the same package.

Taught in Working Memory, Part 4: High Bandwidth Memory; also in Working Memory, Part 2: DRAM From the Inside, Working Memory, Part 3: What Could Follow DRAM

High NA EUV is the newer generation of EUV lithography, whose optics have a higher numerical aperture, so it prints finer features in a single exposure.

Taught in Fab Tracker

The high-resistance state is the resistive cell state that passes little current, and it stores the opposite value to the low-resistance state.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

Hold-up capacitors store enough energy to finish in-flight writes and save metadata after the host power fails.

Taught in Part 6: The Flash Translation Layer; also in Power Loss Lab

The host is the computer a drive is attached to. It sends the commands and waits for the drive to answer.

Taught in Power Loss Lab

Host Controlled Thermal Management lets the host set two temperatures at which an NVMe drive throttles lightly and then heavily. It is an optional NVMe feature.

Taught in Throttle Lab

Host memory buffer lets a DRAMless NVMe drive borrow a small region of host RAM to cache part of its map.

Taught in Part 5: The Controller; also in Part 6: The Flash Translation Layer, DRAM-Less SSDs Are Slow

Hot data is rewritten often and cold data rarely. Keeping them in separate blocks means blocks empty out together, which reduces garbage collection copying.

Taught in Part 7: Garbage Collection & Wear; also in Defrag Lab

Hybrid bonding joins two dies or wafers face to face with no solder: copper pads set flush in silicon oxide are placed together and annealed, so oxide bonds to oxide and copper to copper at once.

Taught in Working Memory, Part 3: What Could Follow DRAM

Hysteresis is a gap between the temperature where a throttle starts and the lower one where it stops, so it does not flicker on and off.

Taught in Throttle Lab

I/O pacing inserts waits between commands so the NAND does less work each second and makes less heat.

Taught in Throttle Lab

Immersion lithography fills the gap between the lens and the wafer with water, which raises the numerical aperture so the same ArF light prints finer features.

Taught in Fab Tracker

Incremental step pulse programming raises the program voltage a small step with every pulse and checks the cell between pulses, so charge lands precisely.

Taught in Part 2: The Physics of Flash; also in Part 3: From Cell to Die, Follow a Read

IGZO is an oxide semiconductor whose transistors leak far less than silicon ones, which makes it a candidate channel for DRAM cells that hold their charge longer.

Taught in Working Memory, Part 3: What Could Follow DRAM

Inherent overprovisioning comes from raw capacity counted in binary units against a decimal user capacity, and it gives about 7.37% extra space.

Taught in Part 9: Performance & Endurance

Interleaving overlaps work on different dies and channels so one die programs while another transfers data, keeping the bus busy.

Taught in Part 5: The Controller

An interposer is a slab of silicon or other material with very fine wiring that sits under a processor and its memory stacks and connects them side by side.

Taught in Working Memory, Part 4: High Bandwidth Memory

Inventory is finished chips held by makers or buyers. A large inventory lets buyers wait, which pushes prices down, and a small one does the reverse.

Taught in The Memory Cycle

Ion implantation fires charged ions into the silicon where the resist leaves it open, changing how it conducts. It is how transistors are formed in the wafer.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

IOPS counts commands finished per second. Queue depth is how many commands are outstanding at once, and a drive needs a deeper queue to reach its top IOPS.

Taught in Part 1: Standards & Interfaces; also in Part 9: Performance & Endurance, Beyond NAND, Part 2: Phase-Change Memory and Optane

JESD218 and JESD219 are the JEDEC standards that define how SSD endurance is tested and which workload is used for it.

Taught in An Unplugged SSD Loses Its Data in Weeks; also in Hot NAND Is Bad for Your Data

Jetson is NVIDIA’s family of small computer modules for robots and other machines that run SI on board, each with a GPU, a CPU and memory on one module.

Taught in Cogs and Cache

The process factor in the Rayleigh criterion gathers resist chemistry, mask technology and exposure conditions. Lowering it toward its physical limit prints smaller features with the same light and optics.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

A krypton fluoride excimer laser is a deep ultraviolet light source for lithography, with a longer wavelength than the argon fluoride laser that followed it.

Taught in Fab Tracker

A KV cache stores the key and value vectors a language model computes for each token, so later tokens reuse them instead of recomputing them. It grows with context length.

Taught in Memory and Storage for SI, Part 2: High Bandwidth Flash; also in Memory and Storage for SI, Part 5: Context Memory, Networking for SI, Part 5: CXL and SDXI Where They Touch Storage

L0p is a PCIe low-power link state that turns off some of a link’s lanes while at least one keeps carrying traffic, so power falls with use without a pause in data.

Taught in How Storage Works, Part 4: PCIe Gen6 and Gen7 for Storage

The logical-to-physical map needs about 4 bytes for every 4KiB of data, which works out to about 1GB of map for every 1TB of capacity.

Taught in Part 5: The Controller

A laser-produced plasma source makes EUV light from falling droplets of molten tin: one laser pulse flattens each droplet, and a stronger one vaporizes it into a plasma.

Taught in Photolithography, Part 2: Resolution, From Mercury Lamps to EUV

The last-level cache is the outermost cache level, shared by all the cores in a processor. A request that misses it goes out to main memory.

Taught in Working Memory, Part 1: SRAM and the Processor Cache

Latency is how long one command takes, from the moment it is sent to the moment it completes.

Taught in Throttle Lab

The layer count is the number of cell layers in a vertical stack. More layers means more bits per unit of die area.

Taught in Part 4: 3D NAND Stacking; also in The Memory Map: What Comes After Flash, Working Memory, Part 3: What Could Follow DRAM

Vendors count layers differently, including dummy layers, decks and select gates, so a bigger layer number does not by itself mean higher density.

Taught in Part 4: 3D NAND Stacking

Adding layers costs more deposition and etch steps per wafer, so the cost per bit falls only if the extra bits outweigh the extra process cost.

Taught in Part 4: 3D NAND Stacking

Line bias is the voltage held on a word or bit line. Unselected lines can float or sit at a fraction of the read voltage to limit sneak current.

Taught in Crosspoint Lab

Line encoding adds structure to a serial bit stream so the receiver can recover the clock. 8b/10b costs 20% of the bits, while 128b/130b costs under 2%.

Taught in Part 1: Standards & Interfaces

Line resistance is the resistance of the word and bit lines themselves, which drops voltage along the line and weakens cells far from the driver.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

LTFS lets a tape cartridge appear as a file system, so its files can be listed and read without the backup software that wrote them.

Taught in How Storage Works, Part 3: Tape and Cold Archive

LTO is an open tape format developed by HPE, IBM and Quantum, with a new generation of cartridges and drives every few years.

Taught in How Storage Works, Part 3: Tape and Cold Archive

Link training is the handshake at power-up where two PCIe devices agree on a speed and width. The result is readable in the link status register, LnkSta.

Taught in Part 1: Standards & Interfaces

Link-state thermal throttling is Phison’s name for lowering a controller’s own PCIe link rate to cut heat.

Taught in Throttle Lab

Lithography prints a chip’s patterns by shining light through a mask onto a light-sensitive coating on the wafer, so later steps can etch or fill only where the light landed.

Taught in Fab Tracker

A logic chip computes or controls, as processors, GPUs and SSD controllers do, as opposed to a memory chip, which stores data.

Taught in Fab Tracker

A logical block address numbers the fixed-size blocks the host sees, starting at zero. The drive decides where each one is physically stored.

Taught in Part 3: From Cell to Die; also in Part 6: The Flash Translation Layer, Part 8: Error Correction & Integrity

A LUN, or logical unit, is the smallest part of a NAND package that can run its own command independently. On most parts it is one die.

Taught in Part 5: The Controller

The logical-to-physical table records where each logical block currently lives in flash. Every write changes an entry, and every read looks one up.

Taught in Part 5: The Controller; also in Part 6: The Flash Translation Layer, Defrag Lab

LDPC is a code whose decoder passes confidence messages back and forth until the errors resolve. It corrects more errors than BCH, especially with soft input.

Taught in Part 2: The Physics of Flash; also in Part 3: From Cell to Die, Part 5: The Controller

LPDDR is the low-power branch of DDR memory for phones and laptops. It is soldered close to the processor and built to idle at very little power.

Taught in Working Memory, Part 2: DRAM From the Inside; also in Working Memory, Part 4: High Bandwidth Memory, Memory and Storage for SI, Part 2: High Bandwidth Flash

The low-resistance state is the resistive cell state that passes current easily, and it usually stores a one.

Taught in Beyond NAND, Part 2: Phase-Change Memory and Optane; also in Beyond NAND, Part 3: MRAM From Tunnel Junction to Product, Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar

In a multi-bit cell each bit belongs to a different page type: lower, middle, upper and, for QLC, extra. Each type needs a different number of reads.

Taught in Part 3: From Cell to Die

M.2 is a small card format for SSDs. The name 2280 means 22mm wide and 80mm long, and other common lengths are 2230, 2242 and 22110.

Taught in Part 1: Standards & Interfaces

The M.2 socket supplies 3.3V and sets a current limit that caps how much power the drive may draw from the board.

Taught in Part 1: Standards & Interfaces

Machine learning in firmware uses small trained models to predict things such as the best read voltage or the next access, in place of fixed tables.

Taught in Part 10: The Future of Flash

Magnetic tape stores archive data on cartridges kept in tape libraries, with a very low total cost of ownership and very low power use.

Taught in How Storage Works, Part 1: The Memory and Storage Hierarchy; also in How Storage Works, Part 3: Tape and Cold Archive

A magnetic tunnel junction is two thin magnets with an insulating barrier between them. One is fixed and the other can flip, and their alignment sets the junction’s resistance.

Taught in Beyond NAND, Part 3: MRAM From Tunnel Junction to Product

The map can live in on-drive DRAM, in a slice of host memory, or mostly in flash with a small cache on a DRAMless drive. Placement sets random-read speed.

Taught in Part 6: The Flash Translation Layer

A mask blank is the coated glass plate a photomask starts as: the mask maker writes the circuit pattern onto it, then develops and etches it to fix the pattern.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

MDTS is the most data one NVMe command may move between host memory and the drive. The drive reports it in its Identify Controller data, where zero means no limit.

Taught in Defrag Lab

MTBF is a statistical rating drawn from failure rates across a large number of drives. It is no guarantee or estimate of how long any one drive will last.

Taught in Storage and Memory in Practice, Part 4: How to Read an SSD Spec Sheet

The media encryption key encrypts everything a self-encrypting drive stores. It never leaves the drive and is kept wrapped under a key derived from the user’s password.

Taught in AES Engine Lab; also in Secure Erase Lab

Memory bandwidth is how fast a processor can read and write its memory, in bytes per second. For SI inference it often sets the speed more than raw compute does.

Taught in How Storage Works, Part 1: The Memory and Storage Hierarchy; also in Best GPUs, Cogs and Cache

A memory controller is the circuit, usually inside the processor, that turns reads and writes into DRAM commands and schedules them around refresh and timing rules.

Taught in Working Memory, Part 2: DRAM From the Inside; also in Working Memory, Part 3: What Could Follow DRAM, Working Memory, Part 4: High Bandwidth Memory

The memory cycle is the repeating swing in memory prices and profits: a shortage lifts prices and spending, new fabs add supply, and prices fall until spending stops.

Taught in The Memory Cycle

The memory hierarchy combines memories that differ in cost, speed and power, from SRAM cache on the processor to DRAM main memory and storage, to act like one ideal memory.

Taught in Working Memory, Part 1: SRAM and the Processor Cache

MTD is the Linux subsystem that gives flash chips one uniform interface. An MTD device, such as /dev/mtd0, represents raw flash.

Taught in Flash in Small Devices: Routers, Cameras and Watches

A metal-oxide resist is a photoresist built on metal oxides, such as tin oxide, instead of the carbon and oxygen of conventional chemically amplified resists. It absorbs EUV light more strongly than those resists.

Taught in Photolithography, Part 2: Resolution, From Mercury Lamps to EUV

Metrology measures what the process printed, such as how well two layers line up, and feeds the data back so the lithography tool can correct the next wafers.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

A microbump is a tiny solder joint that connects one stacked die to the next, landing on the through-silicon vias of the die below.

Taught in Working Memory, Part 4: High Bandwidth Memory

A microSD Express card adds a second row of pins that carries PCI Express and NVMe, while its first row keeps the UHS-I interface, so an existing host still runs it at UHS-I speed.

Taught in SD and microSD Cards: Classes, Bus Modes and SD Express

MAMR adds a radio-frequency field from a spin torque oscillator in the write head to the write field, which helps the head write media that holds its bits more firmly.

Taught in How Storage Works, Part 2: How a Hard Drive Works

M-PHY is the MIPI physical layer that carries UFS traffic. It sits under UniPro, and together the two form the high-speed serial link between host and flash device.

Taught in UFS Explained: The Flash Storage Inside Your Phone

A mixture-of-experts model splits its layers into many expert blocks and sends each token through only a few of them, so memory holds every expert while each token reads a fraction.

Taught in Understanding SI, Part 2: Running Language Models Locally on Windows

MRAM stores each bit as the magnetic state of a magnetic tunnel junction and reads it by sensing the junction’s resistance. The magnets hold their state without power.

Taught in Beyond NAND, Part 3: MRAM From Tunnel Junction to Product

MCQ is a UFS host controller mode with separate submission and completion queues, as NVMe uses, in place of one command list. Several CPU cores can use them at once.

Taught in UFS Explained: The Flash Storage Inside Your Phone

A multi-level resistive cell holds more than one bit by being set to one of several distinct resistances instead of just two.

Taught in Crosspoint Lab

Multi-pass programming writes a page in two or more passes, first a coarse placement of charge, then a fine pass that tightens each level.

Taught in Part 5: The Controller

Multi-patterning splits one complex layer pattern into simpler patterns exposed separately. Litho-etch-litho-etch (LELE) prints and etches in turn, while self-aligned double and quadruple patterning (SADP, SAQP) build sidewall spacers by deposition and etch from a pre-pattern of lines.

Taught in Photolithography, Part 2: Resolution, From Mercury Lamps to EUV; also in Photolithography, Part 3: High-NA EUV and What It Means for Memory

Multi-stream lets the host tag writes with a stream number so data with similar lifetimes lands in the same blocks.

Taught in Part 6: The Flash Translation Layer

An MRDIMM is a server memory module whose buffer chips run two ranks at once and merge their data onto the channel, so the module moves more data than a standard registered DIMM. JEDEC standardizes its buffer chips.

Taught in Working Memory, Part 4: High Bandwidth Memory

A multiply-accumulate multiplies an input by a weight and adds the product to a running total. A crossbar does one in every cell and sums them along each column.

Taught in Crosspoint Lab

A namespace is a slice of an NVMe drive that the host sees as its own disk.

Taught in Secure Erase Lab

A NAND die is one piece of silicon holding flash memory. A drive spreads its work across many dies, and each can run an operation on its own.

Taught in Memory and Storage for SI, Part 2: High Bandwidth Flash; also in Follow a Read, Parallelism Lab

NAND flash is the memory that keeps data with the power off. Writing it is much slower than writing DRAM, and it must be erased before it is rewritten.

Taught in The Memory Map: What Comes After Flash; also in Beyond NAND, Part 1: NOR and Memory on the Processor Die, Beyond NAND, Part 2: Phase-Change Memory and Optane

NAND bus speed is the transfer rate between controller and die, in megatransfers per second. It sets a ceiling on per-channel throughput.

Taught in Part 4: 3D NAND Stacking; also in Parallelism Lab

A NAND string is a column of cells connected in series between a bitline and the source line, with a select transistor at each end.

Taught in Part 3: From Cell to Die; also in The Memory Map: What Comes After Flash, Beyond NAND, Part 4: Ferroelectric Memory From Polarization to Product

tR is the time to read a page into the buffer, tPROG the time to program a page and tBERS the time to erase a block. Erase is slowest.

Taught in Part 3: From Cell to Die; also in Follow a Read, Parallelism Lab

Network-attached storage is a storage system that gives other computers access to its files over a network.

Taught in Running a NAS, Part 1: NAS Operating Systems Compared; also in Running a NAS, Part 3: Drive Pooling on Windows, Running a NAS, Part 5: Tuning the NAS Network

NOR flash wires cells in parallel for fast random reads of single bytes. NAND wires them in series for much higher density at the cost of page-wise access.

Taught in Part 3: From Cell to Die

Numerical aperture measures how wide a cone of light a lens gathers. A higher numerical aperture lets a lithography tool print smaller features with the same light.

Taught in Fab Tracker

NVMe over Fabrics carries NVMe commands across a network, such as RDMA, Fibre Channel or TCP, so remote drives look like local ones.

Taught in Part 7: Garbage Collection & Wear

NVMe power states are numbered levels that trade performance for power. Each lists a maximum power and the time needed to enter and leave it.

Taught in Part 5: The Controller; also in Working Memory, Part 2: DRAM From the Inside, Throttle Lab

NVMe Protection Information attaches a checksum and tag to each block so corruption between host and media can be detected end to end.

Taught in Part 8: Error Correction & Integrity

NVMe uses pairs of queues in host memory: the host places commands in a submission queue and the drive reports results in a completion queue.

Taught in Part 1: Standards & Interfaces; also in How Storage Works, Part 1: The Memory and Storage Hierarchy, Follow a Read

The on/off ratio is how many times more current a low-resistance cell passes than a high-resistance one at the same voltage. A bigger ratio makes reads easier.

Taught in Beyond NAND, Part 4: Ferroelectric Memory From Polarization to Product; also in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar, Memory and Storage for SI, Part 1: Memory as a Synapse

ONFI and Toggle are the two families of NAND interface standards. Both move data with a double-data-rate strobe and differ in signaling details.

Taught in Part 5: The Controller

Operating margin is operating income divided by revenue: the share of each sales dollar left after the costs of making and running the business, before interest and tax.

Taught in The Memory Cycle; also in Earnings Desk

An operational amplifier is a high-gain circuit with two inputs. With feedback it drives the difference between them to nearly zero.

Taught in Crosspoint Lab

Optical proximity correction adjusts the mask pattern to counter distortions that nearby features cause in the printed image, such as unequal line widths, shortened line ends and rounded corners.

Taught in Photolithography, Part 2: Resolution, From Mercury Lamps to EUV

An orbital data center is a plan to put servers and accelerators in satellites, powered by sunlight and cooled by radiating their heat into space.

Taught in Signals

The spare, or out-of-band, area is extra bytes on every page that hold error-correction parity and controller metadata.

Taught in Part 3: From Cell to Die

An out-of-place write puts new data in a fresh page and marks the old copy invalid, because flash cannot overwrite a page directly.

Taught in Secure Erase Lab

Overlay is how well one printed layer is aligned with the layer before it, and an important measure of lithography performance.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light; also in Photolithography, Part 3: High-NA EUV and What It Means for Memory

Overprovisioning is flash capacity held back from the user. The controller uses it as working space for garbage collection, which lowers write amplification.

Taught in Part 2: The Physics of Flash; also in Part 7: Garbage Collection & Wear, Part 8: Error Correction & Integrity

An ovonic threshold switch is a chalcogenide layer that conducts only above a threshold voltage, used as the selector in phase-change crosspoint memory.

Taught in Beyond NAND, Part 2: Phase-Change Memory and Optane; also in Crosspoint Lab

Several dies can share one package, stacked and connected by wire bonds or through-silicon vias, which adds capacity without more board area.

Taught in Part 3: From Cell to Die

A package-on-package stack puts a DRAM package on top of the processor package. In the conventional layout the flash is a separate package beside the stack.

Taught in Flash in Phones and Tablets: One Board, Two Memories

Flash programs one page at a time but erases a whole block at a time, which is why changing a small amount of data causes much more internal work.

Taught in Part 3: From Cell to Die

The page buffer is a set of latches on the die that hold one page of data on its way to or from the cells.

Taught in Part 3: From Cell to Die; also in Follow a Read

A page is the smallest unit a NAND die programs or reads, commonly 16KiB of data plus a spare area for error-correction codes and metadata.

Taught in Part 3: From Cell to Die; also in Memory and Storage for SI, Part 2: High Bandwidth Flash, Follow a Read

NRZ sends one bit per symbol on two voltage levels. PAM4 sends two bits on four levels, which doubles the data rate but shrinks the noise margin.

Taught in Part 1: Standards & Interfaces

Flash gets its speed by working in parallel at several levels: channels carry data, each channel serves several dies, and each die has several planes.

Taught in Part 3: From Cell to Die; also in Throttle Lab

Parity is redundancy calculated from the data on several drives, so the contents of a lost drive can be rebuilt from the ones that remain.

Taught in Running a NAS, Part 2: Pools and Filesystems on a NAS

Pass voltage, Vpass, is applied to every unselected wordline during a read so those cells conduct whatever they hold and the selected cell decides the current.

Taught in Part 3: From Cell to Die

PCI Express is the serial link between an SSD and the host, built from one or more lanes. Each generation roughly doubles the rate per lane.

Taught in Beyond NAND, Part 2: Phase-Change Memory and Optane; also in Follow a Read, Parallelism Lab

PCIe 6.0 uses PAM4 signaling at 64GT/s per lane. The signal loses more strength on the board, so the channel must be short or use retimers.

Taught in Part 10: The Future of Flash

The PCIe bandwidth controller is a Linux kernel feature that lets the operating system lower a link’s speed as a cooling action.

Taught in Throttle Lab

Each PCIe generation roughly doubles the per-lane transfer rate, so the same x4 link carries more data in every new generation.

Taught in Part 1: Standards & Interfaces; also in Throttle Lab

A PCIe lane is one pair of transmit wires and one pair of receive wires. A link bundles one, two, four, eight or sixteen lanes.

Taught in Part 1: Standards & Interfaces

PCMark is UL’s benchmark of whole system performance, built from real-world apps and activities. Its storage benchmarks take a trace-based approach.

Taught in A Gen5 SSD Loads Games Faster

A pellicle is a thin membrane held just below the mask inside a lithography tool. It catches tiny particles that would otherwise cling to the mask and print on the wafer as defects.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

PLC stores five bits per cell using thirty-two voltage levels, which packs more data into the same silicon but leaves very little margin between levels.

Taught in Part 2: The Physics of Flash; also in Part 10: The Future of Flash

Percentage Used is a vendor estimate of drive life consumed, based on writes and wear. It can pass 100%, and the drive may keep working.

Taught in A Secure Erase Does Not Make an Old SSD Like New; also in Do SSDs Wear Out in a Couple of Years?, Does an SSD Fail With No Warning?

Phase-change memory stores data in a material that switches between a crystalline, low-resistance state and an amorphous, high-resistance state when heated.

Taught in The Memory Map: What Comes After Flash; also in Beyond NAND, Part 2: Phase-Change Memory and Optane, Beyond NAND, Part 4: Ferroelectric Memory From Polarization to Product

A photomask, also called a reticle, is the template that carries the circuit pattern for one layer, and light is projected through it to transfer that pattern onto the wafer. An EUV mask works by selectively reflecting or blocking light.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light; also in Photolithography, Part 3: High-NA EUV and What It Means for Memory

Photoresist is the light-sensitive coating on the wafer. Exposure changes how easily it dissolves in the developer, so the develop step washes away the exposed or the unexposed part and leaves a mask for later etching.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light; also in Photolithography, Part 3: High-NA EUV and What It Means for Memory

The PHY is the part of a controller that drives the PCIe link, sending and receiving the signals. It draws more power at higher link speeds.

Taught in Throttle Lab

Pitch is the width of one line plus one space in a repeating pattern of lines and spaces, and half-pitch is half that distance.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

Planar NAND stopped shrinking when cells grew so close that neighbors interfered and too few electrons stayed on each gate to tell levels apart.

Taught in Part 4: 3D NAND Stacking

A plane is an independent set of blocks on a die with its own page buffer. A multi-plane operation runs the same command on several planes at once.

Taught in Part 3: From Cell to Die; also in Follow a Read, Parallelism Lab

A platter is a spinning disk inside a hard drive that holds the magnetic recording media. One or more actuators give the drive physical access to the data on it.

Taught in How Storage Works, Part 1: The Memory and Storage Hierarchy; also in How Storage Works, Part 2: How a Hard Drive Works

A power budget caps how much power a drive may draw at once. Firmware meets it by running fewer NAND operations at the same time.

Taught in Working Memory, Part 4: High Bandwidth Memory; also in Throttle Lab

A power cycle removes power from a drive and restores it, which clears a latched shutdown.

Taught in Throttle Lab

Power loss protection uses stored energy to let a drive finish writing buffered data and metadata when power fails, so acknowledged writes survive.

Taught in Part 5: The Controller; also in Part 6: The Flash Translation Layer, Part 9: Performance & Endurance

Without power loss protection, a sudden power cut can lose data held in volatile buffers and can leave the map out of step with the flash.

Taught in Part 6: The Flash Translation Layer

A power management IC converts the host supply into the several voltages the controller, DRAM and NAND need, and sequences them at power-up.

Taught in Part 5: The Controller

Precharge closes the open row of a DRAM bank and resets its bit lines, so the bank is ready to open a different row.

Taught in Working Memory, Part 2: DRAM From the Inside; also in Working Memory, Part 3: What Could Follow DRAM

Prefetch is how many bits per data pin a DRAM die fetches from its slow core in one go, which lets the interface run many times faster than the cells.

Taught in Working Memory, Part 2: DRAM From the Inside

A preprint is a research paper posted in public, often on arXiv, before a journal or conference has reviewed it, or without any review at all.

Taught in Cogs and Cache

A process node names a generation of a maker’s manufacturing process. Smaller names once meant smaller transistors; for logic they are now labels rather than measurements.

Taught in Fab Tracker

In a tall stack the hole is narrower at the bottom than at the top, so cells on different layers differ in size and behave differently.

Taught in Part 4: 3D NAND Stacking

Program disturb is unwanted charge added to cells that should stay unchanged. Self-boosting raises the channel voltage of inhibited strings to reduce it.

Taught in Part 3: From Cell to Die

Pages in a block must be programmed in a set order, usually from the first wordline to the last, to limit disturb between neighboring cells.

Taught in Part 3: From Cell to Die

Program and erase suspend let a die pause a long operation to serve a read, then resume, which cuts the wait that reads would otherwise see.

Taught in Part 9: Performance & Endurance

Program-verify alternates a program pulse with a read check. Cells that reached their target stop receiving pulses, and the rest continue.

Taught in Part 3: From Cell to Die

A program/erase cycle is one write of a block followed by its erase. Each cycle wears the oxide, and the cell type sets how many cycles it tolerates.

Taught in Part 2: The Physics of Flash; also in Part 3: From Cell to Die, Part 4: 3D NAND Stacking

Projected phase-change memory adds a conducting segment alongside the phase-change material, so the read current can avoid the part that drifts.

Taught in Crosspoint Lab

A pseudo channel is one of the two halves an HBM channel is split into. The halves share the channel’s command bus but each decodes and runs its own commands on its own half of the data pins.

Taught in Working Memory, Part 4: High Bandwidth Memory

Quantization stores each weight of a language model in fewer bits, which shrinks the file and the memory it needs at some cost in accuracy.

Taught in Understanding SI, Part 2: Running Language Models Locally on Windows

RAID, a redundant array of independent disks, combines several drives into one array. Its parity levels let the array keep working when one drive fails.

Taught in Running a NAS, Part 1: NAS Operating Systems Compared; also in Running a NAS, Part 2: Pools and Filesystems on a NAS, Running a NAS, Part 8: Keeping a NAS Healthy

RAIN adds parity across dies, much like RAID across drives, so the data from a failed page or even a whole die can be rebuilt.

Taught in Part 8: Error Correction & Integrity

Random I/O reads or writes small requests at scattered addresses across a drive, so each request lands somewhere new.

Taught in How Storage Works, Part 1: The Memory and Storage Hierarchy

A rank is the set of DRAM chips on a module that answer one command together to fill the full width of the memory channel.

Taught in Working Memory, Part 2: DRAM From the Inside

Raw bit error rate is the fraction of bits read from the NAND that are wrong before error correction is applied.

Taught in Part 2: The Physics of Flash; also in Part 3: From Cell to Die, Part 4: 3D NAND Stacking

The Rayleigh criterion gives the smallest feature a lithography tool can print: a process factor times the wavelength of its light, divided by the numerical aperture of its optics.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light; also in Photolithography, Part 2: Resolution, From Mercury Lamps to EUV

Read disturb is the slow charge gain in unselected cells caused by the pass voltage applied to them every time a neighboring page is read.

Taught in Part 3: From Cell to Die

The controller counts reads per block and rewrites a block into fresh flash before read disturb errors grow beyond what error correction can handle.

Taught in Part 7: Garbage Collection & Wear

A read level is one reference voltage a die compares each cell against. A page that needs more levels needs more sensing passes.

Taught in Follow a Read

Read margin is how far apart a low-resistance read and a high-resistance read stay once the worst-case neighbors are counted. When it reaches zero the two cannot be told apart.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

Read retry rereads a failed page with the read reference voltages shifted, trying a table of offsets until the data decodes.

Taught in Part 2: The Physics of Flash; also in Part 4: 3D NAND Stacking, Hot NAND Is Bad for Your Data

The read window budget is the voltage room left between distributions for placing read references. It shrinks with every added bit per cell and every cycle of wear.

Taught in Part 3: From Cell to Die

Read-reference calibration hardware measures how the threshold distributions have moved and adjusts the read voltages to follow them.

Taught in Part 5: The Controller

Refresh reads every DRAM row and writes it back before its capacitors leak too far to tell a one from a zero. A bank that is refreshing cannot serve reads or writes.

Taught in Working Memory, Part 2: DRAM From the Inside

Refresh and scrubbing read old data in the background, correct errors and rewrite it, so charge loss does not accumulate unseen.

Taught in Part 7: Garbage Collection & Wear

A registered DIMM adds a chip that buffers the command and address signals, so a server can carry more modules per channel at the cost of a little latency.

Taught in Working Memory, Part 4: High Bandwidth Memory

A remap changes which physical location a logical address points to, so data can move without being copied.

Taught in Defrag Lab

In the replacement-gate process the stack is first built with sacrificial layers, then those layers are etched away and replaced with metal wordlines.

Taught in Part 4: 3D NAND Stacking

Request splitting happens when one read crosses a fragment boundary or the transfer size limit and reaches the drive as several commands.

Taught in Defrag Lab

Reset switches a resistive cell back to its high-resistance state, usually with a pulse of the opposite polarity or a different shape.

Taught in Crosspoint Lab

Resistance drift is the slow rise in resistance of a phase-change cell after it is written, which makes in-between levels hard to hold.

Taught in Crosspoint Lab

Retention loss is charge slowly leaking from the storage layer. Heat speeds it up, and a worn oxide leaks faster.

Taught in Automotive and Industrial Flash: Built for Heat and Wear; also in Hot NAND Is Bad for Your Data, Throttle Lab

Retention behavior describes how many errors accumulate while data sits unpowered. The endurance standard specifies a retention period at a given temperature.

Taught in Part 8: Error Correction & Integrity

A retimer is a chip partway along a high-speed link that recovers the signal and sends it on afresh, so the link can reach farther across a board or cable than it could alone.

Taught in How Storage Works, Part 4: PCIe Gen6 and Gen7 for Storage

ReTrim sends TRIM again for all the free space on a volume. Windows runs it from Optimize Drives on a schedule.

Taught in Windows Defrags Your SSD and Wears It Out; also in You Have to Run TRIM by Hand, Defrag Lab

Rotational latency is the wait for the right part of a spinning platter to come under the head. On average it is half a turn.

Taught in Defrag Lab

A round key is a block-sized key the key schedule makes from the main key. AES mixes a fresh one into the data at every round.

Taught in AES Engine Lab

Random telegraph noise is a small threshold-voltage jump that appears when one electron is repeatedly captured and released by a single trap near the channel.

Taught in Part 2: The Physics of Flash; also in Crosspoint Lab

The S-box is the fixed lookup table AES uses in its SubBytes step, the one part of each round that is not simple arithmetic.

Taught in AES Engine Lab

NVMe sanitize offers block erase, overwrite and cryptographic erase, and a drive may support any of them. Each runs in the background and survives a power cycle.

Taught in Part 6: The Flash Translation Layer; also in Secure Erase Lab

The Sanitize Status log is where an NVMe drive reports whether a sanitize is running, finished or failed.

Taught in Secure Erase Lab

A scanner is a lithography tool that moves the mask through a narrow slit of light while the wafer moves the opposite way in step, so only a small part of the pattern is exposed at a time. ArF immersion and EUV tools are scanners.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light; also in Photolithography, Part 3: High-NA EUV and What It Means for Memory, What a Gigawatt Takes

A scrub reads stored data and checks it against its checksum or parity, so silent corruption is found and, where a good copy exists, repaired.

Taught in Running a NAS, Part 2: Pools and Filesystems on a NAS

SDXC is the SD card capacity family above SDHC and below SDUC, and its cards come formatted with the exFAT file system.

Taught in SD and microSD Cards: Classes, Bus Modes and SD Express

A sector is the smallest unit of a drive the host reads or writes, and each one has its own logical block address.

Taught in AES Engine Lab

Seek time is how long a hard drive’s head takes to move to the right track. The head cannot read while it moves.

Taught in Defrag Lab

The drain and source select gates connect a string to its bitline and to the source line, so only the chosen strings take part in an operation.

Taught in Part 3: From Cell to Die

A selector is a device in series with a memory cell that blocks current until the voltage across it passes a threshold.

Taught in Crosspoint Lab

Nonlinearity is how sharply current rises with voltage. A strongly nonlinear selector passes almost nothing at half the read voltage and a lot at the full read voltage.

Taught in Crosspoint Lab

A self-encrypting drive encrypts all data with AES in hardware as it is written, using a media key that the drive itself holds.

Taught in Part 5: The Controller; also in Networking for SI, Part 3: DPUs and SmartNICs as Storage Engines, AES Engine Lab

A self-rectifying cell passes current far more easily in one direction than the other, so it blocks idle cells on its own and needs no separate selector.

Taught in Crosspoint Lab

A sense amplifier compares the current or voltage of a selected cell against a reference to decide which stored level the cell holds.

Taught in Part 3: From Cell to Die; also in Working Memory, Part 1: SRAM and the Processor Cache, Working Memory, Part 2: DRAM From the Inside

Sequential I/O reads or writes one address after the next, usually in large requests.

Taught in The Memory Map: What Comes After Flash

SATA is the serial interface for storage that tops out at 6Gb/s, or 600MB/s on the wire before overhead, with one command queue of 32 entries.

Taught in Part 1: Standards & Interfaces

SAS is the serial interface used by enterprise drives. It supports dual ports, long cables and expanders, and speaks the SCSI command set.

Taught in Part 1: Standards & Interfaces

SPI is a simple serial bus of a clock, a chip select and data lines. Serial NOR and NAND flash chips use it, often in dual or quad data modes.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Flash in Small Devices: Routers, Cameras and Watches

Serial presence detect is a small nonvolatile memory on a module that describes it, so the BIOS can read it and set up the memory channels correctly.

Taught in Working Memory, Part 6: CAMM2, LPCAMM2 and SOCAMM2

Serpentine recording writes a group of tracks along the whole length of a tape, then turns and writes the next group back the other way, passing over the tape many times to fill it.

Taught in How Storage Works, Part 3: Tape and Cold Archive

Set switches a resistive cell to its low-resistance state by driving it past its set voltage.

Taught in Crosspoint Lab

Shingled magnetic recording overlaps each track on the one before to fit more data. Rewriting part of a band means rewriting the rest of it, which slows sustained writes.

Taught in How Storage Works, Part 2: How a Hard Drive Works; also in Running a NAS, Part 1: NAS Operating Systems Compared, Running a NAS, Part 2: Pools and Filesystems on a NAS

Shrink is making transistors smaller so more of them fit on a wafer. It has been behind the growth in computing power for decades.

Taught in Photolithography, Part 2: Resolution, From Mercury Lamps to EUV

Sideband pins carry control signals beside the data lanes, such as PERST# for reset, CLKREQ# for clock requests and PLN# for power loss notice.

Taught in Part 1: Standards & Interfaces

SLC mode, or pseudo-SLC, runs a multi-level block as one bit per cell. It writes faster and survives more cycles, but holds a fraction of the data.

Taught in Part 3: From Cell to Die; also in Part 6: The Flash Translation Layer

The SLC cache may shrink as the drive fills. Writes run fast until it is full, then fall to the speed of direct TLC or QLC writes.

Taught in Part 9: Performance & Endurance

An SLC cache writes incoming data first in a fast one-bit-per-cell mode, then folds it into denser TLC or QLC cells when the drive has time.

Taught in Part 1: Standards & Interfaces; also in Part 5: The Controller, How Storage Works, Part 1: The Memory and Storage Hierarchy

Folding rewrites data held in SLC blocks into TLC or QLC blocks, which frees the SLC space but costs extra writes inside the drive.

Taught in Part 6: The Flash Translation Layer

SCSI is a family of standards for storage interfaces and commands. SAS still uses the SCSI command set, over a serial link in place of the older parallel SCSI bus.

Taught in UFS Explained: The Flash Storage Inside Your Phone

A SO-DIMM is the shorter memory module used in laptops and small desktops.

Taught in Best RAM

The SMART and NVMe health log reports counters such as temperature, percentage used, available spare, media errors and data units written.

Taught in Part 6: The Flash Translation Layer; also in Part 7: Garbage Collection & Wear, Part 8: Error Correction & Integrity

A snapshot is a point-in-time image of a file system or dataset, kept on the same drives, so changed or deleted files can be brought back from it.

Taught in Running a NAS, Part 2: Pools and Filesystems on a NAS

A sneak path is current that goes around the selected cell in a crossbar, through a chain of unselected cells, and adds error to the read.

Taught in Crosspoint Lab

The SNIA Performance Test Specification sets a repeatable method for measuring SSDs: precondition the drive, reach steady state, then record.

Taught in Part 1: Standards & Interfaces

Soft-decision decoding reads each page several times at slightly different voltages to estimate how reliable each bit is, which lets LDPC correct more.

Taught in Part 8: Error Correction & Integrity

SOT-MRAM writes a bit with current through a layer beside the magnetic tunnel junction instead of through its barrier. The separate read and write paths spare the barrier from wear.

Taught in Beyond NAND, Part 3: MRAM From Tunnel Junction to Product

SR-IOV lets one physical PCIe device present itself as several virtual functions, so each virtual machine can talk to its own slice of the drive.

Taught in Part 5: The Controller; also in Automotive and Industrial Flash: Built for Heat and Wear

SRAM is fast memory of latching cells with several transistors each. It needs no refresh but takes far more area per bit than DRAM, so it serves as on-chip memory.

Taught in The Memory Map: What Comes After Flash; also in Working Memory, Part 1: SRAM and the Processor Cache, Working Memory, Part 2: DRAM From the Inside

An SRAM cell is two cross-coupled inverters and two access transistors, six transistors in all. It takes more silicon area per bit than any other memory in the hierarchy.

Taught in Working Memory, Part 1: SRAM and the Processor Cache

An SSD board carries the controller, the NAND packages, optional DRAM, power regulation and the connector, laid out to keep the signal paths short.

Taught in Part 5: The Controller

An SSD heatsink is a heat sink fitted to the drive, sometimes pre-installed, to help it maintain peak performance through long, intense workloads.

Taught in Every NVMe SSD Needs a Heatsink

Stack height is how many DRAM dies an HBM stack holds. More dies give more capacity in the same footprint but make the stack harder to build and cool.

Taught in Working Memory, Part 4: High Bandwidth Memory

The staircase is the stepped edge of the stack where each wordline layer ends in a ledge, so a contact can reach it from above.

Taught in Part 4: 3D NAND Stacking

Stale data is an older copy of a block returned after power loss because the map update never reached flash.

Taught in Part 6: The Flash Translation Layer

A stale page holds data the drive no longer maps to any address. The bytes stay on the chip until its block is erased.

Taught in Secure Erase Lab

Standards bodies such as NVM Express, PCI-SIG, SATA-IO, JEDEC and ONFI each write the rules for one layer, from the host link down to the NAND bus.

Taught in Part 1: Standards & Interfaces; also in Working Memory, Part 3: What Could Follow DRAM

Steady state is the condition where performance has stopped changing because the drive is full of data and garbage collection runs continuously.

Taught in Part 7: Garbage Collection & Wear; also in Part 9: Performance & Endurance, SSD Benchmarking 201, Part 2: Steady State and Tail Latency

A stepper is an older lithography tool that exposes one field of the wafer through the mask in a single shot, then steps the exposure stage and repeats until the wafer is covered. Scanners, which move the mask and wafer together during exposure, came later.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

Stitching prints a chip too large for one exposure field as separate exposures that meet at a boundary, which needs tight overlay and size control where they join.

Taught in Photolithography, Part 3: High-NA EUV and What It Means for Memory

A stochastic defect is a random, isolated printing failure, such as a missing or merged feature. At EUV wavelengths only a few photons create the pattern, and the molecular nature of the resist and chance in how light and resist interact add to the randomness.

Taught in Photolithography, Part 2: Resolution, From Mercury Lamps to EUV; also in Photolithography, Part 3: High-NA EUV and What It Means for Memory

Storage class memory keeps data with the power off like flash but answers far faster, aimed at the performance gap between DRAM and ordinary flash.

Taught in The Memory Map: What Comes After Flash

Striping spreads consecutive data across dies or drives, so one large transfer can use many of them at once.

Taught in Defrag Lab

STT-MRAM writes a bit by passing current through the magnetic tunnel junction itself. Electrons spin-polarized by the fixed magnet flip the free one, an effect called spin-transfer torque.

Taught in Beyond NAND, Part 3: MRAM From Tunnel Junction to Product

A stuck cell no longer switches and holds one conductance whatever is written to it.

Taught in Crosspoint Lab

A DDR5 module splits its data bus into two independent subchannels. They let the memory controller run more accesses at once and schedule them better.

Taught in Working Memory, Part 2: DRAM From the Inside

A superblock groups one block from each die or plane so the controller can write and erase them together as a single larger unit.

Taught in Part 6: The Flash Translation Layer

A latency percentile gives the time within which that share of commands finished. The 99th percentile is the time that 99% of commands beat.

Taught in Part 7: Garbage Collection & Wear; also in Networking for SI, Part 3: DPUs and SmartNICs as Storage Engines, SSD Benchmarking 201, Part 1: Building a Repeatable Benchmark Job

A Tanner graph draws an LDPC code as two rows of nodes, bits and parity checks, joined by edges. Iterative decoding passes messages along those edges.

Taught in Part 8: Error Correction & Integrity

Terabytes written is the total host data a manufacturer rates a drive to absorb over its life under the warranty conditions.

Taught in Part 2: The Physics of Flash; also in Part 5: The Controller, Part 6: The Flash Translation Layer

Temperature differs across a die and between dies in a package. Simulations model a hotter end of the string, but any gradient inside the stack is unproven.

Taught in Part 4: 3D NAND Stacking

Thermal overshoot is temperature rising past a trigger after a throttle acts, because heat already stored keeps flowing.

Taught in Throttle Lab

Thermal resistance says how many degrees hotter a part gets for each watt it must shed, and a heatsink lowers it.

Taught in Every NVMe SSD Needs a Heatsink; also in Throttle Lab

Thermal throttling slows a drive when its temperature passes a limit, cutting power and heat so the hardware stays within its safe range.

Taught in Part 9: Performance & Endurance

A thermal time constant is how long a part takes to get about two thirds of the way to a new temperature. Small parts heat in seconds, boards in minutes.

Taught in Throttle Lab

Threshold switching is a material conducting only once the voltage across it passes a threshold and stopping again when the voltage falls below a lower holding value.

Taught in Crosspoint Lab

Threshold voltage, Vt, is the gate voltage at which a flash cell starts to conduct. The stored charge shifts it, and the controller reads data from it.

Taught in Part 2: The Physics of Flash; also in Part 3: From Cell to Die, Part 4: 3D NAND Stacking

A throttle level is one step in a drive’s table of speed caps, from full speed down to the heaviest cap.

Taught in Throttle Lab

A through-silicon via is a vertical copper wire etched through a thinned die, so stacked dies can pass signals and power straight down.

Taught in Working Memory, Part 4: High Bandwidth Memory

Total ionizing dose is the radiation a part has absorbed over its life, counted in krad(Si), thousands of rad absorbed in silicon. Charge it leaves trapped in the oxides shifts the transistors until the part fails.

Taught in Signals

A trajectory, in robot learning, is one recorded run of a robot doing a task: its camera frames, joint positions and commands from start to finish.

Taught in Cogs and Cache

A transistor is an electronic switch, the basic building block of a chip, and a single modern chip can hold billions of them.

Taught in Photolithography, Part 1: How a Chip Is Printed With Light

The translation lookaside buffer is a small, fast cache of recent translations from virtual to physical memory addresses, so the processor does not have to work each one out again.

Taught in How Storage Works, Part 1: The Memory and Storage Hierarchy

TRIM, called Deallocate in NVMe, tells the drive which logical blocks the file system no longer uses, so garbage collection need not copy them.

Taught in Part 5: The Controller; also in Part 7: Garbage Collection & Wear, Leave a Quarter to Half of the Drive Empty

The tunnel oxide is the thin insulating layer between the channel and the charge-storage layer. Electrons cross it during program and erase, and it wears out.

Taught in Part 2: The Physics of Flash; also in Beyond NAND, Part 1: NOR and Memory on the Processor Die

A tweak is a public value mixed into encryption beside the key. XTS uses the sector address, so the same data at two addresses encrypts differently.

Taught in AES Engine Lab

U.2 and U.3 are 2.5-inch drive form factors with a PCIe connector. U.3 lets one backplane slot accept SAS, SATA or NVMe drives.

Taught in Part 1: Standards & Interfaces

UBI is a wear-leveling and volume management layer that runs on top of an MTD device. It hides wear and bad blocks from the file system above it.

Taught in Flash in Small Devices: Routers, Cameras and Watches

A UPIU is the message format UFS uses between host and device. Commands, task management requests, queries and their responses all travel as UPIUs.

Taught in UFS Explained: The Flash Storage Inside Your Phone

A uMCP is a multichip package that pairs UFS flash storage with LPDDR DRAM in one package.

Taught in Flash in Phones and Tablets: One Board, Two Memories

UHS is the family of faster SD card bus modes, UHS-I, UHS-II and UHS-III, that followed the original Default Speed and High Speed modes.

Taught in SD and microSD Cards: Classes, Bus Modes and SD Express

Uncorrectable bit error rate is the fraction of bits that are still wrong after error correction. Drive specifications use it as a reliability target.

Taught in Part 8: Error Correction & Integrity; also in Does an SSD Fail With No Warning?

A unipolar cell sets and resets with the same polarity, told apart by the height and length of the pulse, as phase-change cells are.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

UCIe is an open standard for the links between chiplets inside one package, so dies from different makers can be joined.

Taught in Memory and Storage for SI, Part 2: High Bandwidth Flash

Universal Flash Storage is the JEDEC flash storage standard for phones and mobile devices. Its serial link has separate read and write paths, so it reads and writes at once.

Taught in UFS Explained: The Flash Storage Inside Your Phone

A bridge chip in a portable SSD translates between the USB link to the computer and the NVMe drive inside. Some controllers speak USB natively and need none.

Taught in Storage and Memory in Practice, Part 6: Portable SSDs and Enclosures

Valence-change memory is a resistive memory in which oxygen vacancies move under the electric field and change how well an oxide layer conducts.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

Vertical pitch is the thickness of one wordline layer plus its insulator. A smaller pitch fits more layers into the same stack height.

Taught in Part 4: 3D NAND Stacking

Victim selection picks which block to reclaim. Greedy takes the one with the fewest valid pages, while cost-benefit also weighs how old the data is.

Taught in Part 7: Garbage Collection & Wear; also in Defrag Lab

A virtual ground is a node an amplifier holds at zero volts without wiring it to ground. Current can flow into it while its voltage stays put.

Taught in Crosspoint Lab

A volatile write cache is memory in a drive that holds a write after the drive reports it done and before the data reaches flash.

Taught in A Power Cut Does Not Wipe Your SSD; also in Follow a Read

Volume production is when a fab makes a product in full commercial quantities, past engineering samples and trial runs.

Taught in Fab Tracker

A volume shadow copy keeps old versions of changed blocks so Windows can restore them, and System Restore depends on it.

Taught in Defrag Lab

The von Neumann bottleneck is the cost of carrying data between a processor and a separate memory, which for large neural networks can exceed the cost of the arithmetic.

Taught in Crosspoint Lab

In glass storage, a voxel is a tiny three-dimensional mark a laser writes inside the glass, the way a pixel is a mark on a flat surface.

Taught in How Storage Works, Part 3: Tape and Cold Archive

VRAM is a graphics card’s own memory, soldered beside the GPU. A model or game scene that does not fit in it spills into slower system memory.

Taught in Understanding SI, Part 2: Running Language Models Locally on Windows; also in Best GPUs

A wafer is the thin disc of pure silicon that chips are built on, many at a time, before it is cut into separate dies.

Taught in Fab Tracker

Wafer capacity is how many wafers a fab can start in a month, the usual measure of how much a fab can make.

Taught in Fab Tracker

A watt is one joule of energy per second. Nearly every watt a drive draws ends up as heat.

Taught in Throttle Lab

WCTEMP is the warning temperature and CCTEMP the critical one. TMT1 and TMT2 are host-set points at which the drive starts to throttle.

Taught in Part 9: Performance & Endurance; also in Every NVMe SSD Needs a Heatsink, Throttle Lab

Wear leveling spreads erases evenly over all blocks. Dynamic leveling picks young blocks for new writes, while static leveling also moves cold data off them.

Taught in Part 7: Garbage Collection & Wear; also in The Memory Map: What Comes After Flash, Beyond NAND, Part 1: NOR and Memory on the Processor Die

A weighted sum multiplies each input by its own weight and adds the products. Most of the work in a neural network layer is weighted sums.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

A wordline is the conductor that crosses a row of cells and sets the gate voltage for every cell on it. One wordline holds one or more pages.

Taught in Part 3: From Cell to Die; also in Crosspoint Lab

Wordline metal carries the gate voltage along each layer. Tungsten is standard, and molybdenum is being introduced because it has lower resistance in thin films.

Taught in Part 4: 3D NAND Stacking

A workload rating is the most data a year, read and written, that a maker says a hard drive is built to move. Going over it can hurt its reliability.

Taught in How Storage Works, Part 2: How a Hard Drive Works; also in Best HDDs

Write amplification factor is the data written to NAND divided by the data the host wrote. A value of 1 means no extra internal writes.

Taught in Part 2: The Physics of Flash; also in Part 3: From Cell to Die, Part 5: The Controller

Write disturb is an unwanted change in an idle cell caused by the voltage it sees while a neighbor on the same line is written.

Taught in Crosspoint Lab

Write-verify writes a cell, reads it back and writes again until the value is close enough to the target, spending time and energy for a tighter result.

Taught in Beyond NAND, Part 5: Resistive Memory and Computing in the Crossbar; also in Crosspoint Lab

XMP from Intel and EXPO from AMD are memory profiles stored on a module that set faster speeds and timings than the standard ones when turned on in the BIOS.

Taught in Storage and Memory in Practice, Part 1: DDR5 for Builders; also in Best RAM

XOR compares two bits and gives a one when they differ. Applying the same XOR twice undoes it, which is why ciphers use it to mix in key bits.

Taught in Running a NAS, Part 2: Pools and Filesystems on a NAS; also in AES Engine Lab

XTS is the AES mode self-encrypting drives use for stored data. It mixes the sector address and the block position into every block, so no two places encrypt alike.

Taught in AES Engine Lab

Yield is the share of chips on a wafer that work. Chipmakers raise it by measuring each step and catching defects early.

Taught in Photolithography, Part 3: High-NA EUV and What It Means for Memory

zNAND-O is a Samsung concept for flash placed in the same package as a processor and joined to it over a die-to-die link that the October 2026 release names as UCIe. Samsung showed it as a concept model in August 2026, and it is not a shipping product.

Taught in Memory and Storage for SI, Part 3: zNAND-O

Zoned Namespaces split the drive into zones that must be written in order, which moves data placement to the host and removes most garbage collection.

Taught in Part 10: The Future of Flash; also in Memory and Storage for SI, Part 8: Where Memory Goes Next, Defrag Lab

zRAM is a part of RAM that serves as compressed swap space. The kernel can move cached pages into it, where they are compressed, which frees RAM.

Taught in Flash in Phones and Tablets: One Board, Two Memories