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    Webster’s Corner

    A reference desk for memory and storage engineers. The specs, standards, die papers, controller notes and talks are filed in numbered zones from the dies up, with flash and SSDs beside DRAM and HBM and the current spec at the top of each list. Every row links its own source.

    The 8 zones Maker news and patents All Timelines

    Theme: “Scheming Weasel (faster version)” by Kevin MacLeod (opens in a new tab), CC BY 4.0 (opens in a new tab).

    How to read it

    The desk holds 273 spec documents in 177 families, 476 papers and preprints (93 of them die papers), 35 talks and white papers and 28 controller notes, filed in 8 zones from the cells and dies up to what comes next. Each zone sets flash and SSDs beside DRAM and HBM. A spec family is one document across its revisions, so the newest revision leads its row and the earlier ones fold under it, and the standards timeline has their dated history.

    Pick a kind of entry or a standards body to see only those rows across every zone, or search for a document number or a word. Nothing here is copied, and a row with a short note carries Sean’s take. The newest entry is from November 2026.

    Zone 01

    Dies and cells90 die papers · 82 papers and talks

    Storage: NAND cells and flash dies. Memory: DRAM, LPDDR, GDDR and HBM dies.

    Storage, newest die paper
    3D Flash Memory Technology for the AI Era

    Storage NAND cells and flash dies

    Die papers 77

    PaperSourceDate
    3D Flash Memory Technology for the AI Era (opens in a new tab)Die paperDOI 10.1109/VLSITechnologyandCir65830.2026.11577464Kioxia's VLSI 2026 roadmap paper. No abstract in the public metadata yet, so the content needs a read before it goes into anything.VLSI Symposium 2026, Kioxia
    A Multi-Stacked Cell Array Architecture with Wafer-to-Wafer Cu Direct Bonding for Ultra-High-Density 3D Flash Memory beyond 1,000 Word Lines (opens in a new tab)Die paperDOI 10.1109/VLSITechnologyandCir65830.2026.11577274Kioxia and Sandisk bond two cell-array wafers of 218 word lines each onto one CMOS wafer and show QLC working on a prototype. It is their route past 1,000 word lines without building one tall stack.VLSI Symposium 2026 (paper T1.4), Kioxia and Sandisk
    NAND Flash Memory: Boundless Battle Against Capacity and Performance (opens in a new tab)Die paperDOI 10.1109/IMW68301.2026.11532921Samsung design review on NAND's cell area versus peripheral area problem and why SI data center SSDs now push performance as hard as capacity.IEEE IMW 2026, Samsung Electronics
    An Ideal Approach to 3D NAND Flash Design for Ultra-High IOPS SSDs (>100M) with Low-Latency (<=us), Fine-Grained (Page Size=512B), and a Novel MB-level Embedded DRAM to support On-Chip NAND Managements (opens in a new tab)Die paperDOI 10.1109/imw68301.2026.115328642026 IEEE International Memory Workshop (IMW)
    CMOS directly Bonded to Array (CBA) Architecture and Manufacturing Challenges of 3D Flash Memory (opens in a new tab)Die paperDOI 10.1109/EDTM65772.2026.11497359Kioxia on what it takes to build CBA in volume: wafer-to-wafer Cu direct bonding and the CMP control behind it. Good primary source for any bonded-array explainer.IEEE EDTM 2026, Kioxia
    A 2Tb 4b/Cell 6-Plane 3D-Flash Memory with 37.6Gb/mm² Bit Density and >85MB/s Write Throughput (opens in a new tab)Die paperDOI 10.1109/ISSCC49663.2026.11409136BiCS10 QLC: 332 word line layers, 37.6Gb/mm², under 65µs read and over 85MB/s program. Highest QLC bit density reported at ISSCC so far.On the NAND Die Timeline ISSCC 2026 (paper 15.1), Kioxia and Sandisk
    Bandgap-Engineered Boron Oxynitride Tunneling Layer for Reliable PLC operation of 3D V-NAND Flash Memory Devices (opens in a new tab)Die paperDOI 10.1109/IEDM50572.2025.11353681Swapping SiON for boron oxynitride in the tunnel stack gave 9x faster erase fresh and 23x after cycling, with less trap generation. Aimed squarely at PLC.IEDM 2025, KAIST and Samsung Electronics
    A 28-Gb/mm2 4XX-Layer 1-Tb 3-b/Cell WF-Bonding 3D-NAND Flash With 5.6-Gb/s/Pin IOs (opens in a new tab)Die paperDOI 10.1109/JSSC.2025.3613774The journal version of Samsung’s tenth-generation die: a wafer-bonded vertical NAND with three stacks of 4XX word lines, no dummy holes and 5.6Gb/s per pin.On the NAND Die Timeline IEEE JSSC 2025, Samsung Electronics (journal version of ISSCC 2025 paper 30.1)
    A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os (opens in a new tab)Die paperDOI 10.1109/ISSCC49661.2025.10904509CBA TLC with 4.8Gb/s power-isolated low-tapped-termination I/O and 29% better read energy efficiency. Kioxia's release ties it to Toggle DDR6.0 and a separate command/address bus.ISSCC 2025 (paper 30.2), Kioxia and Western Digital (now Sandisk); Kioxia release 2025-02-19: https://apac.kioxia.com/en-apac/business/news/2025/20250220-1.html
    A 28Gb/mm² 4XX-Layer 1Tb 3b/Cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/Pin IOs (opens in a new tab)Die paperDOI 10.1109/ISSCC49661.2025.10904543Samsung's wafer-bonded 4XX-layer TLC: dummy holes removed, a coded-GSL scheme to cut unselected string power, and 5.6Gb/s per pin.ISSCC 2025 (paper 30.1), Samsung Electronics; extended in IEEE JSSC 2026 (doi 10.1109/JSSC.2025.3613774)
    A 321-Layer 2Tb 4b/cell 3D-NAND-Flash Memory with a 75MB/s Program Throughput (opens in a new tab)Die paperDOI 10.1109/ISSCC49661.2025.10904748SK hynix's 321-layer QLC: 2Tb per die, six planes and 75MB/s program. The QLC part to measure later dies against.On the NAND Die Timeline ISSCC 2025, SK hynix; six-plane detail from the ISSCC 2025 press kit
    NAND Flash Innovations and Future Scaling (opens in a new tab)Die paperDOI 10.1109/IEDM50854.2024.10873543Goda's history and outlook: 2D cells from 1µm to about 15nm, 3D at about 300 layers, and over a million-fold areal density gain in 37 years.IEDM 2024, Micron (Akira Goda)
    Spatial Charge Trap Engineering with Boron Nitride Barrier for 3D V-NAND Flash Memory (opens in a new tab)Die paperDOI 10.1109/IEDM50854.2024.10873581A 1nm BN layer inside a 4nm SiN trap layer: over 20% more memory window, 44% better hole retention, over 10x faster erase. XY scaling via the charge trap.IEDM 2024, KAIST and Samsung Electronics
    A Confined Storage Nitride 3D-NAND Cell with WL Airgap for Cell-To-Cell Interference Reduction and Improved Program Performances (opens in a new tab)Die paperDOI 10.1109/VLSITechnologyandCir46783.2024.10631512Micron cuts the nitride per cell and puts air gaps between word lines: less cell-to-cell interference, less lateral charge loss, faster tPROG. Their path to tighter tier pitch.VLSI Symposium 2024, Micron
    Innovative Barrier Metal-Less Metal Gate Scheme Leading to Highly Reliable Cell Characteristics for 8th Generation 512Gb 3D NAND Flash Memory (opens in a new tab)Die paperDOI 10.1109/VLSITechnologyandCir46783.2024.10631433Dropping the barrier metal cut word line resistance 30% on Samsung's 8th generation 512Gb part, which let the block shrink laterally. Fluorine passivation handled interference and charge loss.VLSI Symposium 2024, Samsung Electronics
    A 1Tb Density 3b/Cell 3D-NAND Flash on a 2YY-Tier Technology with a 300MB/s Write Throughput (opens in a new tab)Die paperDOI 10.1109/ISSCC49657.2024.10454296Micron's 2YY-tier TLC with six planes, 3.6GT/s transfers and 300MB/s write. Six planes per die matters for low-die-count client drives.ISSCC 2024 (paper 13.7), Micron
    A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm² Areal Density and a 3.2GB/s High-Speed IO Rate (opens in a new tab)Die paperDOI 10.1109/ISSCC49657.2024.10454343Samsung's 280-layer QLC at 28.5Gb/mm². The interesting part is the fix for QLC reprogram overhead: coded-data on-chip buffered program and fewer 16-state verifies.On the NAND Die Timeline ISSCC 2024 (paper 13.3), Samsung Electronics
    A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3Gb/mm2 Bit Density (opens in a new tab)Die paperDOI 10.1109/isscc42615.2023.10067616On the NAND Die Timeline 2023 IEEE International Solid-State Circuits Conference (ISSCC)
    28.2 A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers (opens in a new tab)Die paperDOI 10.1109/isscc42615.2023.10067666On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface (opens in a new tab)Die paperDOI 10.1109/isscc42614.2022.9731110On the NAND Die Timeline 2022 IEEE International Solid- State Circuits Conference (ISSCC)
    A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface (opens in a new tab)Die paperDOI 10.1109/isscc42614.2022.9731640On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 1-Tb, 4b/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8Gb/mm2 Density (opens in a new tab)Die paperDOI 10.1109/isscc42614.2022.9731785On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density (opens in a new tab)Die paperDOI 10.1109/isscc42613.2021.9365777Intel’s 144-tier floating-gate QLC die holds 1Tb at 13.8Gb/mm² with 40MB/s program throughput, following two generations of floating-gate QLC it had already shipped.On the NAND Die Timeline ISSCC 2021 (paper 30.2), Intel
    A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology (opens in a new tab)Die paperDOI 10.1109/isscc42613.2021.9366003Kioxia and Western Digital’s 1Tb TLC die on more than 170 word-line layers reaches 10.4Gb/mm², 33% denser than prior TLC work, with asynchronous independent plane reads and a 2.0Gb/s interface.On the NAND Die Timeline ISSCC 2021 (paper 30.4), Kioxia and Western Digital
    A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface (opens in a new tab)Die paperDOI 10.1109/isscc42613.2021.9366054Samsung’s seventh-generation 3D NAND moves the peripheral circuits under the cell array to shrink a 512Gb TLC die and reports 184MB/s write throughput and a 2.0Gb/s interface.On the NAND Die Timeline ISSCC 2021 (paper 30.3), Samsung Electronics
    A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture (opens in a new tab)Die paperDOI 10.1109/isscc42613.2021.9365809SK hynix stacks 176 word lines for a 512Gb TLC die at 10.8Gb/mm² with the peripheral circuits under the cell array, and lists the load, capacitance and RC delay problems taller stacks bring.On the NAND Die Timeline ISSCC 2021 (paper 30.1), SK hynix
    A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems (opens in a new tab)Die paperDOI 10.1109/vlsicircuits18222.2020.9163052IEEE Symposium on VLSI Circuits
    4 bits/cell 96 Layer Floating Gate 3D NAND with CMOS under Array Technology and SSDs (opens in a new tab)Die paperDOI 10.1109/imw48823.2020.9108135Intel describes its 96-layer floating-gate QLC NAND with CMOS under the array and says more than 10 million QLC SSDs built on it had shipped for client and data center use.On the NAND Die Timeline IEEE IMW 2020, Intel
    13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate (opens in a new tab)Die paperDOI 10.1109/isscc19947.2020.9063053On the NAND Die Timeline 2020 IEEE International Solid-State Circuits Conference - (ISSCC)
    13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique (opens in a new tab)Die paperDOI 10.1109/isscc19947.2020.9063117On the NAND Die Timeline 2020 IEEE International Solid- State Circuits Conference - (ISSCC)
    A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75μs and tR=4μs (opens in a new tab)Die paperDOI 10.1109/isscc19947.2020.9063154ISSCC 2020 (paper 13.5)
    A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism (opens in a new tab)Die paperDOI 10.1109/tvlsi.2019.2905626IEEE Transactions on Very Large Scale Integration (VLSI) Systems
    A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface (opens in a new tab)Die paperDOI 10.1109/isscc.2019.8662493Samsung’s sixth-generation V-NAND puts 512Gb at 3 bits per cell on one die with 82MB/s write throughput and a 1.2Gb/s interface, and names channel-hole etch and cell interference as the limits of taller stacks.On the NAND Die Timeline ISSCC 2019 (paper 13.4), Samsung Electronics
    A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology (opens in a new tab)Die paperDOI 10.1109/isscc.2019.8662445Toshiba and Western Digital’s 128-layer 512Gb TLC die reaches 7.80Gb/mm², 31% denser than the 96-layer report before it, using four planes with circuits under the array, multi-die peak power management and a 4KB page read.On the NAND Die Timeline ISSCC 2019 (paper 13.5), Toshiba and Western Digital
    A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology (opens in a new tab)Die paperDOI 10.1109/isscc.2018.8310321On the NAND Die Timeline 2018 IEEE International Solid - State Circuits Conference - (ISSCC)
    A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput (opens in a new tab)Die paperDOI 10.1109/isscc.2018.8310323On the NAND Die Timeline 2018 IEEE International Solid-State Circuits Conference - (ISSCC)
    A 1.2V 1.33Gb/s/pin 8Tb NAND Flash Memory Multi-Chip Package Employing F-Chip for Low Power and High Performance Storage Applications (opens in a new tab)Die paperDOI 10.23919/vlsic.2017.8008479IEEE Symposium on VLSI Circuits 2017 (paper C15-3)
    A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology (opens in a new tab)Die paperDOI 10.1109/isscc.2017.7870328Toshiba and Western Digital’s 64-layer BiCS die stores 512Gb at 3 bits per cell and adds four-block even-odd row decoding, unselected string pre-charge and shielded bit-line sensing to handle the taller stack.On the NAND Die Timeline ISSCC 2017 (paper 11.1), Toshiba and Western Digital
    NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices (opens in a new tab)Die paperDOI 10.1109/tvlsi.2015.2409055IEEE Transactions on Very Large Scale Integration (VLSI) Systems
    A 768Gb 3b/cell 3D-Floating-Gate NAND Flash Memory (opens in a new tab)Die paperDOI 10.1109/isscc.2016.7417947Intel and Micron’s 3D floating-gate die stores 768Gb at 3 bits per cell and reaches 4.29Gb/mm², against the 1.86Gb/mm² the paper cites for charge-trap V-NAND.On the NAND Die Timeline ISSCC 2016 (paper 7.7), Intel and Micron
    A 128Gb 2b/cell NAND Flash Memory in 14nm Technology with tPROG=640µs and 800MB/s I/O Rate (opens in a new tab)Die paperDOI 10.1109/isscc.2016.7417945Samsung’s 128Gb MLC planar die in 14nm uses 150 cells per string and reaches a 640µs program time and an 800MB/s I/O rate, with techniques to offset the reliability cost of the smaller transistors.On the NAND Die Timeline ISSCC 2016 (paper 7.5), Samsung Electronics
    Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations (opens in a new tab)Die paperDOI 10.1109/jssc.2015.2413841IEEE Journal of Solid-State Circuits
    7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology (opens in a new tab)Die paperDOI 10.1109/isscc.2015.7062959On the NAND Die Timeline ISSCC (IEEE Xplore)
    7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate (opens in a new tab)Die paperDOI 10.1109/isscc.2015.7062960On the NAND Die Timeline ISSCC (IEEE Xplore)
    Three-Dimensional 128 Gb MLC Vertical NAND Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming (opens in a new tab)Die paperDOI 10.1109/jssc.2014.2352293On the NAND Die Timeline IEEE Journal of Solid-State Circuits, vol. 50, no. 1 (IEEE Xplore)
    19.1 A 128Gb MLC NAND-Flash device using 16nm planar cell (opens in a new tab)Die paperDOI 10.1109/isscc.2014.6757454On the NAND Die Timeline ISSCC (IEEE Xplore)
    19.2 A 93.4mm2 64Gb MLC NAND-flash memory with 16nm CMOS technology (opens in a new tab)Die paperDOI 10.1109/isscc.2014.6757455On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology (opens in a new tab)Die paperDOI 10.1109/isscc.2013.6487707On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 19 nm 112.8 mm² 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface (opens in a new tab)Die paperDOI 10.1109/jssc.2012.2215094IEEE Journal of Solid-State Circuits
    A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface (opens in a new tab)Die paperDOI 10.1109/isscc.2012.6177073On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology (opens in a new tab)Die paperDOI 10.1109/isscc.2012.6177077On the NAND Die Timeline ISSCC (IEEE Xplore)
    128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode (opens in a new tab)Die paperDOI 10.1109/isscc.2012.6177080On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 151mm2 64Gb MLC NAND flash memory in 24nm CMOS technology (opens in a new tab)Die paperDOI 10.1109/isscc.2011.5746280On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOS (opens in a new tab)Die paperDOI 10.1109/isscc.2011.5746282On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology (opens in a new tab)Die paperDOI 10.1109/isscc.2011.5746287On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 159mm2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface (opens in a new tab)Die paperDOI 10.1109/isscc.2010.5433912On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 32Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes in 32nm CMOS (opens in a new tab)Die paperDOI 10.1109/isscc.2010.5433932On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s (opens in a new tab)Die paperDOI 10.1109/isscc.2010.5433949On the NAND Die Timeline 2010 IEEE International Solid-State Circuits Conference - (ISSCC)
    A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS (opens in a new tab)Die paperDOI 10.1109/isscc.2009.4977395On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 48nm 32Gb 8-level NAND flash memory with 5.5MB/s program throughput (opens in a new tab)Die paperDOI 10.1109/isscc.2009.4977397On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 113mm2 32Gb 3b/cell NAND flash memory (opens in a new tab)Die paperDOI 10.1109/isscc.2009.4977398On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS (opens in a new tab)Die paperDOI 10.1109/isscc.2009.4977400On the NAND Die Timeline ISSCC (IEEE Xplore)
    A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure (opens in a new tab)Die paperDOI 10.1109/jssc.2008.2006437IEEE Journal of Solid-State Circuits
    A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm (opens in a new tab)Die paperDOI 10.1109/isscc.2008.4523236On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface (opens in a new tab)Die paperDOI 10.1109/isscc.2008.4523239On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology (opens in a new tab)Die paperDOI 10.1109/isscc.2008.4523241On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 16Gb 3b/Cell NAND Flash Memory in 56nm with 8MB/s Write Rate (opens in a new tab)Die paperDOI 10.1109/isscc.2008.4523279On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure (opens in a new tab)Die paperDOI 10.1109/isscc.2008.4523281On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 70nm 16Gb 16-level-cell NAND Flash Memory (opens in a new tab)Die paperDOI 10.1109/vlsic.2007.4342710On the NAND Die Timeline VLSI Circuits (IEEE Xplore)
    A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory (opens in a new tab)Die paperDOI 10.1109/iedm.2006.346903IEDM
    A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput (opens in a new tab)Die paperDOI 10.1109/isscc.2006.1696083On the NAND Die Timeline ISSCC (IEEE Xplore)
    A 146-mm2 8-Gb Multi-Level NAND Flash Memory With 70-nm CMOS Technology (opens in a new tab)Die paperDOI 10.1109/jssc.2005.859027On the NAND Die Timeline IEEE JSSC (IEEE Xplore)
    Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node (opens in a new tab)Die paperDOI 10.1109/iedm.2006.346902IEDM
    A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications (opens in a new tab)Die paperDOI 10.1109/jssc.2003.818143On the NAND Die Timeline IEEE JSSC (IEEE Xplore)
    High-performance 1-Gb-NAND flash memory with 0.12-um technology (opens in a new tab)Die paperDOI 10.1109/jssc.2002.802352On the NAND Die Timeline IEEE JSSC (IEEE Xplore)
    A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed (opens in a new tab)Die paperDOI 10.1109/jssc.2002.802355On the NAND Die Timeline IEEE JSSC (IEEE Xplore)
    A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme (opens in a new tab)Die paperDOI 10.1109/4.475701IEEE Journal of Solid-State Circuits

    Foundational 6

    WorkSourceDate
    A floating gate and its application to memory devices (opens in a new tab)PaperDOI 10.1002/j.1538-7305.1967.tb01738.xBell System Technical Journal
    A new flash E2PROM cell using triple polysilicon technology (opens in a new tab)PaperDOI 10.1109/iedm.1984.190752IEDM
    New ultra high density EPROM and flash EEPROM with NAND structure cell (opens in a new tab)PaperDOI 10.1109/iedm.1987.191485IEDM
    Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory (opens in a new tab)PaperDOI 10.1109/vlsit.2007.4339708VLSI Technology
    Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory (opens in a new tab)PaperVLSI Technology
    Three-dimensional 128Gb MLC vertical NAND flash memory with 24-WL stacked layers and 50MB/s high-speed programming (opens in a new tab)Die paperDOI 10.1109/isscc.2014.6757458ISSCC 2014 (paper 19.5), Samsung Electronics

    Papers, talks and releases 70

    TitleSourceDate
    The future of 3D NAND flash technology (opens in a new tab)PreprintarXiv
    QLC Storage in Hyperscale Fleet (opens in a new tab)PresentationMeta makes its case for QLC SSDs in the fleet: write throughput beyond what hard drives manage, with better rack density and power than TLC, at 0.25 to 0.6 drive writes per day.OCP Global Summit
    High Capacity QLC Innovation (opens in a new tab)PresentationFour storage vendors discuss QLC SSDs from 32TB up to 512TB, including how to cut the controller DRAM that holds the logical-to-physical table.OCP Global Summit
    Graceful Degradation for the QLC Era: Moving SSD Lifecycle Management to the Host (opens in a new tab)PresentationProposes host-managed over-provisioning so a QLC drive shrinks its capacity as blocks fail instead of retiring while most of its media still works.SDC
    Maximizing E3.L 2T: Engineering Ultra-Dense QLC SSDs (opens in a new tab)PresentationWalks through filling the tall E3.L 2T form factor with QLC NAND to challenge nearline hard drives, covering signal integrity, controller placement and power and thermal limits.SDC
    Oxide semiconductor gain cell-embedded memory: materials and integration strategies for next generation on-chip memory (opens in a new tab)PaperDOI 10.1038/s44172-026-00616-5Communications Engineering (Nature Portfolio)
    A 29-Gb/mm2 1-Tb 3-b/Cell 3-D Flash Memory With CMOS Direct Bonded Array (CBA) Technology (opens in a new tab)PaperOn the NAND Die Timeline IEEE JSSC
    PDA-LSTM: page data arrangement for LCM suppression in QLC 3D NAND (opens in a new tab)PreprintarXiv
    Modeling methodology for thermo-structural analysis of V-NAND flash memory structure (opens in a new tab)PaperDOI 10.1038/s41598-025-89936-8Scientific Reports
    Channel Potential of Bandgap-Engineered Tunneling Oxide (BE-TOX) in Inhibited 3D NAND Flash Memory Strings (opens in a new tab)PaperDOI 10.3390/electronics13081573MDPI Electronics
    Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory (opens in a new tab)PaperDOI 10.3390/eng5010027MDPI Eng
    An Optimized Device Structure with Improved Erase Operation within the IGZO Channel in 3D NAND Flash Applications (opens in a new tab)PaperDOI 10.3390/electronics13020451MDPI Electronics
    Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory (opens in a new tab)PaperDOI 10.3390/mi14101916Micromachines
    A Study of Invalid Programming in 3D QLC NAND Flash Memories (opens in a new tab)PaperDOI 10.1145/3599691.3603414HotStorage
    Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash (opens in a new tab)PaperDOI 10.3390/mi14030686Micromachines
    A Review of Cell Operation Algorithm for 3D NAND Flash Memory (opens in a new tab)PaperDOI 10.3390/app122110697Applied Sciences
    Modeling Incomplete Conformality during Atomic Layer Deposition in High Aspect Ratio Structures (opens in a new tab)PreprintarXiv
    Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory (opens in a new tab)PreprintarXiv
    Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory (opens in a new tab)PaperDOI 10.3390/electronics11172738Electronics
    Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages (opens in a new tab)PaperDOI 10.3390/mi13071139Micromachines
    Recent Progress on 3D NAND Flash Technologies (opens in a new tab)PaperDOI 10.3390/electronics10243156Electronics
    Architecture and Process Integration Overview of 3D NAND Flash Technologies (opens in a new tab)PaperDOI 10.3390/app11156703Applied Sciences
    All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash (opens in a new tab)PaperDOI 10.1109/access.2021.3058391IEEE Access
    A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs (opens in a new tab)PaperDOI 10.1109/jssc.2020.3028393On the NAND Die Timeline IEEE Journal of Solid-State Circuits
    Implementation of Data Search in Multi-Level NAND Flash Memory by Complementary Storage Scheme (opens in a new tab)PaperDOI 10.1109/led.2020.3004989IEEE Electron Device Letters
    Berry curvature memory through electrically driven stacking transitions (opens in a new tab)PaperDOI 10.1038/s41567-020-0947-0Nature Physics
    Centaur (opens in a new tab)PaperDOI 10.1145/3392146Proceedings of the ACM on Measurement and Analysis of Computing Systems
    A Novel quasi-SLC(qSLC) Program/Erase Scheme in Ultra-Densified Charge-trapping 3D NAND Flash Memory to Enhance System Level Performance (opens in a new tab)PaperDOI 10.1109/snw50361.2020.9131660IEEE Silicon Nanoelectronics Workshop (SNW)
    A Real-Time Non-Volatile Memory Analyzer and its Use on the Evaluation of Storage Devices based on NAND Flash Memories (opens in a new tab)PaperDOI 10.1109/i2mtc43012.2020.9128931IEEE I2MTC
    3-D NAND Technology Achievements and Future Scaling Perspectives (opens in a new tab)PaperDOI 10.1109/ted.2020.2968079IEEE Transactions on Electron Devices
    A novel solution to improve saddle-shape warpage in 3D NAND flash memory (opens in a new tab)PaperDOI 10.1088/1361-6641/ab73ebSemiconductor Science and Technology
    Optimal dummy word line condition to suppress hot carrier injection phenomenon due to the natural local self-boosting effect in 3D NAND flash memory (opens in a new tab)PaperDOI 10.35848/1347-4065/ab6b77Japanese Journal of Applied Physics
    Investigation of Inhibited Channel Potential of 3D NAND Flash Memory According to Word-Line Location (opens in a new tab)PaperDOI 10.3390/electronics9020268Electronics
    A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology (opens in a new tab)PaperDOI 10.1109/jssc.2019.2941758On the NAND Die Timeline IEEE Journal of Solid-State Circuits
    Performance Enhancement of 3-D NAND Flash Featuring a Two-Step Dummy Wordline Program Waveform and Pair-Bitline Program Scheme (opens in a new tab)PaperDOI 10.1109/ted.2019.2951460IEEE Transactions on Electron Devices
    3D analysis of high-aspect ratio features in 3D-NAND (opens in a new tab)PaperDOI 10.1117/12.2552006Proc. SPIE 11325
    SPA-SSD: Exploit Heterogeneity and Parallelism of 3D SLC-TLC Hybrid SSD to Improve Write Performance (opens in a new tab)PaperDOI 10.1109/iccd46524.2019.000882019 IEEE 37th International Conference on Computer Design (ICCD)
    Enhancement of the Electrical Characteristics for 3D NAND Flash Memory Devices Due to a Modified Cell Structure in the Gate Region (opens in a new tab)PaperDOI 10.1166/jnn.2019.17017Journal of Nanoscience and Nanotechnology
    FlashGPU (opens in a new tab)PaperDOI 10.1145/3316781.3317827Proceedings of the 56th Annual Design Automation Conference
    SOML Read (opens in a new tab)PaperDOI 10.1145/3297858.3304035Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems
    What Will Come After V‐NAND-Vertical Resistive Switching Memory? (opens in a new tab)PaperDOI 10.1002/aelm.201800914Advanced Electronic Materials
    A Behavioral Compact Model of 3D NAND Flash Memory (opens in a new tab)PreprintarXiv
    PA-SSD: A Page-Type Aware TLC SSD for Improved Write/Read Performance and Storage Efficiency (opens in a new tab)PaperDOI 10.1145/3205289.3205319ICS
    Space Program Scheme for 3-D NAND Flash Memory Specialized for the TLC Design (opens in a new tab)PaperDOI 10.1109/vlsit.2018.8510660IEEE Symposium on VLSI Technology
    Barrier-Enabled IO Stack for Flash Storage (FAST '18) (opens in a new tab)Paperusenix.org
    The CASE of FEMU: Cheap, Accurate, Scalable and Extensible Flash Emulator (FAST '18) (opens in a new tab)Paperusenix.org
    A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory-based SSDs (opens in a new tab)PaperDOI 10.1002/cpe.4420Concurrency and Computation: Practice and Experience
    A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory (opens in a new tab)PaperDOI 10.1109/jssc.2017.2731813On the NAND Die Timeline IEEE Journal of Solid-State Circuits
    An advanced SLC-buffering for TLC NAND flash-based storage (opens in a new tab)PaperDOI 10.1109/tce.2017.015070IEEE Transactions on Consumer Electronics
    3D NAND Flash Based on Planar Cells (opens in a new tab)PaperDOI 10.3390/computers6040028Computers
    Architectural and Integration Options for 3D NAND Flash Memories (opens in a new tab)PaperDOI 10.3390/computers6030027Computers
    QLC NAND study and enhanced Gray coding methods for sixteen-level-based program algorithms (opens in a new tab)PaperDOI 10.1016/j.mejo.2017.05.019Microelectronics Journal
    256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers (opens in a new tab)PaperDOI 10.1109/jssc.2016.2604297On the NAND Die Timeline IEEE Journal of Solid-State Circuits
    Modeling Size Limitations of Resistive Crossbar Array With Cell Selectors (opens in a new tab)PaperDOI 10.1109/tvlsi.2016.2570120IEEE Transactions on VLSI Systems
    An Integrated Approach for Managing Read Disturbs in High-Density NAND Flash Memory (opens in a new tab)PaperDOI 10.1109/tcad.2015.2504868IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate (opens in a new tab)PaperDOI 10.1109/jssc.2015.2474117On the NAND Die Timeline IEEE Journal of Solid-State Circuits
    First detection of single-electron charging of the floating gate of NAND Flash memory cells (opens in a new tab)PaperDOI 10.1109/led.2014.2377774IEEE Electron Device Letters
    Overview of 3D NAND Flash and Progress of Split-Page 3D Vertical Gate (3DVG) NAND Architecture (opens in a new tab)PaperDOI 10.1109/icsict.2014.7021429IEEE ICSICT
    Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH (opens in a new tab)PaperDOI 10.1109/jssc.2013.2237974IEEE Journal of Solid-State Circuits
    Anatomy of a solid-state drive (opens in a new tab)PaperDOI 10.1145/2380656.2380672Communications of the ACM
    Reducing SSD Read Latency via NAND Flash Program and Erase Suspension (opens in a new tab)PaperUSENIX FAST
    Perpendicular switching of a single ferromagnetic layer by in-plane current injection (opens in a new tab)PaperDOI 10.1038/nature10309Nature
    Design Technology for 64 Gbit 2-Bit Multilevel-Cell NAND Flash Memory Using 24 nm Process (Toshiba Review Vol.66 No.9, Japanese with English abstract; authors Fukuda, Sato, Edahiro) (opens in a new tab)PaperOn the NAND Die Timeline Toshiba Corporation
    Understanding Intrinsic Characteristics and System Implications of Flash Memory based Solid State Drives (opens in a new tab)PaperDOI 10.1145/1555349.1555371ACM SIGMETRICS
    Integrating NAND flash devices onto servers (opens in a new tab)PaperDOI 10.1145/1498765.1498791Communications of the ACM
    ISSCC 2009 Advance Program (paper summaries) (opens in a new tab)PaperOn the NAND Die Timeline ISSCC
    Improving NAND Flash Based Disk Caches (opens in a new tab)PaperDOI 10.1109/isca.2008.322008 International Symposium on Computer Architecture
    A 45nm 4Gb 3-dimensional double-stacked multi-level NAND flash memory with shared bitline structure (opens in a new tab)PaperOn the NAND Die Timeline ISSCC
    Nonvolatile Erasable Flash NAND Memories (author slides, IEEE SSCS Santa Clara Valley chapter talk, 2008-04-17) (opens in a new tab)PaperOn the NAND Die Timeline SanDisk (R. A. Cernea); hosted by IEEE SSCS Santa Clara Valley Chapter
    An Analysis of Data Corruption in the Storage Stack (opens in a new tab)PaperUSENIX FAST

    Memory DRAM, LPDDR, GDDR and HBM dies

    Die papers 11

    PaperSourceDate
    A 36GB 3.3TB/S HBM4 DRAM with Per-Channel TSV RDQS Auto Calibration and Fully-Programmable MBIST (opens in a new tab)Die paperDOI 10.1109/isscc49663.2026.11409139ISSCC 2026 (paper 15.6)
    A 48Gb/s 24Gb GDDR7 DRAM for Mid-Range Inference AI with Symmetric 2CH-Mode Operation, Clock-Path Optimization, and RAS Features (opens in a new tab)Die paperDOI 10.1109/isscc49663.2026.11409122ISSCC 2026 (paper 15.9)
    A 16Gb 12.8Gb/s LPDDR6 SDRAM with 12-DQ/Sub-Channel Wide NRZ Signaling and Enhanced Reliability by Per-Row Activation Counting and Meta-Data Scheme (opens in a new tab)Die paperDOI 10.1109/isscc49663.2026.11409018ISSCC
    A 1cnm 14.4Gb/s/pin 16Gb LPDDR6 SDRAM with Efficiency Mode, LDO-Based WCK Tree, Dynamic Write NT-ODT, Fast CS Control and System Meta Mode (opens in a new tab)Die paperDOI 10.1109/isscc49663.2026.11409121ISSCC
    A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction (opens in a new tab)Die paperDOI 10.1109/isscc49661.2025.10904689ISSCC 2025 (paper 30.3)
    A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process (opens in a new tab)Die paperDOI 10.1109/isscc49661.2025.10904794ISSCC
    A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process (opens in a new tab)Die paperDOI 10.1109/isscc49657.2024.10454327ISSCC 2024 (paper 13.2)
    A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration (opens in a new tab)Die paperDOI 10.1109/isscc49657.2024.10454354ISSCC 2024 (paper 13.6)
    A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL (opens in a new tab)Die paperDOI 10.1109/isscc42615.2023.10067651ISSCC 2023 (paper 28.7)
    A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection (opens in a new tab)Die paperDOI 10.1109/isscc42615.2023.10067736ISSCC
    1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual clock input latch scheme and hybrid multi-oxide output buffer (opens in a new tab)Die paperDOI 10.1109/vlsic.2004.1346494IEEE (2004 Symposium on VLSI Circuits)

    Foundational 2

    WorkSourceDate
    Design of ion-implanted MOSFET's with very small physical dimensions (opens in a new tab)PaperDOI 10.1109/jssc.1974.1050511IEEE Journal of Solid-State Circuits
    A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV (opens in a new tab)Die paperDOI 10.1109/isscc.2014.6757501ISSCC 2014 (paper 25.2), SK hynix

    Papers, talks and releases 6

    TitleSourceDate
    Toward absolute CD reproducibility: active environmental control for next-generation HBM mask manufacturing (opens in a new tab)PaperDOI 10.1117/12.3118195SPIE Photomask Technology
    M3D-FLOW: A Monolithic 3-D-Stackable Processing-Near-DRAM Architecture for Generative Normalizing Flow Applications (opens in a new tab)PreprintarXiv (cs.AR), accepted in IEEE TCAD
    STARFISH: Scalable TSV Architecture for Repairing Faults in Stacked HBM (opens in a new tab)PaperDOI 10.1109/tcad.2026.3741780IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems (opens in a new tab)PaperDOI 10.1145/3123939.3124545MICRO-50 (IEEE/ACM International Symposium on Microarchitecture)
    Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics (opens in a new tab)PaperDOI 10.1145/1815961.1815978ISCA
    Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics (opens in a new tab)PaperDOI 10.1109/hoti.2008.11IEEE Hot Interconnects (HOTI)

    Zone 02

    Chip interfaces25 current specs · 18 papers and talks

    Storage: ONFI, Toggle and xSPI. Memory: DDR, LPDDR, GDDR and HBM buses.

    Storage ONFI, Toggle and xSPI

    Current specs 6

    DocumentBodyLatest
    JEDEC JESD230G.02 NAND Flash Interface Interoperability (opens in a new tab)Latest revisionOn the Standards page
    3 earlier revisions
    1. JEDEC JESD230D NAND Flash Interface Interoperability (opens in a new tab)
    2. NAND Flash Interface Interoperability (opens in a new tab)
    3. JEDEC JESD230B NAND Flash Interface Interoperability (opens in a new tab)
    		JEDEC
    eXpanded Serial Peripheral Interface (xSPI) for Nonvolatile Memory Devices, JESD251D (opens in a new tab)StandardJEDEC
    Serial Flash Reset Signaling Protocol, JESD252A (opens in a new tab)StandardJEDEC
    Open NAND Flash Interface Specification Revision 6.0 (opens in a new tab)Latest revision
    14 earlier revisions
    1. ONFI 5.2 specification (opens in a new tab)
    2. Open NAND Flash Interface Specification Revision 5.1 (opens in a new tab)
    3. Open NAND Flash Interface Specification Revision 5.0 (opens in a new tab)
    4. Open NAND Flash Interface Specification Revision 4.2 (opens in a new tab)
    5. Open NAND Flash Interface Specification Revision 4.1 (opens in a new tab)
    6. Open NAND Flash Interface Specification Revision 4.0 (opens in a new tab)
    7. Open NAND Flash Interface Specification Revision 3.2 (opens in a new tab)
    8. Open NAND Flash Interface Specification Revision 3.1 (opens in a new tab)
    9. Open NAND Flash Interface Specification Revision 3.0 (opens in a new tab)
    10. Open NAND Flash Interface Specification Revision 2.3a (opens in a new tab)
    11. Open NAND Flash Interface Specification Revision 2.2 (opens in a new tab)
    12. Open NAND Flash Interface Specification Revision 2.1 (opens in a new tab)
    13. Open NAND Flash Interface Specification Revision 2.0 (opens in a new tab)
    14. Open NAND Flash Interface Specification Revision 1.0 (opens in a new tab)
    		ONFI
    Serial Flash Discoverable Parameters (SFDP), JESD216H (opens in a new tab)StandardJEDEC
    SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI), JESD255 (opens in a new tab)StandardJEDEC

    Papers, talks and releases 3

    TitleSourceDate
    JEDEC Announces Enhanced NAND Flash Interface Standard (opens in a new tab)StandardOn the Standards page JEDEC
    Impact of Read Enable (RE) Signal Duty Cycle Distortion (DCD) in NAND Flash SI Simulation (opens in a new tab)PaperDOI 10.1109/epeps.2017.8329702IEEE EPEPS
    19nm 112.8mm2 64Gb Multi-level Flash Memory with 400Mb/s/pin 1.8V Toggle Mode Interface (opens in a new tab)PresentationOn the NAND Die Timeline Flash Memory Summit

    Memory DDR, LPDDR, GDDR and HBM buses

    Current specs 19

    DocumentBodyLatest
    JESD239F: Graphics Double Data Rate 7 (GDDR7) SGRAM Standard (opens in a new tab)Latest revisionOn the Standards page
    1 earlier revision
    1. Graphics Double Data Rate 7 SGRAM Standard (GDDR7), JESD239F (opens in a new tab)
    		JEDEC
    JESD270-4 HBM4 (opens in a new tab)StandardOn the Standards page JEDEC
    DDR5 SDRAM Standard, JESD79-5D (opens in a new tab)StandardOn the Standards page JEDEC
    Low Power Double Data Rate Interface for Non-Volatile Memory (LPDDR4X-NVM) Standard, JESD326-4A (opens in a new tab)StandardJEDEC
    Low Power Double Data Rate 6 (LPDDR6) Standard, JESD209-6 (opens in a new tab)StandardOn the Standards page JEDEC
    Addendum No. 1 to JESD209-4 Low Power Double Data Rate 4X (LPDDR4X), JESD209-4-1B (opens in a new tab)Latest revision
    1 earlier revision
    1. Low Power Double Data Rate 4 (LPDDR4), JESD209-4E (opens in a new tab)
    		JEDEC
    JESD238B.01: High Bandwidth Memory (HBM3) DRAM (opens in a new tab)Latest revisionOn the Standards page
    1 earlier revision
    1. High Bandwidth Memory (HBM3) DRAM, JESD238B.01 (opens in a new tab)
    		JEDEC
    LOW POWER DOUBLE DATA RATE (LPDDR) 5/5X, JESD209-5C (opens in a new tab)Latest revisionOn the Standards page
    1 earlier revision
    1. Low Power Double Data Rate 5 (LPDDR5), JESD209-5 (opens in a new tab)
    		JEDEC
    Graphics Double Data Rate (GDDR6) SGRAM Standard, JESD250D (opens in a new tab)StandardJEDEC
    DDR4 SDRAM Standard, JESD79-4D (opens in a new tab)StandardJEDEC
    High Bandwidth Memory (HBM) DRAM, JESD235D (opens in a new tab)StandardOn the Standards page JEDEC
    Low Power Double Data Rate 3 SDRAM (LPDDR3), JESD209-3C (opens in a new tab)StandardJEDEC
    Wide I/O 2 (WideIO2), JESD229-2 (opens in a new tab)StandardJEDEC
    Low Power Double Data Rate 2 (LPDDR2), JESD209-2F (opens in a new tab)StandardJEDEC
    DDR3 SDRAM Standard, JESD79-3F (opens in a new tab)StandardJEDEC
    Wide I/O Single Data Rate (Wide I/O SDR), JESD229 (opens in a new tab)StandardJEDEC
    POD12, 1.2 V Pseudo Open Drain Interface, JESD8-24 (opens in a new tab)StandardJEDEC
    DDR2 SDRAM Standard, JESD79-2F (opens in a new tab)StandardOn the Standards page JEDEC
    DDR SDRAM Specification, JESD79F (opens in a new tab)StandardJEDEC

    Papers, talks and releases 15

    TitleSourceDate
    New JEDEC SPHBM4 standard (opens in a new tab)StandardOn the Standards page JEDEC
    JEDEC Releases New LPDDR6 Standard to Enhance Mobile and AI Memory Performance (opens in a new tab)StandardOn the Standards page JEDEC
    JEDEC and industry leaders release JESD270-4 HBM4 standard (opens in a new tab)StandardOn the Standards page JEDEC
    JEDEC Updates JESD79-5C (opens in a new tab)StandardOn the Standards page JEDEC
    JEDEC Publishes GDDR7 Graphics Memory Standard (opens in a new tab)StandardOn the Standards page JEDEC
    JEDEC Publishes HBM3 Update to High Bandwidth Memory (HBM) Standard (opens in a new tab)StandardOn the Standards page JEDEC
    JEDEC Publishes Update to DDR5 SDRAM Standard (opens in a new tab)StandardOn the Standards page JEDEC
    JEDEC Publishes New and Updated Standards for Low Power Memory Devices Used in 5G and AI Applications (opens in a new tab)StandardJEDEC
    JEDEC Publishes New DDR5 Standard (opens in a new tab)StandardOn the Standards page JEDEC
    JEDEC Updates Standard for Low Power Memory Devices: LPDDR5 (opens in a new tab)StandardOn the Standards page JEDEC
    JEDEC Updates Groundbreaking High Bandwidth Memory (HBM) Standard (JESD235B) (opens in a new tab)StandardOn the Standards page JEDEC
    JEDEC Updates Groundbreaking High Bandwidth Memory (HBM) Standard (JESD235A) (opens in a new tab)StandardOn the Standards page JEDEC
    Skinner (Micron) 2013 LPDDR4 architectural approach, JEDEC Mobile Forum (opens in a new tab)StandardJEDEC
    JEDEC Announces Publication of DDR4 Standard (opens in a new tab)StandardOn the Standards page JEDEC
    Publication of JEDEC DDR3 SDRAM Standard (opens in a new tab)StandardOn the Standards page JEDEC

    Zone 04

    Form factors and platforms81 current specs · 5 papers and talks

    Storage: M.2, U.2, EDSFF and data center SSD specs. Memory: DIMM, CAMM2, SOCAMM2, SPD and PMIC.

    Storage M.2, U.2, EDSFF and data center SSD specs

    Current specs 42

    DocumentBodyLatest
    SFF-TA-1039 Specification for PCI Express Active Module/Cable Supplemental Specifications, Revision 1.0 (opens in a new tab)StandardSNIA
    SFF-TA-1008 Specification for Enterprise and Datacenter Standard Form Factor (E3), Revision 3.0a (opens in a new tab)StandardSNIA
    SFF-TA-1041 Specification for Low Profile PCIe Gen 7 Connector System, Revision 1.0 (opens in a new tab)StandardSNIA
    SFF-TA-1044 Specification for Hybrid Orthogonal EDSFF Connector System, Revision 1.0 (opens in a new tab)StandardSNIA
    SFF-TA-1045 Specification for Pin and Signal Definition for the Hybrid Orthogonal EDSFF Connector Specification, Revision 1.0 (opens in a new tab)StandardSNIA
    SFF-9400 Specification for Universal 4/8X Pinouts, Revision 1.1 (opens in a new tab)StandardSNIA
    SFF-TA-1005 Specification for Universal Backplane Management (UBM), Revision 1.5 (opens in a new tab)StandardSNIA
    Datacenter NVMe SSD Specification, Version 2.7 (opens in a new tab)Latest revision
    2 earlier revisions
    1. Datacenter NVMe SSD Specification, Version 2.6 (opens in a new tab)
    2. Datacenter NVMe SSD Specification, Version 2.5 (opens in a new tab)
    		Open Compute Project
    SFF-TA-1006 Specification for Enterprise and Datacenter 1U Short Device Form Factor (E1.S), Rev 2.0 (opens in a new tab)StandardSNIA
    SFF-TA-1036 Specification for Cable Optimized Boot Peripheral Connector for OCP M-PIC, Revision 1.0 (opens in a new tab)StandardSNIA
    SFF-TA-1007 Specification for Enterprise and Datacenter 1U Long Device Form Factor (E1.L), Revision 1.3 (opens in a new tab)StandardSNIA
    SFF-TA-1026 Specification for Storage System High Speed Cable Interconnect, Revision 2.0a (opens in a new tab)StandardSNIA
    SFF-TA-1042 Specification for Enterprise and Datacenter Device Form Factor (E2), Revision 1.0 (opens in a new tab)StandardSNIA
    SFF-TA-1002 Specification for Protocol Agnostic Multi-Lane High Speed Connector, Rev 1.6a (opens in a new tab)StandardSNIA
    SFF-TA-1009 Rev 4.1a: Enterprise and Datacenter Standard Form Factor Pin and Signal Specification (opens in a new tab)StandardSNIA
    SFF-9639 Specification for Multifunction 6X Unshielded Connector Pinouts, Revision 2.2 (opens in a new tab)StandardSNIA
    PCI Express Card Electromechanical Specification Revision 6.0.1 (opens in a new tab)Latest revision
    7 earlier revisions
    1. PCI Express Card Electromechanical Specification Revision 6.0 (opens in a new tab)
    2. PCI Express Card Electromechanical Specification Revision 5.1, Version 1.0 (opens in a new tab)
    3. PCI Express Card Electromechanical Specification Revision 5.0 (opens in a new tab)
    4. PCI Express Card Electromechanical Specification Revision 4.0, Version 1.0 (opens in a new tab)
    5. PCI Express Card Electromechanical Specification Revision 3.0 (opens in a new tab)
    6. PCI Express Card Electromechanical Specification Revision 2.0 (opens in a new tab)
    7. PCI Express Card Electromechanical Specification Revision 1.1 (opens in a new tab)
    		PCI-SIG
    SFF-TA-1016 Specification for Internal Unshielded High Speed Connector System, Revision 1.3 (opens in a new tab)StandardSNIA
    Catalina: PCIe Gen5 EDSFF NVMe SSD Reference Designs, Version 1.0.1 (opens in a new tab)StandardOpen Compute Project
    SFF-TA-1034 Specification for Pluggable Multipurpose Module (PMM), Revision 1.0a (opens in a new tab)StandardSNIA
    PCI Express M.2 Specification, Revision 5.1 (opens in a new tab)Latest revision
    7 earlier revisions
    1. PCI Express M.2 Specification Revision 4.2 (opens in a new tab)
    2. PCI Express M.2 Specification Revision 5.0, Version 1.0 (opens in a new tab)
    3. PCI Express M.2 Specification Revision 4.0, Version 1.1 (opens in a new tab)
    4. PCI Express M.2 Specification Revision 4.0, Version 1.0 (opens in a new tab)
    5. PCI Express M.2 Specification Revision 3.0, Version 1.2 (opens in a new tab)
    6. PCI Express M.2 Specification Revision 1.1 (opens in a new tab)
    7. PCI Express M.2 Specification Revision 1.0 (opens in a new tab)
    		PCI-SIG
    SFF-8639 Specification for Multifunction 6X Unshielded Connector, Rev 2.2 (opens in a new tab)StandardSNIA
    SD Specifications Part 1 Physical Layer Simplified Specification, Version 9.10 (opens in a new tab)StandardSD Association
    SFF-TA-1020 Specification for Cables and Connector Variants Based on SFF-TA-1002, Revision 1.1 (opens in a new tab)StandardSNIA
    Enclosure Form Factor for SSD Devices, Version 1.0, JESD253.01 (opens in a new tab)StandardJEDEC
    M.2 Accelerator Module Hardware Specification, V1.0 (opens in a new tab)StandardOpen Compute Project
    NVMe Cloud SSD Specification, Version 1.0a (opens in a new tab)Latest revision
    1 earlier revision
    1. NVMe Cloud SSD Specification, Version 1.0 (opens in a new tab)
    		Open Compute Project
    SFF-TA-1021 Specification for PCIe Enclosure Compatible Form Factor Specification (PECFF), Revision 1.0 (opens in a new tab)StandardSNIA
    SFF-8611 Specification for MiniLink 4/8X I/O Cable Assemblies, Revision 1.0 (opens in a new tab)StandardSNIA
    SFF-8631 Specification for Serial Attachment X8/X16 Unshielded Device Connector, Revision 1.4 (opens in a new tab)StandardSNIA
    SFF-TA-1001 Specification for Universal x4 Link Definition for SFF-8639, Revision 1.1 (opens in a new tab)StandardSNIA
    SFF-8654 Specification for 0.6mm 4/8X Unshielded I/O Connector, Revision 1.2 (opens in a new tab)StandardSNIA
    SFF-8201 Specification for 2.5" Form Factor Drive Dimensions, Revision 3.4 (opens in a new tab)StandardSNIA
    SFF-8301 Specification for 3.5" Form Factor Drive Dimensions, Revision 1.9 (opens in a new tab)StandardSNIA
    SFF-8609 Specification for Management Interface for Drive Conditions, Revision 1.0 (opens in a new tab)StandardSNIA
    SFF-8630 Specification for Serial Attachment 4X Unshielded Connector, Revision 1.5 (opens in a new tab)StandardSNIA
    SFF-8200 Specification for Suite of 2.5" Form Factor Drives, Revision 3.3 (opens in a new tab)StandardSNIA
    SFF-8643 Rev 3.5, Mini Multilane 4/8X 12 Gb/s Unshielded Connector (HD12un) (opens in a new tab)StandardSNIA
    Facebook / Microsoft M.2 Carrier Card Design Specification, Version 1.0 (opens in a new tab)StandardOpen Compute Project
    PCI Express 225 W/300 W High Power Card Electromechanical Specification Revision 1.0 (opens in a new tab)StandardPCI-SIG
    Embedded MultiMediaCard (e.MMC) Mechanical Standard, JESD84-C43 (opens in a new tab)StandardJEDEC

    Papers, talks and releases 3

    TitleSourceDate
    Liquid Cooling Approaches for E1.S SSDs (opens in a new tab)PresentationKIOXIA argues air cooling throttles E1.S drives under sustained AI loads and shows a cold-plate direct liquid cooling design for its NX1 drives, built to SNIA SFF-TA-1006 Rev. 2.0.OCP Global Summit
    SNIA SFF Spec Updates to the Storage Form Factor (opens in a new tab)PresentationMicron, as co-chair of the SNIA form factor group, covers the year of SSD form factor changes: liquid-cooled E1.S, streaming boot, PCIe 7.0 throughput and I3C problems.OCP Global Summit
    E2: The SSD Form Factor for the Petabyte SSD Era (opens in a new tab)PresentationExplains why the SNIA E2 form factor, which fits more NAND packages than other drives, is the route to a 1PB SSD, and what it costs in capacity per system and cooling.SDC

    Memory DIMM, CAMM2, SOCAMM2, SPD and PMIC

    Current specs 39

    DocumentBodyLatest
    Standard Manufacturer's Identification Code, JEP106BP (opens in a new tab)StandardJEDEC
    DDR5MRCD02 Multiplexed Rank Registering Clock Driver, JESD82-542 (opens in a new tab)StandardJEDEC
    DDR5MRCD03 Multiplexed Rank Registering Clock Driver, JESD82-543 (opens in a new tab)StandardOn the Standards page JEDEC
    DDR5MDB03 Multiplexed Rank Data Buffer, JESD82-553 (opens in a new tab)StandardJEDEC
    JC-42.6 Manufacturer Identification (ID) Code for Low Power Memories, JEP166G (opens in a new tab)StandardJEDEC
    LPDDR5/5X Small Outline Compression Attached Memory Module (SOCAMM2) Common Standard, JESD328 (opens in a new tab)StandardOn the Standards page JEDEC
    CMM02 Memory Module for Compute Express Link (CXL), JESD317-2 (opens in a new tab)StandardJEDEC
    LPDDR5/5X Compression Attached Memory Module (CAMM2) Raw Card E Annex, JESD318-F0-RCE (opens in a new tab)StandardOn the Standards page JEDEC
    DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard, JESD305B.01 (opens in a new tab)StandardJEDEC
    LPDDR5/5X Serial Presence Detect (SPD) Contents, JESD406-5D (opens in a new tab)StandardOn the Standards page JEDEC
    DDR5RCD05 Registering Clock Driver, JESD82-515.01 (opens in a new tab)StandardJEDEC
    DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM and CQDIMM) Common Standard, JESD323B (opens in a new tab)StandardJEDEC
    DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Standard, JESD324B (opens in a new tab)StandardJEDEC
    DDR5MDB02 Multiplexed Rank Data Buffer, JESD82-552 (opens in a new tab)StandardOn the Standards page JEDEC
    PMIC5030 Power Management IC Standard, JESD301-5 (opens in a new tab)StandardOn the Standards page JEDEC
    DDR5 Serial Presence Detect (SPD) Contents, JESD400-5D.01 (opens in a new tab)StandardJEDEC
    DDR5CKD01 Clock Driver, JESD82-531B.02 (opens in a new tab)StandardJEDEC
    Compression Attached Memory Module (CAMM2) Common Standard, JESD318B (opens in a new tab)StandardJEDEC
    PMIC5200 Power Management IC Standard, JESD301-3 (opens in a new tab)StandardJEDEC
    PMIC5020 Power Management IC Standard, JESD301-4A (opens in a new tab)StandardJEDEC
    PMIC5000/PMIC5010 Power Management IC Standard, JESD301-1A.03 (opens in a new tab)StandardJEDEC
    PMIC5120 Power Management IC Standard, JESD301-6 (opens in a new tab)StandardJEDEC
    DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard, JESD308B (opens in a new tab)StandardJEDEC
    DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard, JESD309A (opens in a new tab)StandardJEDEC
    DDR5 Registering Clock Driver Definition (DDR5RCD04), JESD82-514.01 (opens in a new tab)StandardJEDEC
    JEDEC Memory Module Reference Base Standard for Compute Express Link (CXL), JESD317A (opens in a new tab)StandardJEDEC
    TS511X, TS521X Serial Bus Thermal Sensor Device Standard, JESD302-1A (opens in a new tab)StandardJEDEC
    SPD5118 Hub and Serial Presence Detect Device Standard, JESD300-5B.01 (opens in a new tab)StandardJEDEC
    DDR4 NVDIMM-N Design Standard, JESD248A.01 (opens in a new tab)StandardJEDEC
    DDR5 Registering Clock Driver Definition (DDR5RCD02), JESD82-512 (opens in a new tab)StandardJEDEC
    DDR5 Registering Clock Driver Definition (DDR5RCD03), JESD82-513 (opens in a new tab)StandardJEDEC
    DDR4 Registering Clock Driver (DDR4RCD02), JESD82-31A.01 (opens in a new tab)StandardJEDEC
    PMIC5100 Power Management IC Standard, JESD301-2 Rev. 1.03 (opens in a new tab)StandardJEDEC
    Byte Addressable Energy Backed Interface, JESD245E (opens in a new tab)StandardJEDEC
    Backup Energy Module Standard for NVDIMM Memory Devices (BEM), JESD315 (opens in a new tab)StandardJEDEC
    DDR5 Buffer Definition (DDR5DB01), JESD82-521 Rev. 1.1 (opens in a new tab)StandardJEDEC
    DDR5 Registering Clock Driver Definition (DDR5RCD01), JESD82-511 (opens in a new tab)StandardJEDEC
    Configurations for Solid State Memories, JESD21-C (opens in a new tab)StandardJEDEC

    Papers, talks and releases 2

    TitleSourceDate
    JEDEC Releases Updated LPDDR5/5X SPD Standard with Enhanced Mode Switching Support (opens in a new tab)StandardOn the Standards page JEDEC
    JEDEC Publishes New CAMM2 Memory Module Standard (opens in a new tab)StandardJEDEC

    Zone 05

    Controllers, firmware and ECC1 current spec · 28 controller notes · 76 papers and talks

    Storage: SSD controllers, FTL, garbage collection and ECC. Memory: Memory controllers, refresh and on-die ECC.

    Storage SSD controllers, FTL, garbage collection and ECC

    Current specs 1

    DocumentBodyLatest
    Zoned Storage Models, Version 1.0 (opens in a new tab)StandardSNIA

    Controller and drive notes 28

    NoteSourceDate
    Powering the Next Generation of PCIe Gen6 NVMe SSDs with the Marvell Bravera SC6 SSD Controller (opens in a new tab)ControllerOn the Controller Timeline Marvell
    Silicon Motion SM2524XT PCIe Gen5 DRAM-less SSD controller (FMS 2026 showcase) (opens in a new tab)ControllerDRAM-less Gen5 at up to 14.5GB/s read and 2.8M IOPS. That matches the SM2508's 14.5GB/s sequential read in the same release.Silicon Motion press release
    Silicon Motion SM8466 PCIe Gen6 enterprise SSD controller (FMS 2026 showcase) (opens in a new tab)ControllerSMI's Gen6 enterprise controller: up to 28GB/s sequential and 7M random IOPS, with drive capacities past 512TB.Silicon Motion press release
    Phison previews X3 PCIe Gen6 SSD controller and E37T PCIe Gen5 DRAM-less SSD (COMPUTEX 2026) (opens in a new tab)ControllerPreview only for X3, no specs given. E37T is DRAM-less Gen5 at up to 14.9GB/s and 8TB, aimed at the mainstream.Phison press release
    CES 2026: Phison Showcases Gen5 Storage to Redefine User Experiences (opens in a new tab)ControllerOn the Controller Timeline Phison
    Joint innovation for the AI storage industry (in Chinese) (opens in a new tab)ControllerOn the Controller Timeline Maxio
    Micron 9650 SSD, first PCIe Gen6 data center SSD (launch with 6600 ION and 7600) (opens in a new tab)ControllerFirst PCIe Gen6 data center SSD per Micron, built on its G9 NAND, quoted at up to 5.5 million random read IOPS.Micron press release
    Phison E28 PCIe 5.0 SSD controller (COMPUTEX 2025) (opens in a new tab)ControllerPhison's TSMC 6nm Gen5 flagship, up to 2,600K/3,000K random read/write IOPS, with on-controller SI processing.Phison press release
    Phison E31T DRAM-less PCIe 5.0 SSD controller (COMPUTEX 2025) (opens in a new tab)ControllerDRAM-less Gen5 for M.2 2230 and 2242, aimed at thin laptops and handhelds. Gen5 reaches the small form factors.Phison press release
    Silicon Motion SM2504XT PCIe Gen5 4-channel DRAM-less SSD controller (opens in a new tab)ControllerTSMC 6nm, 4 channels at 3600MT/s, up to 11.5GB/s read with total SSD power under 5W. The mainstream Gen5 tier.On the Controller Timeline Silicon Motion product page (introduced at COMPUTEX 2025)
    Samsung 9100 PRO series SSDs with PCIe 5.0 (in-house 5nm controller) (opens in a new tab)ControllerSamsung's own 5nm controller with V8 TLC: up to 14,800/13,400MB/s and up to 49% better power efficiency than its predecessor.Samsung US newsroom
    Marvell Announces Breakthrough Custom HBM Compute Architecture to Optimize Cloud AI Accelerators (opens in a new tab)ControllerMarvell
    Silicon Motion SM2508 PCIe Gen5 SSD controller (FMS 2024 live demo) (opens in a new tab)ControllerSMI's 6nm Gen5 flagship, demoed at FMS 2024: about half the power of 12nm Gen5 controllers per SMI, at 14.5GB/s read and 2.5M random IOPS.Silicon Motion blog
    Maxio MAP1602 sets the standard for PCIe 4.0 (in Chinese) (opens in a new tab)ControllerOn the Controller Timeline Maxio
    Marvell Introduces Bravera SSD Controllers to Enable the Highest Performing Data Center Flash Storage Solutions (opens in a new tab)ControllerOn the Controller Timeline Marvell
    New Phison E18 Flash Controller for 176-Layer NAND now Commercially Available (opens in a new tab)ControllerOn the Controller Timeline Phison
    Silicon Motion Launches PCIe 4.0 NVMe 1.4 Controller Solutions for Client SSDs (opens in a new tab)ControllerOn the Controller Timeline Silicon Motion
    Phison at the Forefront of PCIe Gen4 Storage Market with a Portfolio of Products (opens in a new tab)ControllerOn the Controller Timeline On the Standards page Phison
    Marvell Unveils Industry's Lowest Power PCIe Gen4 NVMe SSD Controllers (opens in a new tab)ControllerOn the Controller Timeline Marvell
    Phison Announces E12 PCIe SSD controller (opens in a new tab)ControllerOn the Controller Timeline Phison
    Marvell Debuts 88SS1092 Second-Gen NVM Express SSD Controller at OCP Summit (blog) (opens in a new tab)ControllerMarvell
    Phison Unveil at CES 2017 The Next Generation of NAND Flash Controllers (opens in a new tab)ControllerOn the Controller Timeline Phison
    Marvell Expands Its Award-Winning SSD Product Suite by Introducing Advanced BGA SSD Controllers (opens in a new tab)ControllerMarvell
    Phison Announces PS5007-E7, PCIe Gen3x4 SSD controller with NVMe Specification (opens in a new tab)ControllerOn the Controller Timeline Phison
    Phison Announces New Generation Quad-Core PS3110 SATA III SSD Processor (opens in a new tab)ControllerOn the Controller Timeline Phison
    Marvell's Groundbreaking LDPC Technology Enables TLC NAND Flash With New Generation SATA SSD Controller (opens in a new tab)ControllerOn the Controller Timeline Marvell
    Marvell Solidifies Leadership in SSD Market with Introduction of PCIe SSD Controller Supporting SATA Express (opens in a new tab)ControllerOn the Controller Timeline Marvell
    Marvell Unveils Third-Generation SSD 6Gb/s SATA Controller Powered by High Performance Embedded Processor (opens in a new tab)ControllerOn the Controller Timeline Marvell

    Foundational 12

    WorkSourceDate
    Error detecting and error correcting codes (opens in a new tab)PaperDOI 10.1002/j.1538-7305.1950.tb00463.xBell System Technical Journal
    Low-density parity-check codes (opens in a new tab)PaperDOI 10.1109/tit.1962.1057683IRE Transactions on Information Theory
    The design and implementation of a log-structured file system (opens in a new tab)PaperDOI 10.1145/146941.146943ACM Transactions on Computer Systems
    A flash-memory based file system (opens in a new tab)PaperUSENIX Winter
    Good error-correcting codes based on very sparse matrices (opens in a new tab)PaperDOI 10.1109/18.748992IEEE Transactions on Information Theory
    Algorithms and data structures for flash memories (opens in a new tab)PaperDOI 10.1145/1089733.1089735ACM Computing Surveys
    A superblock-based flash translation layer for NAND flash memory (opens in a new tab)PaperDOI 10.1145/1176887.1176911EMSOFT
    Design tradeoffs for SSD performance (opens in a new tab)PaperUSENIX ATC
    DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings (opens in a new tab)PaperDOI 10.1145/1508244.1508271ASPLOS
    Write Amplification Analysis in Flash-Based Solid State Drives (slides) (opens in a new tab)PresentationDOI 10.1145/1534530.1534544SYSTOR
    LightNVM: The Linux Open-Channel SSD Subsystem (opens in a new tab)PaperUSENIX FAST
    ZNS: Avoiding the Block Interface Tax for Flash-based SSDs (opens in a new tab)PaperUSENIX ATC

    Papers, talks and releases 60

    TitleSourceDate
    Dynamic-size Superblock Management based on Buddy System for Modern SSDs (opens in a new tab)PaperDOI 10.1145/3860055ACM Transactions on Architecture and Code Optimization
    VS-Flash: Harnessing Vector Search with Computational Memory-Semantic Flash (opens in a new tab)PreprintarXiv (cs.DB), Samsung Semiconductor
    FDP: The Data Placement Promise of Modern NVMe SSDs (opens in a new tab)PreprintarXiv
    HFLSM: A Hybrid Flattened LSM-Tree for Write-Efficient Key-Value Stores (opens in a new tab)PaperDOI 10.1109/les.2026.3724139IEEE Embedded Systems Letters
    Recent Advancements in OCP Telemetry for SSDs (opens in a new tab)PresentationMicron and Meta show how the OCP Datacenter NVMe SSD spec's telemetry logs let a fleet spot drives drifting from the population before they fail, using the same tools for buyer and maker.OCP Global Summit
    Direct Write QLC: The End of SLC Caching (opens in a new tab)PresentationSandisk's Stephen Gold explains why QLC normally writes each wordline in two program passes behind an SLC cache, and makes the case for writing host data straight to QLC instead.OCP Global Summit
    Increasing Block Sizing Changes Data Placement Economics (opens in a new tab)PresentationSandisk shows NAND erase blocks growing by more than 250% over recent generations, and how that shifts write amplification, SLC cache needs and the cost of small data placement.OCP Global Summit
    FDP: The Data Placement Promise of Modern NVMe SSDs (opens in a new tab)PresentationSamsung tests production NVMe drives with Flexible Data Placement on raw devices and Linux file systems, to see how far placement hints really cut write amplification.SDC
    Introduction to Flexible Data Placement: A New Era of Optimized Data Management (opens in a new tab)StandardSNIA
    DPDA: A Dynamic Partition-Driven Data Allocation Scheme for Boosting Hybrid SSD Performance (opens in a new tab)PaperDOI 10.1109/tc.2026.3742536IEEE Transactions on Computers
    Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs (opens in a new tab)PaperDOI 10.1145/3689031.3696091FDP in Meta's CacheLib with production traces from Meta and Twitter: device write amplification near 1. A production-trace case for FDP.EuroSys 2025 (arXiv 2503.11665)
    LVLDPC: Intra-Layer Variation Aware LDPC Coding for 3D TLC NAND Flash Memory (opens in a new tab)PaperDOI 10.1109/ICCD63220.2024.00080RBER varies by layer, so pick LDPC strength by layer instead of one high-rate code for all, to cut read retries.ICCD
    In-place Switch: Reprogramming based SLC Cache Design for Hybrid 3D SSDs (opens in a new tab)PreprintReprogramming used SLC-mode pages to TLC in place keeps an SLC cache free, aimed at the performance cliff of a full cache and the write amplification that idle-time migration causes.arXiv 2409.14360 (Xiamen University)
    We Ain't Afraid of No File Fragmentation: Causes and Prevalence of Fragmentation in Modern File Systems (opens in a new tab)PaperUSENIX FAST
    Filesystem Fragmentation on Modern Storage Systems (opens in a new tab)PaperDOI 10.1145/3611386ACM
    Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses (opens in a new tab)PreprintDOI 10.1145/3579371.3589071arXiv
    Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses (ISCA 2023, arXiv:2305.07768) (opens in a new tab)PreprintarXiv
    New NVMe Command Sets: Zoned Namespace (ZNS) and Key Value (KV) (opens in a new tab)PresentationOn the Standards page NVM Express
    Embedded Transaction Support Inside SSD With Small-Capacity Non-Volatile Disk Cache (opens in a new tab)PaperDOI 10.1109/tkde.2020.3004518IEEE Transactions on Knowledge and Data Engineering
    3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU, ISSCC 2022 (opens in a new tab)PaperDOI 10.1109/isscc42614.2022.9731565IEEE ISSCC
    Reducing Solid-State Drive Read Latency by Optimizing Read-Retry (ASPLOS 2021, arXiv:2104.09611) (opens in a new tab)PreprintarXiv
    Reducing Solid-State Drive Read Latency by Optimizing Read-Retry (opens in a new tab)PreprintDOI 10.1145/3445814.3446719arXiv
    DEPS: Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD (opens in a new tab)PaperDOI 10.1109/tcad.2020.2994266IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    Boosting the Performance of SSDs via Fully Exploiting the Plane Level Parallelism (opens in a new tab)PaperDOI 10.1109/tpds.2020.2987894IEEE Transactions on Parallel and Distributed Systems
    Probability-Based Address Translationfor Flash SSDs (opens in a new tab)PaperDOI 10.1109/lca.2020.3006529IEEE Computer Architecture Letters
    Quantifying molecular bias in DNA data storage (opens in a new tab)PaperDOI 10.1038/s41467-020-16958-3Nature Communications
    Beyond Address Mapping: A User-Oriented Multiregional Space Management Design for 3-D NAND Flash Memory (opens in a new tab)PaperDOI 10.1109/tcad.2019.2912937IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    ZDC: A Zone Data Compression Method for Solid State Drive Based Flash Memory (opens in a new tab)PaperDOI 10.3390/sym12040623Symmetry
    Multiple Subpage Writing FTL in MLC by Exploiting Dual Mode Operations (opens in a new tab)PaperDOI 10.1109/tcad.2018.2890689IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    Influence of different factors on the RAID 0 paired magnetic disk arrays (opens in a new tab)PaperDOI 10.7251/ijeec1902070dIJEEC - INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTING
    DNA storage: research landscape and future prospects (opens in a new tab)PaperDOI 10.1093/nsr/nwaa007National Science Review
    HMB-SSD: Framework for Efficient Exploiting of the Host Memory Buffer in the NVMe SSD (opens in a new tab)PaperDOI 10.1109/access.2019.2947350IEEE Access
    A Flexible Hybrid BCH Decoder for Modern NAND Flash Memories Using General Purpose Graphical Processing Units (GPGPUs) (opens in a new tab)PaperDOI 10.3390/mi10060365Micromachines
    Why and How to Increase SSD Performance Transparency (opens in a new tab)PaperDOI 10.1145/3317550.3321430Proceedings of the Workshop on Hot Topics in Operating Systems
    Reducing Flash Memory Write Traffic by Exploiting a Few MBs of Capacitor-Powered Write Buffer Inside Solid-State Drives (SSDs) (opens in a new tab)PaperDOI 10.1109/tc.2018.2871683IEEE Transactions on Computers
    Fully Automatic Stream Management for Multi-Streamed SSDs Using Program Contexts (opens in a new tab)PaperUSENIX FAST
    FlashShare: Punching Through Server Storage Stack from Kernel to Firmware for Ultra-Low Latency SSDs (OSDI '18) (opens in a new tab)Paperusenix.org
    Improving I/O Performance of Large-Page Flash Storage Systems Using Subpage-Parallel Reads (opens in a new tab)PaperDOI 10.1109/nvmsa.2018.000172018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium (NVMSA)
    FastGC (opens in a new tab)PaperDOI 10.1145/3195970.3196051Proceedings of the 55th Annual Design Automation Conference
    MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices (FAST '18) (opens in a new tab)Paperusenix.org
    A Flash Memory Controller for 15μs Ultra-Low-Latency SSD Using High-Speed 3D NAND Flash with 3μs Read Time (opens in a new tab)PaperDOI 10.1109/isscc.2018.8310322ISSCC 2018 (paper 20.2)
    Tiny-Tail Flash (opens in a new tab)PaperDOI 10.1145/3121133ACM Transactions on Storage
    A workload-aware flash translation layer enhancing performance and lifespan of TLC/SLC dual-mode flash memory in embedded systems (opens in a new tab)PaperDOI 10.1016/j.micpro.2016.12.009Microprocessors and Microsystems
    Improving File System Performance of Mobile Storage Systems Using a Decoupled Defragmenter (janusd) (opens in a new tab)PaperUSENIX ATC
    In-Place Appends for Real: DBMS Overwrites on Flash without Erase (opens in a new tab)PaperDOI 10.5441/002/edbt.2017.76Appending small database updates to the same flash page without an erase cut page invalidations by 67% and garbage collection overhead by 80% in the authors’ Shore-MT tests on real flash.EDBT
    Practical Implication of Analytical Models for SSD Write Amplification (opens in a new tab)PaperDOI 10.1145/3030207.3030219Four analytical write amplification models checked against a real SSD; the models assume uniform random writes on a full drive and so miss what general workloads do.ACM/SPEC ICPE
    Performance Evaluation of Dynamic Page Allocation Strategies in SSDs (opens in a new tab)PaperDOI 10.1145/2829974ACM Transactions on Modeling and Performance Evaluation of Computing Systems
    Exploiting Page Correlations for Write Buffering in Page-Mapping Multichannel SSDs (opens in a new tab)PaperDOI 10.1145/2815622ACM Transactions on Embedded Computing Systems
    TLC-FTL: Workload-Aware Flash Translation Layer for TLC/SLC Dual-Mode Flash Memory in Embedded Systems (opens in a new tab)PaperDOI 10.1109/hpcc-css-icess.2015.2632015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspac
    Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications (opens in a new tab)PaperDOI 10.4218/etrij.14.0213.0537ETRI Journal
    SRFTL: An Adaptive Superblock-Based Real-Time Flash Translation Layer for NAND Flash Memory (opens in a new tab)PaperDOI 10.1109/HPCC.2014.572014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 1
    EC-Cache (opens in a new tab)PaperDOI 10.1145/2593069.2593130Proceedings of the 51st Annual Design Automation Conference
    Data pattern aware FTL for SLC+MLC hybrid SSD (opens in a new tab)PaperDOI 10.1007/s10617-014-9138-5Design Automation for Embedded Systems
    The Multi-streamed Solid-State Drive (opens in a new tab)PaperUSENIX HotStorage
    DLOOP: A Flash Translation Layer Exploiting Plane-Level Parallelism (opens in a new tab)PaperDOI 10.1109/ipdps.2013.582013 IEEE 27th International Symposium on Parallel and Distributed Processing
    Understanding the Robustness of SSDs under Power Fault (opens in a new tab)PaperPower faults injected into fifteen commodity SSDs from five vendors made thirteen of them misbehave, with bit corruption, shorn writes, metadata corruption and total device failure.USENIX FAST ’13
    Transparent Online Storage Compression at the Block-Level (opens in a new tab)PaperDOI 10.1145/2180905.2180906ACM Transactions on Storage
    A comprehensive study of energy efficiency and performance of flash-based SSD (opens in a new tab)PaperDOI 10.1016/j.sysarc.2011.01.005Journal of Systems Architecture
    Using Transparent Compression to Improve SSD-based I/O Caches (opens in a new tab)PaperDOI 10.1145/1755913.1755915EuroSys
    Exploiting Internal Parallelism of Flash-based SSDs (opens in a new tab)PaperDOI 10.1109/l-ca.2010.3IEEE Computer Architecture Letters

    Memory Memory controllers, refresh and on-die ECC

    Foundational 2

    WorkSourceDate
    Memory access scheduling (opens in a new tab)PaperDOI 10.1145/339647.339668ISCA
    RAIDR: Retention-aware intelligent DRAM refresh (opens in a new tab)PaperDOI 10.1109/isca.2012.6237001ISCA

    Papers, talks and releases 2

    TitleSourceDate
    MORDOR: Mitigating Overheads of Read Disturbance Preventive Operations via Elastic Refresh Scheduling (opens in a new tab)PreprintarXiv
    Verified DRAM Address Mapping Reverse Engineering with Threshold Sweep (opens in a new tab)PreprintarXiv

    Zone 06

    Reliability and test16 current specs · 68 papers and talks

    Storage: Retention, disturb, endurance and field studies. Memory: Qualification stress tests and DRAM field errors.

    Storage Retention, disturb, endurance and field studies

    Current specs 6

    DocumentBodyLatest
    JESD219A.01 Solid-State Drive (SSD) Endurance Workloads (Revision of JESD219A, July 2012) (opens in a new tab)Latest revision
    1 earlier revision
    1. JESD219A Client Test Trace, 64 GB to 128 GB SSD (trace + readme) (opens in a new tab)
    		JEDEC
    Solid State Storage (SSS) Performance Test Specification (PTS), Version 2.0.2 (opens in a new tab)StandardSNIA
    JESD22-A117E Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Stress Test (reaffirmed October 2024) (opens in a new tab)StandardJEDEC
    Solid-State Drive (SSD) Requirements and Endurance Test Method, JESD218B (opens in a new tab)StandardJEDEC
    Solid State Storage (SSS) Performance Test Specification (PTS) Client, Version 1.2 (opens in a new tab)StandardSNIA
    Solid State Storage (SSS) Performance Test Specification (PTS) Enterprise, Version 1.1 (opens in a new tab)StandardSNIA

    Foundational 6

    WorkSourceDate
    Bit error rate in NAND flash memories (opens in a new tab)PaperDOI 10.1109/relphy.2008.4558857IRPS
    Characterizing flash memory: anomalies, observations, and applications (opens in a new tab)PaperDOI 10.1145/1669112.1669118MICRO
    Error patterns in MLC NAND flash memory: measurement, characterization, and analysis (opens in a new tab)PaperDOI 10.1109/date.2012.6176524DATE
    A Large-Scale Study of Flash Memory Failures in the Field (opens in a new tab)PaperDOI 10.1145/2745844.2745848Proceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems
    Flash Reliability in Production: The Expected and the Unexpected (opens in a new tab)PaperSix years of Google data center SSDs show raw bit error rates growing far slower with wear than assumed and not predicting uncorrectable errors, and SLC drives no more reliable than MLC.USENIX FAST ’16
    Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives (opens in a new tab)PaperA long survey from Carnegie Mellon, Seagate and ETH Zürich of where NAND flash errors come from and how SSD controllers mitigate them and recover the data.Proceedings of the IEEE, September

    Papers, talks and releases 57

    TitleSourceDate
    RLFC: An adaptive RL-driven framework for efficient flow control in SSD-SMR hybrid storage with improved latency and endurance (opens in a new tab)PaperDOI 10.1007/s10586-026-06639-zCluster Computing
    Reliable HCI-Based Programming in V-NAND Flash Memory: Co-optimization of SWL Waveform and Trap-Cut Architecture (opens in a new tab)PaperDOI 10.1088/1361-6641/aeb1e8Semiconductor Science and Technology (accepted manuscript)
    Thermal-Aware Write Management on 3-D NAND Flash Solid-State Drives (opens in a new tab)PaperDOI 10.1109/les.2026.3727142IEEE Embedded Systems Letters
    Memory as a Wasting Asset: Pricing Flash Endurance for Embodied Agents, and the Limits of Doing So (opens in a new tab)PreprintDOI 10.48550/arxiv.2606.18144arXiv
    Experimental Study on System-Level Performance Impact of Read Disturbance in Modern SSDs (opens in a new tab)PaperDOI 10.1145/378809215 NVMe SSDs from 10 vendors. Read disturb shows up as real I/O slowdowns, and one process can degrade its neighbors with reads alone.ACM POMACS / SIGMETRICS
    A 0.87pJ/b 17Gb/s/pin Parallel Receiver with a Local DQS Recovery for a Supply-Noise-Tolerant DQS Distribution in High-Performance NAND Flash Interfaces (opens in a new tab)PaperDOI 10.1109/ISSCC49663.2026.11409032Interface test chip, not a die: a 40nm receiver running 17Gb/s per pin for NAND buses, cutting clocking power 70%. Points to where NAND bus speeds go next.ISSCC 2026, POSTECH and Samsung Electronics
    Total Ionizing Dose Impacts on Read Disturb in 3D NAND Flash Memory (opens in a new tab)PaperDOI 10.1109/tns.2026.3744362IEEE Transactions on Nuclear Science
    STAR: Improving Lifetime and Performance of High-Capacity Modern SSDs Using State-Aware Randomizer (opens in a new tab)PaperDOI 10.1109/ICCAD66269.2025.11240772A randomizer that removes the data patterns behind lateral charge spreading. Built on data from 160 real 3D NAND chips, up to 2.3x SSD lifetime.ICCAD
    Material engineering to enhance reliability in 3D NAND flash memory (opens in a new tab)PaperDOI 10.1016/j.device.2024.100682Device (Cell Press)
    STRAW: A Stress-Aware WL-Based Read Reclaim Technique for High-Density NAND Flash-Based SSDs (opens in a new tab)PaperDOI 10.1109/LCA.2024.3516205Read disturb hits word lines unevenly, so reclaim per word line instead of per block. Read-reclaim page writes drop 83.6%.IEEE Computer Architecture Letters, 2025 (arXiv 2501.02517)
    Retention Accelerated Testing for 3-D QLC NAND Flash Memory: Characterization, Analysis, and Modeling (opens in a new tab)PaperDOI 10.1109/TCAD.2025.3526055Finds the standard Arrhenius model inaccurate for charge trap 3D QLC retention and proposes a new model. Matters for anyone baking QLC to predict lifespan.IEEE TCAD
    Origin of the Temperature Dependence of Gate-Induced Drain Leakage-Assisted Erase in Three-Dimensional nand Flash Memories (opens in a new tab)PaperDOI 10.3390/mi15121516Micromachines
    Discrete-Trap Effects on 3-D NAND Variability, Part I: Threshold Voltage (opens in a new tab)PaperDOI 10.1109/jeds.2024.3447149IEEE Journal of the Electron Devices Society
    AERO: Adaptive Erase Operation for Improving Lifetime and Performance of Modern NAND Flash-Based SSDs (opens in a new tab)PaperDOI 10.1145/3620666.3651341ASPLOS
    Comparing the Reliability of Solid-State Drives Based on TLC and QLC NAND Flash Memories (Invited) (opens in a new tab)PaperDOI 10.1109/IRPS48228.2024.10529487Qualification and field data on enterprise QLC versus TLC SSDs. The authors call it the first published QLC enterprise field data, and it finds similar reliability.IEEE IRPS
    Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate (opens in a new tab)PreprintarXiv
    Operation Scheme Optimizations to Achieve Ultra-high Endurance (1e10) in Flash Memory (opens in a new tab)PreprintarXiv
    Analysis of High-Temperature Data Retention in 3D Floating-Gate NAND Flash Memory Arrays (opens in a new tab)PaperDOI 10.1109/jeds.2023.3320722IEEE Journal of the Electron Devices Society
    New Total-Ionizing-Dose Resistant Data Storing Technique for NAND Flash Memory (opens in a new tab)PaperDOI 10.1109/tdmr.2022.3189673IEEE Transactions on Device and Materials Reliability
    Impact of Residual Stress on a Polysilicon Channel in Scaled 3D NAND Flash Memory (opens in a new tab)PaperDOI 10.3390/electronics10212632Electronics
    iTRIM: I/O-Aware TRIM for Improving User Experience on Mobile Devices (opens in a new tab)PaperDOI 10.1109/tcad.2020.3027656IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    Endurance of NVMe, SAS, and SATA SSDs (opens in a new tab)White paperSNIA explains how SSD endurance is rated and measured, the math behind it, overprovisioning, and why client and data center drives are rated differently.SNIA Solid State Drive Special Interest Group white paper
    Machine learning model for predicting threshold voltage by taper angle variation and word line position in 3D NAND flash memory (IEICE ELEX 17(22)) (opens in a new tab)PaperDOI 10.1587/elex.17.20200345IEICE Electronics Express
    Research on 3D TLC NAND flash reliability from the perspective of threshold voltage distribution (opens in a new tab)PaperDOI 10.1016/j.microrel.2020.113738Microelectronics Reliability
    Layer-Dependent Bit Error Variation in 3-D NAND Flash Under Ionizing Radiation (opens in a new tab)PaperDOI 10.1109/tns.2020.3014261IEEE Transactions on Nuclear Science
    Integration of fluorographene trapping medium in MoS2-based nonvolatile memory device (opens in a new tab)PaperDOI 10.1063/1.5126793Journal of Applied Physics
    Approximate 3D-TLC NAND Flash Write with Initial Error Injection for Application-level Reliability Improvement of Machine Learning-based Computing (opens in a new tab)PaperDOI 10.1109/snw50361.2020.9131417IEEE Silicon Nanoelectronics Workshop (SNW)
    A Novel Confined Nitride-Trapping Layer Device for 3-D NAND Flash With Robust Retention Performances (opens in a new tab)PaperDOI 10.1109/ted.2020.2968805IEEE Transactions on Electron Devices
    Novel Quad-Interface MTJ Technology and its First Demonstration With High Thermal Stability Fact (opens in a new tab)PaperDOI 10.1109/ted.2020.2966731IEEE Transactions on Electron Devices
    Impact of Cycling Induced Intercell Trapped Charge on Retention Charge Loss in 3-D NAND Flash Memory (opens in a new tab)PaperDOI 10.1109/jeds.2019.2963473IEEE Journal of the Electron Devices Society
    Measurement and Analysis of SSD Reliability Data Based on Accelerated Endurance Test (opens in a new tab)PaperDOI 10.3390/electronics8111357Electronics
    VaLLR: Threshold Voltage Distribution Aware LLR Optimization to Improve LDPC Decoding Performance for 3D TLC NAND Flash (opens in a new tab)PaperDOI 10.1109/iccd46524.2019.000962019 IEEE 37th International Conference on Computer Design (ICCD)
    Dynamic Vth Tracking for Cross-Temperature Suppression in 3D-TLC NAND Flash (opens in a new tab)PaperDOI 10.1109/iirw47491.2019.8989886IEEE IIRW
    iLife: Safely Extending Lifetime for Memory-Oriented SSD (opens in a new tab)PaperDOI 10.3390/electronics8060610Electronics
    Modeling of program Vth distribution for 3-D TLC NAND flash memory (opens in a new tab)PaperDOI 10.1007/s11432-018-9490-1Science China Information Sciences
    Subpage-Aware Solid State Drive for Improving Lifetime and Performance (opens in a new tab)PaperDOI 10.1109/tc.2018.2827033IEEE Transactions on Computers
    Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation (opens in a new tab)PreprintarXiv
    Read Disturb Errors in MLC NAND Flash Memory (opens in a new tab)PreprintarXiv
    Utilizing Subpage Programming to Prolong the Lifetime of Embedded NAND Flash-Based Storage (opens in a new tab)PaperDOI 10.1109/tce.2018.2811638IEEE Transactions on Consumer Electronics
    Heavy Ion and Proton-Induced Single Event Upset Characteristics of a 3-D NAND Flash Memory (opens in a new tab)PaperDOI 10.1109/tns.2017.2764852IEEE Transactions on Nuclear Science
    HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness (opens in a new tab)PaperDOI 10.1109/hpca.2018.00050Measurements on real 3D NAND chips of self-recovery, where idle time between program and erase partly repairs the damage each cycle does, and of how temperature changes it.IEEE HPCA
    Cross-Temperature Effects of Program and Read Operations in 2D and 3D NAND Flash Memories (opens in a new tab)PaperDOI 10.1109/iirw.2018.8727102Reading NAND at a different temperature from the one it was programmed at still causes many fail bits in 3D NAND, and the worst case is programming hot and reading cold.IEEE IIRW
    Improving SSD lifetime with byte-addressable metadata (opens in a new tab)PaperDOI 10.1145/3132402.3132420Proceedings of the International Symposium on Memory Systems
    Improving Performance and Lifetime of Large-Page NAND Storages Using Erase-Free Subpage Programming (opens in a new tab)PaperDOI 10.1145/3061639.3062264Proceedings of the 54th Annual Design Automation Conference
    Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices (opens in a new tab)PaperDOI 10.3390/computers6020016Computers
    Power Loss Protection in SSDs (opens in a new tab)White paperSamsung white paper
    Improving performance and lifetime of NAND storage systems using relaxed program sequence (opens in a new tab)PaperDOI 10.1145/2897937.2898032Proceedings of the 53rd Annual Design Automation Conference
    WARM: Improving NAND Flash Memory Lifetime with Write-hotness Aware Retention Management (opens in a new tab)PaperDOI 10.1109/msst.2015.7208284IEEE MSST
    Random telegraph noise-induced sensitivity of data retention to cell position in the programmed distribution of NAND Flash memory arrays (opens in a new tab)PaperDOI 10.1109/led.2015.2428282IEEE Electron Device Letters
    Multi-Channel Architecture-Based FTL for Reliable and High-Performance SSD (opens in a new tab)PaperDOI 10.1109/tc.2013.169IEEE Transactions on Computers
    Revisiting charge trapping/detrapping in Flash memories from a discrete and statistical standpoint - Part II: on-field operation and distributed-cycling effects (opens in a new tab)PaperDOI 10.1109/ted.2014.2327149IEEE Transactions on Electron Devices
    Revisiting charge trapping/detrapping in Flash memories from a discrete and statistical standpoint - Part I: VT instabilities (opens in a new tab)PaperDOI 10.1109/ted.2014.2327661IEEE Transactions on Electron Devices
    Increasing Flash Memory Lifetime by Dynamic Voltage Allocation for Constant Mutual Information (opens in a new tab)PreprintarXiv
    Energy-band engineering for improved charge retention in double floating-gate single-electron memories (opens in a new tab)PreprintarXiv
    Room-Temperature Single-Charging Behavior of Self-Aligned Single-Dot Memory Devices (opens in a new tab)PreprintarXiv
    Understanding the Impact of Power Loss on Flash Memory (opens in a new tab)PaperDOI 10.1145/2024724.2024733Cutting power to raw flash during program and erase shows that a cut during a program can corrupt data an earlier, successful program wrote, and that waiting longer before the cut does not always lower error rates.DAC
    Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design (opens in a new tab)PaperDOI 10.1145/1278480.1278533DAC 2007 (paper 13.1)

    Memory Qualification stress tests and DRAM field errors

    Current specs 10

    DocumentBodyLatest
    Stress Test Driven Qualification of Integrated Circuits, JESD47N (opens in a new tab)StandardJEDEC
    Temperature Cycling, JESD22-A104F.01 (opens in a new tab)StandardJEDEC
    JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs), J-STD-020F (opens in a new tab)StandardJEDEC
    Temperature, Bias, and Operating Life, JESD22-A108G (opens in a new tab)StandardJEDEC
    Method for Developing Acceleration Models for Electronic Device Failure Mechanisms, JESD91B (opens in a new tab)StandardJEDEC
    Measurement and Reporting of Alpha Particle and Terrestrial Cosmic Ray Induced Soft Errors in Semiconductor Devices, JESD89B (opens in a new tab)StandardJEDEC
    High Temperature Storage Life, JESD22-A103E.01 (opens in a new tab)StandardJEDEC
    Highly Accelerated Temperature and Humidity Stress Test (HAST), JESD22-A110E.01 (opens in a new tab)StandardJEDEC
    Failure Mechanisms and Models for Semiconductor Devices, JEP122H (opens in a new tab)StandardJEDEC
    Vibration, Variable Frequency, JESD22-B103B.01 (opens in a new tab)StandardJEDEC

    Foundational 3

    WorkSourceDate
    DRAM errors in the wild: a large-scale field study (opens in a new tab)PaperDOI 10.1145/1555349.1555372SIGMETRICS
    Memory errors in modern systems: the good, the bad, and the ugly (opens in a new tab)PaperDOI 10.1145/2694344.2694348ASPLOS
    Revisiting memory errors in large-scale production data centers: analysis and modeling of new trends from the field (opens in a new tab)PaperDOI 10.1109/dsn.2015.57DSN

    Papers, talks and releases 2

    TitleSourceDate
    CXL in Hyperscale Environment: Fleet-Scale Challenges, Failure Modes, and the Path to Better Debuggability (opens in a new tab)PresentationMeta lists how CXL memory failures show up across a fleet, from event logs and kernel errors to device health counters, and what is missing to debug them.OCP Global Summit
    A 62.5-fJ/b/mm and 23.6-fJ/b/dB Transition-Detection-Based Transceiver Robust to Higher Order ISI and Low-Frequency Supply Noise for On-Chip Global Data Bus and HBM Interfaces (opens in a new tab)PaperDOI 10.1109/tcsi.2026.3743217IEEE Transactions on Circuits and Systems I

    Zone 07

    Security16 current specs · 11 papers and talks

    Storage: Encryption, Opal and sanitize. Memory: RowHammer and memory attacks.

    Memory, newest paper or talk
    An Experimental Analysis of RowHammer in HBM2 DRAM Chips

    Storage Encryption, Opal and sanitize

    Current specs 16

    DocumentBodyLatest
    Security Protocol and Data Model (SPDM) Specification, DSP0274 Version 1.4.1 (opens in a new tab)Latest revision
    4 earlier revisions
    1. Security Protocol and Data Model (SPDM) Specification, DSP0274 Version 1.4.0 (opens in a new tab)
    2. Security Protocol and Data Model (SPDM) Specification, DSP0274 Version 1.3.0 (opens in a new tab)
    3. Security Protocol and Data Model (SPDM) Specification, DSP0274 Version 1.2.0 (opens in a new tab)
    4. Security Protocol and Data Model (SPDM) Specification, DSP0274 Version 1.1.0 (opens in a new tab)
    		DMTF
    TCG Storage Feature Set: Media Encryption Key Multiparty Authorization (MEK-MPA), Version 1.00 (opens in a new tab)StandardTrusted Computing Group
    NIST Special Publication 800-88 Rev. 2, Guidelines for Media Sanitization (opens in a new tab)Latest revision
    1 earlier revision
    1. NIST Special Publication 800-88 Rev. 1, Guidelines for Media Sanitization (opens in a new tab)
    		NIST
    TCG Storage Interface Interactions Specification (SIIS), Version 1.20 (opens in a new tab)StandardTrusted Computing Group
    TCG Storage Security Subsystem Class: Opal, Version 2.30 (opens in a new tab)Latest revision
    1 earlier revision
    1. TCG Storage Security Subsystem Class: Opal, Version 2.02, Revision 1.0 (opens in a new tab)
    		Trusted Computing Group
    TCG Storage Security Subsystem Class (SSC): Key Per I/O, Version 1.00, Revision 1.41 (opens in a new tab)StandardTrusted Computing Group
    FIPS 197 (2023 update), Advanced Encryption Standard (AES) (opens in a new tab)Latest revision
    1 earlier revision
    1. FIPS 197 (original), Advanced Encryption Standard (AES) (opens in a new tab)
    		NIST
    Secure Serial Flash Bus Transactions, JESD254 (opens in a new tab)StandardJEDEC
    IEEE 2883-2022, IEEE Standard for Sanitizing Storage (opens in a new tab)StandardIEEE
    TCG Storage Feature Set: Block SID Authentication, Version 1.01, Revision 1.00 (opens in a new tab)StandardTrusted Computing Group
    TCG Storage Security Subsystem Class: Pyrite Specification, Version 2.01, Revision 1.00 (opens in a new tab)StandardTrusted Computing Group
    TCG Storage Security Subsystem Class: Ruby, Version 1.00, Revision 1.00 (opens in a new tab)StandardTrusted Computing Group
    IEEE 1667-2018, IEEE Standard for Discovery, Authentication, and Authorization in Host Attachments of Storage Devices (opens in a new tab)StandardIEEE
    TCG Storage Architecture Core Specification, Version 2.01, Revision 1.00 (opens in a new tab)StandardTrusted Computing Group
    TCG Storage Security Subsystem Class: Enterprise Specification, Version 1.01, Revision 1.00 (opens in a new tab)StandardTrusted Computing Group
    TCG Storage Security Subsystem Class: Opalite Specification, Version 1.00, Revision 1.00 (opens in a new tab)StandardTrusted Computing Group

    Foundational 3

    WorkSourceDate
    Reliably Erasing Data From Flash-Based Solid State Drives (opens in a new tab)PaperUSENIX FAST '11, UC San Diego
    Vulnerabilities in MLC NAND flash memory programming: experimental analysis, exploits, and mitigation techniques (opens in a new tab)PaperDOI 10.1109/hpca.2017.61HPCA
    Self-encrypting deception: weaknesses in the encryption of solid state drives (opens in a new tab)PaperDOI 10.1109/sp.2019.00088IEEE Symposium on Security and Privacy

    Papers, talks and releases 3

    TitleSourceDate
    Rowhammer Vulnerabilities in 3D NAND Flash: Attack Characterization and Mitigation Strategies (opens in a new tab)PaperDOI 10.1109/IRPS61424.2026.11499193About 1M reads of one word line corrupts adjacent word lines across all sub-blocks, on both floating gate and charge trap TLC parts.IEEE IRPS 2026, Colorado State University
    Evanesco: Architectural Support for Efficient Data Sanitization in Modern Flash-Based Storage Systems (opens in a new tab)PaperDOI 10.1145/3373376.3378490ASPLOS
    Investigation of Data Deletion Vulnerabilities in NAND Flash Memory Based Storage (opens in a new tab)PreprintarXiv

    Memory RowHammer and memory attacks

    Foundational 4

    WorkSourceDate
    Lest we remember: cold boot attacks on encryption keys (opens in a new tab)PaperUSENIX Security
    Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors (opens in a new tab)PaperDOI 10.1109/isca.2014.6853210ISCA
    TRRespass: exploiting the many sides of target row refresh (opens in a new tab)PaperDOI 10.1109/sp40000.2020.00090IEEE Symposium on Security and Privacy
    RowHammer: a retrospective (opens in a new tab)PaperDOI 10.1109/tcad.2019.2915318IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

    Papers, talks and releases 1

    TitleSourceDate
    An Experimental Analysis of RowHammer in HBM2 DRAM Chips (opens in a new tab)PreprintarXiv

    Zone 08

    Next5 current specs · 3 die papers · 157 papers and talks

    Storage: Emerging memory, HBF and computational storage. Memory: Memory for AI, CXL pooling and processing in memory.

    Storage Emerging memory, HBF and computational storage

    Current specs 5

    DocumentBodyLatest
    High Bandwidth Flash (HBF) High-Level Base Die Specification v0.7.0 (opens in a new tab)StandardOpen Compute Project
    NVM Express Computational Programs Command Set Specification, Revision 1.3 (opens in a new tab)StandardNVM Express
    NVM Express Subsystem Local Memory Command Set Specification, Revision 1.3 (opens in a new tab)StandardNVM Express
    Computational Storage API, Version 1.1 (opens in a new tab)StandardSNIA
    Computational Storage Architecture and Programming Model, Version 1.1 (opens in a new tab)Latest revision
    1 earlier revision
    1. Computational Storage Architecture and Programming Model, Version 1.0 (opens in a new tab)
    		SNIA

    Die papers 2

    PaperSourceDate
    Comprehensive Reliability Assessment of 32Gb (Hf,Zr)O 2 -Based Ferroelectric NVDRAM (opens in a new tab)Die paperDOI 10.1109/irps48228.2024.10529336IEEE International Reliability Physics Symposium proceedings
    NVDRAM: A 32Gb Dual Layer 3D Stacked Non-volatile Ferroelectric Memory with Near-DRAM Performance for Demanding AI Workloads (opens in a new tab)Die paperDOI 10.1109/iedm45741.2023.10413848Technical digest - International Electron Devices Meeting

    Foundational 5

    WorkSourceDate
    Storage-class memory: the next storage system technology (opens in a new tab)PaperDOI 10.1147/rd.524.0439IBM Journal of Research and Development
    Phase change memory technology (opens in a new tab)PreprintarXiv
    Ferroelectricity in hafnium oxide thin films (opens in a new tab)PaperDOI 10.1063/1.3634052Applied Physics Letters
    Metal-oxide RRAM (opens in a new tab)PaperDOI 10.1109/jproc.2012.2190369Proceedings of the IEEE
    Biscuit: a framework for near-data processing of big data workloads (opens in a new tab)PaperDOI 10.1109/isca.2016.23ISCA

    Papers, talks and releases 138

    TitleSourceDate
    Gandalf: Flash Shall Not Die! Increasing Flash Storage Lifetime for KV Cache Offloading in LLM Serving (opens in a new tab)PreprintarXiv (cs.LG)
    Technology and Products Leadership for the AI Era (Micron investor webinar, G11 NAND) (opens in a new tab)PresentationMicron's own slides put its next NAND generation, G11, at more than 400 layers with wafer-on-wafer bonding and a volume ramp in the second half of 2027.On the NAND Die Timeline Micron investor webinar, 2026-10-21
    SARP: An On-SSD Index for KVCache with Fast Prefix Matching and Recovery (opens in a new tab)PreprintarXiv (cs.DB)
    HBFSim: A Simulator for Exploring HBF in Memory Hierarchies for LLMs (opens in a new tab)PreprintarXiv (cs.AR)
    MemLLM: End-to-end In-Storage Acceleration of On-device Retrieval-Augmented Generation using Precomputed KV Caches (opens in a new tab)PreprintarXiv (cs.AR), to appear at MICRO
    Charge-Domain In-Memory Computing With NAND-Compatible Ferroelectric Memcapacitor Crossbar (opens in a new tab)PaperDOI 10.1002/smll.76242Small
    CXDVirt: Low Latency Kernel Module Based CXL-SSD Emulation (opens in a new tab)PreprintarXiv
    Multi-bit Ferroelectric-NAND for High-throughput Massive Database Search (opens in a new tab)PreprintarXiv
    RetainZ: Reclaim-Time-Aware Placement for AI Checkpoints on Zoned SSDs (opens in a new tab)PreprintarXiv
    SARIA: Persistence-Aware KV Caching with Coordinated DRAM-SSD Reload for LLM Agents (opens in a new tab)PreprintarXiv
    Near-Line SSD: The Path to the Future (opens in a new tab)PresentationMicron covers where a nearline SSD makes sense, why the E2 form factor suits it, and how failure-in-place can be fitted to the application.OCP Global Summit
    Material Compatibility and Long-Term Hardware Integrity of Enterprise SSDs in Two-Phase Immersion (opens in a new tab)PresentationSamsung describes a long-term reliability test of a high-performance enterprise SSD sitting in two-phase immersion coolant, and what that does to its materials over time.OCP Global Summit
    Storage as a Performance Tier for LLM Serving (opens in a new tab)PresentationSK hynix explains prompt caching of KV states and shows when an SSD tier can cut prefill compute and time to first token for LLM serving.OCP Global Summit
    Characterizing High Bandwidth Flash for LLM Serving (opens in a new tab)PreprintarXiv
    TempoKV: Timely Staging of LLM KV Caches for Memory-Semantic Flash (opens in a new tab)PreprintarXiv
    HBF-Sim: An Extensible HBF Simulator for Large-scale GPU Memory Systems (opens in a new tab)PreprintarXiv
    Bridging LLM Serving and CXL-SSDs with Chunk-Aware KV Cache Management (opens in a new tab)PreprintarXiv
    SPLASH: Co-Designing Sparse Attention with High-Bandwidth Flash for Efficient Long-Context Inference (opens in a new tab)PreprintarXiv
    LTmem: A Hybrid Disaggregated Memory Management Library for Pointer-Intensive Data Structures (opens in a new tab)PaperDOI 10.1109/cluster68337.2026.00054IEEE CLUSTER
    Rethinking Near-Data Processing Execution: Enabling Device Collaboration with CXL Peer-To-Peer Communication (opens in a new tab)PaperDOI 10.1109/cluster68337.2026.00040IEEE CLUSTER
    Beyond GPUs: NVMe SSD Power and Voltage Telemetry for AI Data Centers (opens in a new tab)PresentationShows what the new standardized SSD power and rail-voltage telemetry reveals under AI workloads, including measured drive power that differs sharply from the usual static estimates.SDC
    Evolving Flash Media to Meet the Demands of Evolving AI: Not All SLC Is Equal (opens in a new tab)PresentationArgues that checkpointing, model offload, GNN training and bandwidth-heavy AI jobs each want a differently tuned SLC mode, and lays out the trade-offs a buyer can pick between.SDC
    Less DRAM, Same KV Performance: Persistent KV Caching with CXL-Attached AI SSDs (opens in a new tab)PresentationDescribes sending KV-cache traffic between GPUs and CXL-attached SSDs without staging it in host DRAM, which at four GPUs would otherwise carry roughly 200GB/s.SDC
    Processing-in-Memory Architecture for In-Storage Information Retrieval on 3-D NAND Flash Solid-State Drives (opens in a new tab)PaperDOI 10.1109/tvlsi.2026.3692428IEEE Transactions on Very Large Scale Integration (VLSI) Systems
    Characterizing Vision-Language-Action Models across XPUs: Constraints and Acceleration for On-Robot Deployment (opens in a new tab)PreprintDOI 10.48550/arxiv.2604.24447arXiv
    Read-Reclaim-Induced Endurance Degradation in High-Bandwidth Flash for LLM Inference (opens in a new tab)PaperDOI 10.1109/lca.2026.3742410IEEE Computer Architecture Letters
    SETA: Lifecycle-Aware Session Execution Tiering in Agentic LLM Serving with High-Bandwidth Flash (opens in a new tab)PaperDOI 10.1109/lca.2026.3746209IEEE Computer Architecture Letters
    AI Fabric Specialization for Agentic AI (opens in a new tab)White paperOpen Compute Project, AI HW/SW Co-Design Workgroup
    Vertical NAND in a Ferroelectric-driven Paradigm Shift (opens in a new tab)PreprintarXiv
    Towards a future space-based, highly scalable AI infrastructure system design (opens in a new tab)PreprintDOI 10.48550/arxiv.2511.19468arXiv
    Photonic Fabric Platform for AI Accelerators (opens in a new tab)PreprintDOI 10.48550/arxiv.2507.14000arXiv
    Rapid yet accurate Tile-circuit and device modeling for Analog In-Memory Computing (opens in a new tab)PreprintarXiv
    A Framework for Embedded Non-Volatile Memory Development: Examples from Pb(ZrxTi1-x)O3 Ferroelectric Random Access Memory (opens in a new tab)PaperDOI 10.3390/electronics14040818Electronics (MDPI)
    Ferroelectric NAND for efficient hardware bayesian neural networks (opens in a new tab)PaperDOI 10.1038/s41467-025-61980-yNature Communications
    Dieny 2024 Impact of external magnetic fields on STT-MRAM (arXiv 2409.05584) (opens in a new tab)PreprintarXiv
    Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors (opens in a new tab)PaperDOI 10.1126/sciadv.adn1345Science Advances
    Ferroelectric HfO2-based Capacitors for FeRAM: Reliability from Field Cycling Endurance to Retention (invited) (opens in a new tab)PaperDOI 10.1109/irps48228.2024.10529299IEEE International Reliability Physics Symposium proceedings
    DROID: A Large-Scale In-The-Wild Robot Manipulation Dataset (opens in a new tab)PreprintDOI 10.48550/arxiv.2403.12945arXiv
    Ferroelectric domain nucleation and switching pathways in hafnium oxide (opens in a new tab)PreprintarXiv
    Open X-Embodiment: Robotic Learning Datasets and RT-X Models (opens in a new tab)PreprintDOI 10.48550/arxiv.2310.08864arXiv
    Overcoming the Memory Wall with CXL-Enabled SSDs (USENIX ATC '23) (opens in a new tab)Paperusenix.org
    Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators (opens in a new tab)PreprintarXiv
    Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges (opens in a new tab)PaperDOI 10.1109/jproc.2023.3234607Proceedings of the IEEE
    Investigation of Recovery Phenomena in Hf0.5Zr0.5O2-Based 1T1C FeRAM (opens in a new tab)PaperDOI 10.1109/jeds.2022.3230402IEEE Journal of the Electron Devices Society
    A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference (opens in a new tab)PreprintarXiv
    Krizakova 2022 Spin-orbit torque switching of magnetic tunnel junctions for memory application (arXiv 2207.11974; J. Magn. Magn. Mater. 562, 169692) (opens in a new tab)PreprintarXiv
    Reliability Study of 1T1C FeRAM Arrays With Hf0.5Zr0.5O2 Thickness Scaling (opens in a new tab)PaperDOI 10.1109/jeds.2022.3187101IEEE Journal of the Electron Devices Society
    Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks (opens in a new tab)PaperDOI 10.1002/advs.202105784Advanced Science
    International Roadmap for Devices and Systems 2022 Edition: Beyond CMOS and Emerging Materials Integration (opens in a new tab)PaperIEEE IRDS
    One Nanometer HfO2‐Based Ferroelectric Tunnel Junctions on Silicon (opens in a new tab)PaperDOI 10.1002/aelm.202100499Advanced Electronic Materials
    Preisach modeling of imprint on hafnium zirconium oxide ferroelectric capacitors (opens in a new tab)PaperDOI 10.1063/5.0053185Journal of Applied Physics
    A compute-in-memory chip based on resistive random-access memory (opens in a new tab)PreprintarXiv
    Organic Memory and Memristors: From Mechanisms, Materials to Devices (opens in a new tab)PaperDOI 10.1002/aelm.202100432Advanced Electronic Materials
    ZNS+: Advanced Zoned Namespace Interface for Supporting In-Storage Zone Compaction (opens in a new tab)PaperUSENIX OSDI
    HyR-tree: a spatial index for hybrid flash/3D XPoint storage (opens in a new tab)PaperDOI 10.1007/s00521-021-05804-2Neural Computing and Applications
    A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Pr (opens in a new tab)PaperDOI 10.1109/iedm13553.2020.93721152020 IEEE International Electron Devices Meeting (IEDM)
    A Novel Structure and Operation Scheme of Vertical Channel NAND Flash with Ferroelectric Memory for Multi String Operations (opens in a new tab)PaperDOI 10.3390/electronics10010032Electronics (MDPI)
    Single-shot dynamics of spin-orbit torque and spin transfer torque switching in three-terminal magnetic tunnel junctions (opens in a new tab)PreprintarXiv
    Scalability of Quad Interface p-MTJ for 1X nm STT-MRAM With 10-ns Low Power Write Operation, 10 Yea (opens in a new tab)PaperDOI 10.1109/ted.2020.3025749IEEE Transactions on Electron Devices
    Committee machines: a universal method to deal with non-idealities in memristor-based neural networks (opens in a new tab)PaperDOI 10.1038/s41467-020-18098-0Nature Communications
    Phase-change memories: materials science, technological applications and perspectives (opens in a new tab)PaperDOI 10.1088/1361-6463/aba0e0Journal of Physics D: Applied Physics
    Pathways to efficient neuromorphic computing with non-volatile memory technologies (opens in a new tab)PaperDOI 10.1063/1.5113536Applied Physics Reviews
    Multi-level resistance uniformity of double pinned perpendicular magnetic-tunnel-junction spin-valve depending on top MgO barrier thickness (opens in a new tab)PaperDOI 10.1063/5.0007064AIP Advances
    Benchmarking and Optimization of Spintronic Memory Arrays (opens in a new tab)PaperDOI 10.1109/jxcdc.2020.2999270IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
    SoC Compatible 1T1C FeRAM Memory Array Based on Ferroelectric Hf0.5Zr0.5O2 (opens in a new tab)PaperDOI 10.1109/vlsitechnology18217.2020.9265063IEEE Symposium on VLSI Technology
    Enhancement of data storage capability in a bilayer oxide-based memristor for wearable electronic applications (opens in a new tab)PaperDOI 10.1088/1361-6463/ab81d3Journal of Physics D: Applied Physics
    Memory devices and applications for in-memory computing (opens in a new tab)PaperDOI 10.1038/s41565-020-0655-zNature Nanotechnology 15, 529-544
    Sub-nanosecond memristor based on ferroelectric tunnel junction (opens in a new tab)PaperDOI 10.1038/s41467-020-15249-1Nature Communications
    Fully hardware-implemented memristor convolutional neural network (opens in a new tab)PaperDOI 10.1038/s41586-020-1942-4Nature
    Single-shot dynamics of spin-orbit torque and spin transfer torque switching in three-terminal magnetic tunnel junctions (Nat. Nanotechnol. 15, 111) (opens in a new tab)PaperDOI 10.1038/s41565-019-0607-7Nature Nanotechnology
    Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays (opens in a new tab)PreprintarXiv
    First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under (opens in a new tab)PaperDOI 10.1109/iedm19573.2019.89934432019 IEEE International Electron Devices Meeting (IEDM)
    Demonstration of BEOL-compatible ferroelectric Hf0.5Zr0.5O2 scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications (opens in a new tab)PaperDOI 10.1109/iedm19573.2019.8993485Technical digest - International Electron Devices Meeting
    RoboNet: Large-Scale Multi-Robot Learning (opens in a new tab)PreprintDOI 10.48550/arxiv.1910.11215arXiv
    Ovonic threshold switching selectors for three-dimensional stackable phase-change memory (opens in a new tab)PaperDOI 10.1557/mrs.2019.206MRS Bulletin
    Opportunities and challenges for spintronics in the microelectronics industry (opens in a new tab)PreprintarXiv
    Accurate deep neural network inference using computational phase-change memory (opens in a new tab)PreprintarXiv
    Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM (opens in a new tab)PaperDOI 10.23919/vlsit.2019.87765372019 Symposium on VLSI Technology
    Subsystem under 3D-Storage Class Memory on a chip (opens in a new tab)PaperDOI 10.1016/j.compeleceng.2019.01.009Computers and Electrical Engineering
    Basic Performance Measurements of the Intel Optane DC Persistent Memory Module (opens in a new tab)PreprintDOI 10.48550/arxiv.1903.05714arXiv
    Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization (opens in a new tab)PreprintarXiv
    13.2 A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology (opens in a new tab)PaperISSCC
    PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference (opens in a new tab)PreprintarXiv
    Direct Correlation of Ferroelectric Properties and Memory Characteristics in Ferroelectric Tunnel Junctions (opens in a new tab)PaperDOI 10.1109/jeds.2019.2932138IEEE Journal of the Electron Devices Society
    14ns write speed 128Mb density Embedded STT-MRAM with endurance>1010 and 10yrs retention@85°C using (opens in a new tab)PaperDOI 10.1109/iedm.2018.86146062018 IEEE International Electron Devices Meeting (IEDM)
    MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology (opens in a new tab)PaperDOI 10.1109/iedm.2018.86146202018 IEEE International Electron Devices Meeting (IEDM)
    Demonstration of Highly Manufacturable STT-MRAM Embedded in 28nm Logic (opens in a new tab)PaperDOI 10.1109/iedm.2018.86146352018 IEEE International Electron Devices Meeting (IEDM)
    Vertical Ferroelectric HfO2 FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory (opens in a new tab)PaperDOI 10.1109/iedm.2018.8614710Technical digest - International Electron Devices Meeting
    Efficient and self-adaptive in-situ learning in multilayer memristor neural networks (opens in a new tab)PaperDOI 10.1038/s41467-018-04484-2Nature Communications
    In-memory computing with resistive switching devices (opens in a new tab)PaperDOI 10.1038/s41928-018-0092-2Nature Electronics
    Embedded STT-MRAM in 28-nm FDSOI Logic Process for Industrial MCU/IoT Application (opens in a new tab)PaperDOI 10.1109/vlsit.2018.85106232018 IEEE Symposium on VLSI Technology
    22-nm FD-SOI Embedded MRAM with Full Solder Reflow Compatibility and Enhanced Magnetic Immunity (opens in a new tab)PaperDOI 10.1109/vlsit.2018.85106552018 IEEE Symposium on VLSI Technology
    Demonstration of Ultra-Low Voltage and Ultra Low Power STT-MRAM (opens in a new tab)PaperDOI 10.1109/vlsit.2018.85106722018 IEEE Symposium on VLSI Technology
    Mars Helicopter Technology Demonstrator (opens in a new tab)PaperDOI 10.2514/6.2018-0023AIAA Aerospace Sciences Meeting
    Implementation of multilayer perceptron network with highly uniform passive memristive crossbar circuits (opens in a new tab)PreprintarXiv
    Analogue signal and image processing with large memristor crossbars (opens in a new tab)PaperDOI 10.1038/s41928-017-0002-zNature Electronics
    Ferroelectric FET analog synapse for acceleration of deep neural network training (opens in a new tab)PaperDOI 10.1109/iedm.2017.8268338Technical digest - International Electron Devices Meeting
    A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond (opens in a new tab)PaperDOI 10.1109/iedm.2017.8268425Technical digest - International Electron Devices Meeting
    Reconfigurable NAND/NOR logic gates in 28 nm HKMG and 22 nm FD-SOI FeFET technology (opens in a new tab)PaperDOI 10.1109/iedm.2017.8268471Technical digest - International Electron Devices Meeting
    First demonstration of vertically stacked ferroelectric Al doped HfO2 devices for NAND applications (opens in a new tab)PaperDOI 10.23919/vlsit.2017.7998162Symposium on VLSI Technology
    Mixed-precision in-memory computing (opens in a new tab)PreprintarXiv
    A novel true random number generator based on a stochastic diffusive memristor (opens in a new tab)PaperDOI 10.1038/s41467-017-00869-xNature Communications 8, 882 (2017)
    A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs (opens in a new tab)PaperDOI 10.1109/iedm.2016.7838397Technical digest - International Electron Devices Meeting
    Acceleration of Deep Neural Network Training with Resistive Cross-Point Devices: Design Considerations (opens in a new tab)PaperDOI 10.3389/fnins.2016.00333Frontiers in Neuroscience
    Resistive memory device requirements for a neural algorithm accelerator (opens in a new tab)PaperDOI 10.1109/ijcnn.2016.7727298
    ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars (opens in a new tab)PaperDOI 10.1109/isca.2016.12ISCA
    Physical Mechanisms behind the Field‐Cycling Behavior of HfO 2 ‐Based Ferroelectric Capacitors (opens in a new tab)PaperDOI 10.1002/adfm.201600590Advanced Functional Materials
    Nanosecond-timescale low error switching of in-plane magnetic tunnel junctions through dynamic Oersted-field-assisted spin Hall effect (opens in a new tab)PreprintarXiv
    Projected phase-change memory devices (opens in a new tab)PaperDOI 10.1038/ncomms9181Nature Communications
    AMD's Next Generation GPU and High Bandwidth Memory Architecture: FURY (opens in a new tab)PresentationHot Chips 27
    A new spin on magnetic memories (opens in a new tab)PaperDOI 10.1038/nnano.2015.24Nature Nanotechnology
    Ferroelectricity and Antiferroelectricity of Doped Thin HfO 2 ‐Based Films (opens in a new tab)PaperDOI 10.1002/adma.201404531Advanced Materials
    Training and Operation of an Integrated Neuromorphic Network Based on Metal-Oxide Memristors (opens in a new tab)PreprintarXiv
    A million spiking-neuron integrated circuit with a scalable communication network and interface (opens in a new tab)PaperDOI 10.1126/science.1254642Science
    Wake-up effects in Si-doped hafnium oxide ferroelectric thin films (opens in a new tab)PaperDOI 10.1063/1.4829064Applied Physics Letters
    Ultrafast magnetization switching by spin-orbit torques (opens in a new tab)PreprintarXiv
    A Fully Functional 64 Mb DDR3 ST-MRAM Built on 90 nm CMOS Technology (opens in a new tab)PaperDOI 10.1109/tmag.2013.2243133IEEE Transactions on Magnetics
    Spin-transfer torque magnetic random access memory (STT-MRAM) (opens in a new tab)PaperDOI 10.1145/2463585.2463589ACM Journal on Emerging Technologies in Computing Systems
    Basic principles of STT-MRAM cell operation in memory arrays (opens in a new tab)PaperDOI 10.1088/0022-3727/46/7/074001Journal of Physics D: Applied Physics
    Ferroelectricity in Simple Binary ZrO 2 and HfO 2 (opens in a new tab)PaperDOI 10.1021/nl302049kNano Letters
    Breaking the Speed Limits of Phase-Change Memory (opens in a new tab)PaperDOI 10.1126/science.1221561Science
    Spin torque switching with the giant spin Hall effect of tantalum (opens in a new tab)PreprintarXiv
    Ferroelectricity in hafnium oxide: CMOS compatible ferroelectric field effect transistors (opens in a new tab)PaperDOI 10.1109/iedm.2011.6131606Technical digest - International Electron Devices Meeting
    A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction (opens in a new tab)PaperDOI 10.1038/nmat2804Nature Materials
    Complementary resistive switches for passive nanocrossbar memories (opens in a new tab)PaperDOI 10.1038/nmat2748Nature Materials
    A stackable cross point Phase Change Memory (opens in a new tab)PaperDOI 10.1109/iedm.2009.5424263IEDM
    A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MR (opens in a new tab)PaperDOI 10.1109/iedm.2008.47966792008 IEEE International Electron Devices Meeting
    Corona: System Implications of Emerging Nanophotonic Technology (opens in a new tab)PaperDOI 10.1109/isca.2008.35ISCA
    The missing memristor found (opens in a new tab)PaperDOI 10.1038/nature06932Nature
    Nanoionics-based resistive switching memories (opens in a new tab)PaperDOI 10.1038/nmat2023Nature Materials
    Tunneling Across a Ferroelectric (opens in a new tab)PaperDOI 10.1126/science.1126230Science
    Physics of thin-film ferroelectric oxides (opens in a new tab)PreprintarXiv
    Giant electroresistance in ferroelectric tunnel junctions (opens in a new tab)PreprintarXiv
    A 4-Mb toggle MRAM based on a novel bit and switching method (opens in a new tab)PaperDOI 10.1109/tmag.2004.840847IEEE Transactions on Magnetics
    Polarization fatigue in ferroelectric films: Basic experimental findings, phenomenological scenarios, and microscopic features (opens in a new tab)PaperDOI 10.1063/1.1381542Journal of Applied Physics
    Spin-current interaction with a monodomain magnetic body: A model study (opens in a new tab)PaperDOI 10.1103/physrevb.62.570Physical Review B
    Emission of spin waves by a magnetic multilayer traversed by a current (opens in a new tab)PaperDOI 10.1103/physrevb.54.9353Physical Review B
    Ferroelectric Memories (opens in a new tab)PaperDOI 10.1126/science.246.4936.1400Science

    Memory Memory for AI, CXL pooling and processing in memory

    Foundational 5

    WorkSourceDate
    The 5 minute rule for trading memory for disc accesses and the 10 byte rule for trading memory for CPU time (opens in a new tab)PaperDOI 10.1145/38713.38755SIGMOD
    Hitting the memory wall: implications of the obvious (opens in a new tab)PaperDOI 10.1145/216585.216588ACM SIGARCH Computer Architecture News
    A 20nm 6GB function-in-memory DRAM, based on HBM2 with a 1.2TFLOPS programmable computing unit using bank-level parallelism, for machine learning applications (opens in a new tab)Die paperDOI 10.1109/isscc42613.2021.9365862ISSCC 2021 (paper 25.4), Samsung Electronics
    Pond: CXL-based memory pooling systems for cloud platforms (opens in a new tab)PaperDOI 10.1145/3575693.3578835ASPLOS
    AI and memory wall (opens in a new tab)PaperDOI 10.1109/mm.2024.3373763IEEE Micro

    Papers, talks and releases 10

    TitleSourceDate
    Three-dimensional dynamic random-access memory beyond two-dimensional scaling limits (opens in a new tab)PaperDOI 10.1038/s44287-026-00347-xNature Reviews Electrical Engineering
    A Hybrid GPU and Processing-Near-Memory Architecture with Shared DRAM for Efficient Prefill-Decode Disaggregation (opens in a new tab)PreprintarXiv (cs.AR)
    CMM-MP: A Novel Memory Pooling Architecture using Purpose-built Memory Device with CXL and Ethernet (opens in a new tab)PreprintarXiv (cs.AR)
    Indexing Designs and Adaptive Data Distribution Optimization for In-Memory Databases on Hybrid DDR-CXL Memory (opens in a new tab)PreprintarXiv
    Custom HBM as a System: Co-designing the Base Die, Die-to-Die Power, and Package Thermals for AI (opens in a new tab)PresentationMarvell walks through what HBM4's 2,048-bit interface does to the base die, and why that die, its power delivery and the package thermals now get designed together with the accelerator.OCP Global Summit
    Tiered Memory for LLM Inference: A Modeling Framework for KV-Cache Offload (opens in a new tab)PresentationMicron models where an inference server's KV cache should live once HBM capacity runs out, across CPU DRAM, CXL memory and SSDs, and when the CXL tier starts to pay off.OCP Global Summit
    Disaggregated CXL Memory Architecture for Agentic AI: Dynamic Pooling, Sharing, and PNM Offloading (opens in a new tab)PresentationSamsung and partners show CXL memory pooled and shared between servers for agentic AI, with processing-near-memory taking part of the KV-cache work.OCP Global Summit
    Vertical Optimizations for KV Cache Infrastructure (opens in a new tab)PresentationSamsung argues KV cache is a new kind of ephemeral, recomputable data and shows how SSD requirements, including Flexible Data Placement, can be tuned for it.OCP Global Summit
    Beyond HBM-on-GPU: Thermal Design Envelope for 3D Volumetric DRAM-on-GPU Integration (opens in a new tab)PreprintarXiv
    A Photonic-CXL Memory Appliance for Scalable KV Cache Management in LLM Inference (opens in a new tab)PreprintDOI 10.48550/arxiv.2607.27187arXiv

    After the zones

    Maker news and patents604 entries

    Product news from the makers’ own newsrooms, and patents by assignee. Patents start hidden; Show patents lists them.

    Rows
    Topic

    Showing 1 to 20 of 273, 331 patents hidden

    2026

    1. GlobalWafers Proposes US$500 Million Private Placement of Convertible Bonds; Micron Designated as Sole Subscriber (opens in a new tab)

      Maker announcementIndustry

      GlobalWafers

    2. Price rises for some 16GB Raspberry Pi products (opens in a new tab)

      Maker announcementIndustry

      Raspberry Pi

    3. Micron and Lenovo put 1-gamma LPCAMM2 at 8533 MT/s in the ThinkPad P1 Gen 9 mobile workstation (opens in a new tab)

      Maker announcementInterfaces, Industry

      Micron

    4. Seagate Technology Reports Fiscal First Quarter 2027 Financial Results (opens in a new tab)

      Maker announcementIndustry

      Seagate Technology

    5. Nagare Labs: Z2RAM, memory designed for AI infrastructure, integrated directly on the AI accelerator (opens in a new tab)

      Maker announcementEmerging memory, Industry

      Nagare Labs

    6. SK hynix ends the Solidigm IPO review and says Solidigm needs additional production facilities in the U.S. (opens in a new tab)

      Maker announcementIndustry

      SK hynix

    7. Everspin Technologies to Chair New JEDEC Task Group Exploring LPDDR Persistent Memory Standard (opens in a new tab)

      Maker announcementEmerging memory, Industry

      Everspin Technologies

    8. Samsung Electronics Announces Earnings Guidance for Third Quarter 2026 (PRELIMINARY) (opens in a new tab)

      Maker announcementIndustry

      Samsung

    9. NVIDIA Vera Rubin NVL72 spec table: 288GB of HBM4 at 19.2TB/s per Rubin GPU (NVIDIA's July 2026 developer blog says up to 22TB/s) (opens in a new tab)

      Maker announcementIndustry

      NVIDIA

    10. Micron Technology, Inc. Reports Record Fiscal Fourth-Quarter and Full-Year 2026 Results (opens in a new tab)

      Maker announcementIndustry

      Micron

    11. Samsung V-NAND : A Landmark of the Hyperscale AI Era (opens in a new tab)

      Maker announcementNAND dies

      Samsung

    12. Samsung LPDDR6: Advancing Low-Power Memory for AI with Industry-First Validation on Qualcomm Technologies' New Snapdragon Platform (opens in a new tab)

      Maker announcementEmerging memory

      On the DRAM Die Timeline

      Samsung

    13. [FMS 2026 3D & NAND Innovation Award] V10 BV-NAND: Pushing the Boundaries of AI Storage Beyond 400 Layers (opens in a new tab)

      Maker announcementNAND dies

      On the NAND Die Timeline

      Samsung

    14. Phison 2Q26 Consolidated Financial Report Announcement (opens in a new tab)

      Maker announcementIndustry

      Phison

    15. Sandisk Investor Day 2026, Next Wave of Innovation (Ilkbahar, CTO) (opens in a new tab)

      Maker announcementIndustry

      Sandisk

    16. HBF at FMS 2026 (opens in a new tab)

      Maker announcementIndustry

      SK hynix

    17. New 3D Flash Memory Technology from Kioxia and Sandisk Achieves Industry's Highest Bit Density for QLC NAND (opens in a new tab)

      Maker announcementNAND dies

      On the NAND Die Timeline

      Kioxia

    18. Samsung Unveils Next-Gen 3D-Memory Vision at FMS 2026, Charting the Future of AI Infrastructure (opens in a new tab)

      Maker announcementNAND dies, Emerging memory

      Samsung

    19. Sandisk and SK hynix Advance Global Standardization of High Bandwidth Flash with Release of First OCP Technical Specification (opens in a new tab)

      Maker announcementInterfaces, NAND dies

      Sandisk

    Where to go next

    The standards timeline dates every revision and its headline speed. The NAND die, DRAM die, HBM and controller timelines hold the parts these papers describe, and Flash Foundations explains how they work.