Beyond NAND, Part 4: Ferroelectric Memory From Polarization to Product

Memory map gave ferroelectric memory one section and a plain fact. It is already on sale, in small parts, while its newest forms are still research. This part opens the film first, then the capacitor that has been mass-produced since 1999, then the transistor and the NAND stringA NAND string is a column of cells connected in series between a bitline and the source line, with a select transistor at each end. that have not, and ends on the numbers that explain the gap. Beyond NAND has the other parts.

Polarization and hysteresis

A bit that is a field, not a current

A ferroelectric film holds an electric polarization that points one of two ways, and a strong enough field turns it around. Two directions are the two states of a bit. Polarization left when the field is removed is the remanent polarization, and the field that has to be exceeded to flip it is the coercive field. Plot polarization against field and the film traces a loop, with two stable points at zero field.

Switching is purely field driven. It happens once the applied field exceeds the coercive field, and it needs no current through the cell (a review by Mikolajick and colleagues). That sets it apart from the spin-torque cells of Part 3 and the resistive cells of Part 5, where not every electron contributes to switching.

How a film flips

Films do not flip all at once. It switches by nucleating many reverse domains at particular, non-random sites, then fast forward growth of those domains across the film, then slower sideways widening. Unlike a ferromagnet, the switching is not mainly sideways motion of an existing wall (a review by Dawber, Rabe and Scott).

In hafnia-based ferroelectrics the speed is set by that nucleation and growth, and it has been reported faster than 300ps. It follows an activation law, so a field well above the coercive field switches exponentially faster, at the cost of voltage and earlier breakdown (APL Materials roadmap). Real-time electron microscopy of hafnium oxide films shows the reversal passing through a transient tetragonal-like local structure as oxygen ions move within their parent hafnium polyhedra (Calderon and colleagues, a preprint).

Why hafnia was a surprise

Ferroelectrics that memory used for decades are perovskite ceramics such as strontium bismuth tantalate (SBT) and lead zirconate titanate (PZT). Ferroelectricity in hafnium oxide was reported in 2011. In bulk it is monoclinic at room temperature and pressure and turns tetragonal and cubic only at 1973K and 2773K, and those three phases have permittivities of 22, 46 and 36. Ferroelectricity here sits in a different phase, orthorhombic, with no inversion symmetry, and electron diffraction confirmed it (Mikolajick and colleagues, again).

Böscke and colleagues gave the first report. Doped hafnium oxide films about 10nm thick, with less than 4 mol% silicon oxide, crystallize in a mix of monoclinic and tetragonal phases. Crystallized under a mechanical cap, they form an orthorhombic phase that is piezoelectric and shows a remanent polarization above 10µC/cm² at a coercive field of 1MV/cm, which the authors take to be ferroelectric (abstract). Böscke’s group put the film in transistors as the gate insulator and saw a permanent, switchable shift of the threshold voltageThreshold voltage, Vt, is the gate voltage at which a flash cell starts to conduct. The stored charge shifts it, and the controller reads data from it., the first CMOS-compatible FeFETs with gate insulators under 10nm (abstract).

A year later, Müller and colleagues showed that pure zirconium oxide films under 10nm thick undergo a field-driven transition to a ferroelectric phase, and that hafnium-zirconium mixed oxide has a composition- and temperature-dependent transition to a stable one (abstract). That phase is orthorhombic too, with no inversion symmetry, which is what lets a crystal hold a spontaneous polarization.

The new material differs in its field. Mikolajick and colleagues tabulate four ferroelectrics, SBT at a coercive field of 0.05MV/cm, PZT at 0.1MV/cm, the polymer PVDF-TrFE at 0.5MV/cm and doped hafnium oxide at 0.8 to 2MV/cm. Switched charge (2Pr) is 15 to 25µC/cm² for SBT, 30 to 60 for PZT and doped hafnium oxide, and 10 for the polymer. So hafnia has about ten times the coercive field of the perovskites at similar polarization.

Figure 4.1 draws the loop on the left, as a schematic, and the four coercive fields on the right on a log axis. High coercive field is a mixed result. Inside a capacitor it means cycling close to breakdown, and in a transistor it means a larger window from a thin film, as the next two sections show.

FeRAM: a capacitor with memory

Capacitor FeRAM is the form that has been in production since 1999. This section covers the cell, why the ceramic version stopped shrinking, and what the hafnia version has shown.

One transistor, one capacitor, one pulse

A one-transistor, one-capacitor (1T1C) ferroelectric cell is a DRAM-like cell with the dielectric replaced by a ferroelectric and the plate line pulsed. Storage sits at 0V, and the capacitor has to be actively driven to be read, so the read is destructive and read cycles count toward endurance (Mikolajick and colleagues). Infineon’s datasheet says the same in product terms: F-RAM reads are destructive and restored internally, so every access, read or write, costs one endurance cycle on the whole row it touches (datasheet).

Why the perovskite version stalled

Perovskite FeRAM stalled at the 130nm process generation and did not follow other memories into the 20nm regime. Mikolajick and colleagues give four reasons. They are the thermal budget, sensitivity to hydrogen, missing deposition techniques and a three-dimensional capacitor that was never solved.

It is still sold. An industry review of PZT embedded FRAM covers a 130nm, 1.5V product in which the FRAM module is a two-mask adder to standard 130nm CMOS. It says commercial PZT FRAM uses planar capacitors with drawn sizes from about 3µm² down to about 0.4µm² (Electronics, 2025). With no three-dimensional capacitor the array stays flat, which fits the densities of the parts in the last section.

The hafnia version

Hafnia changes the capacitor. State of the art is an 8 to 10nm hafnium-zirconium oxide (HZO) film with a coercive field near 1.5MV/cm, a switched charge (2Pr) near 40µC/cm² and switching in the nanosecond range. Lowering the switching voltage improves endurance but worsens retention, so the voltage is a trade (APL Materials roadmap). Okuno in 2020, Francois, and Okuno in 2022 show it in arrays.

A 64kbit 1T1C hafnia array on 130nm CMOS showed 2Pr above 40µC/cm², endurance above 10¹¹ cycles, 10-year retention at 85°C by extrapolation, and 100% bit functionality at 2.5V and 14ns (Okuno and colleagues, 2020, abstract). Its TiN/HZO/TiN capacitor was made in a process under 500°C. HZO capacitors scaled from 100µm diameter down to 300nm were integrated in the back end of 130nm CMOS, with the same 2Pr and endurance, switching under 100ns, operation under 4V and retention at 125°C, pointing to under 10fJ per bit (Francois and colleagues, abstract).

Thickness matters. On a 64kbit 130nm array an 8nm film had a breakdown field of 4.8MV/cm against 4.2MV/cm for 10nm, and lasted more cycles before hard breakdown, so a thinner film allows lower voltage and longer life (Okuno and colleagues, 2022).

The big one: a 32Gb paper

Micron’s NVDRAM is a 32Gb, two-layer, non-volatile ferroelectric memory. Its abstract describes a 5.7nm ferroelectric capacitor cell, a stackable poly-silicon access transistorAn access transistor is the switch that connects one memory cell to its bit line when the cell’s word line rises, so only the selected row is read or written., a 4F² layout at 48nm pitch above CMOS, an LPDDR5 command protocol and a bit density of 0.45Gb/mm² that Micron puts above its 1-beta planar DRAM (Ramaswamy and colleagues). Cell area in F² is the unit that density uses.

Ettisserry’s companion paper names imprint, fatigue and disturb as known mechanisms. It adds a bipolar AC time-dependent dielectric breakdown failure mode and a frequency-dependent accelerated polarization loss, and proposes an Effective Read Window metric to show more than 10 years of reliability (Ettisserry and colleagues, abstract). Ramaswamy and colleagues report a paper result, with no product named in the abstract. Working Memory, Part 3 holds the cycling and read-window figures this section leaves out (What Could Follow DRAM).

Figure 4.2 shows the cell as a schematic and one read as three steps. One measured number sits in the box at the bottom. The 64kbit array above ran at 14ns and 2.5V, and that timing belongs to that array alone.

FeFET: polarization moves the threshold

A FeFET puts the ferroelectric in the gate of a transistor instead of in a separate capacitor. IRDS calls it a MISFET with a ferroelectric oxide in the gate stack, and a gate pulse above the coercive voltage sets the polarization, which shifts the threshold voltage and allows a non-destructive read (IRDS). One transistor is the whole cell, so there is no plate line and no restore step.

The window

Memory window is the difference between the two threshold voltages. Inside a FeFET it is set by the coercive field times the film thickness, about 2 × Ec × d (Mikolajick and colleagues). Hafnia’s high coercive field is a benefit here for that reason, and perovskites needed much thicker films to get the same window. Logic use of one FeFET as a gate stays on the memory map.

Embedded arrays

Trentzsch and colleagues built a one-transistor FeFET embedded memory in a 28nm gate-first low-power CMOS platform with two extra masks. A 64kbit array showed clearly separated states, retention to 250°C and endurance to 10⁵ cycles (abstract). On 22nm FDSOI, a FeFET array showed a 1.5V memory window in cells as small as 0.025µm², endurance to 10⁵ cycles, 32Mbit arrays written with 10ns pulses at 4.2V, and retention to 300°C (Dünkel and colleagues, abstract). Neither abstract gives a duration for those retention temperatures, so Figure 4.4 does not plot them.

Gate-stack engineering has gone much further in a research cell. A hafnia FeFET reached a 10V memory window and 16 levels per cell without growing the device area (Science Advances, 2024, abstract). Sixteen is the number of states in a QLC NAND cell, which Figure 4.3 sets beside a FeFET’s two.

What the gate stack does to it

Stack under the ferroelectric is the weak point. A FeFET’s interlayer oxide is in series with the ferroelectric, so a large polarization puts a large field across it and breaks it down, and charge trapping at the interface is the most damaging non-ideality. Endurance is limited by the gate stack rather than by the ferroelectric film (APL Materials roadmap).

Typical reported FeFET endurance is about 10⁴ to 10⁶ write cycles, far from the 10¹² the IRDS requires (Zagni, Pavan and Alam). Silicon-based FeFETs sit at about 10⁵ on that roadmap, limited mainly by degradation of the channel interface, and a high-k silicon nitride layer between the silicon and the film took HZO past 10¹⁰ cycles. A critical review of HfO₂ FeFETs names three persistent challenges, retention, endurance and variability, and says a deep understanding of the reliability physics is a prerequisite for commercialization (Padovani and colleagues, abstract).

Stacked into a NAND string

A ferroelectric NAND string ties this back to flash. Florent and colleagues made the first 3D ferroelectric Al-doped hafnium oxide device for NAND in 2017, with poly-silicon channels 60 to 200nm in diameter, a 6V loop width (2Vc) and an estimated time to failure above 10 years of retention at 85°C (abstract). A vertical ferroelectric HfO₂ FET in a 3D macaroni NAND architecture then gave up to a 2V memory window after 100ns program and erase pulses and 10⁴ cycles of endurance, which the authors call flash-like (Florent and colleagues, 2018, abstract).

A ferroelectric string would swap the oxide-nitride-oxide charge-trap layer of today’s 3D NAND for a ferroelectric, so the string structure and operation could mostly be kept. Polarity runs the other way, since a positive threshold shift needs a negative gate-to-channel voltage, so the channel has to be taken positive. A vertical string has no body contact to raise the channel, and a bit-line or source-line voltage does not pass through the resistive silicon channel. Heavily n-doped channels were proposed for that reason, and the paper proposes a new operating scheme and checks it in device simulation (Electronics, 2020). Flash Foundations Part 4 covers the strings these would replace. Florent’s strings and the 2020 operating scheme are research devices, with no product named.

A third cell: the tunnel junction

A ferroelectric can also be the barrier of a tunnel junction, the structure Part 3 built from magnets. Inside a ferroelectric tunnel junction (FTJ) the barrier is the ferroelectric. If the two metal electrodes screen differently, reversing the polarization changes the potential profile that tunneling electrons see, and a model predicts a conductance change of a few orders of magnitude (Zhuravlev and colleagues, a theory paper).

With hafnia the film has to be under about 5nm. Early junctions gave a tunneling electroresistance of 20 at a 2.8nm barrier probed with an atomic force microscope tip, and stand-alone devices with 1.5 to 2nm HZO barriers, 30 by 30µm², worked at an on/off ratioThe on/off ratio is how many times more current a low-resistance cell passes than a high-resistance one at the same voltage. A bigger ratio makes reads easier. of 50 (APL Materials roadmap). A 1nm Zr-doped hafnium oxide junction grown by atomic layer deposition on silicon showed an electroresistance above 20,000% and a tunneling current above 1A/cm² at low read voltage (Advanced Electronic Materials, 2021, abstract).

Two limits follow. Cyclability is the problem because the switching fields approach breakdown and move oxygen vacancies as in resistive memory. Robust switching shows up mainly at low voltage, where the reported electroresistance falls to about 5 (roadmap). And partial switching can give several levels. In HZO/Al₂O₃ junctions the fraction of reversed domains can be set by pulse amplitude and width, but endurance tracks wake-up and fatigue and is ultimately limited by hard breakdown (IEEE JEDS, 2019, abstract).

Figure 4.3 puts a FeFET’s one window beside the many states of NAND. Right panel numbers come from papers: 1.5V in the embedded 22nm array, 2V in the NAND string and 10V in the 16-level research cell. Left panel follows the schematic style of Flash Foundations Part 2, with no voltages printed for the NAND rows, because that figure uses teaching shapes and not measurements. It shows the count. A QLC cell must tell apart 16 states where a FeFET tells apart two.

Retention against temperature

Retention is how long the polarization stays put, and it is never one number. Every datasheet states it at a temperature, and the figure below plots the ones given in this part.

What retention is asked to be

APL Materials roadmap sets the targets at 10 years at 85°C for general-purpose use, 125°C for industrial use and 165°C for automotive use.

What degrades it

Two mechanisms degrade retention. Thermal depolarization is the fall of remanent polarization as temperature rises toward the Curie temperature, which is above 350°C for hafnia films and lower for thinner or doped ones. Imprint lowers the opposite-state polarization and raises the coercive field needed to switch it (roadmap). It arises because the fields in operation attract charge from the electrodes and drift charged defects in the film, which can leave switching incomplete and let the polarization flip back spontaneously.

For HfO₂ capacitors, polarization sensing problems caused by imprint are described as the most critical reliability concern for production. A charge-injection imprint model from PZT was adapted to HZO and points to an interface-driven mechanism (IRPS 2024 abstract).

What the datasheets say

Infineon’s industrial 4Mb F-RAM is specified for 10 years at 85°C, 38 years at 75°C and 151 years at 65°C (datasheet). Quoted 151 years is the 65°C case. Its automotive grade 1 part is specified for 11,000 hours at 125°C, about 1.25 years, then 11 years at 105°C and 121 years at 85°C (datasheet). Retention accumulates across a temperature profile. Infineon’s worked example, with 10% of the time at 125°C, 15% at 105°C, 25% at 85°C and 50% at 55°C, comes to more than 10.46 years.

Texas Instruments rates its FRAM microcontroller at 100 years at 25°C, 40 years at 70°C and 10 years when the part is held at 85°C (datasheet).

Figure 4.4 plots those points, with the roadmap’s three targets as rings. Three parts with different qualification draw those lines, so read each as a few points from one datasheet and not as a family of curves. At 125°C the automotive part is rated for about 1.25 years, below the roadmap’s 10-year ring at that temperature, and the worked example above is how its datasheet turns that into a lifetime.

FeFET retention

Embedded FeFET arrays report retention to 250°C and 300°C, but their abstracts give a temperature and no duration, so the figure leaves them out. Hafnia capacitor arrays are in the same position. Okuno’s 130nm array gives a 10-year figure at 85°C as an extrapolation, and the back-end-integrated capacitors report retention at 125°C without a duration. The voltage trade from the FeRAM section applies here too, and a lower switching voltage means worse retention.

Wake-up, fatigue, imprint and endurance

A ferroelectric film is not the same after a million cycles as on day one. It first improves, then wears. This section covers what changes, and then puts the endurance numbers side by side.

Wake-up

Wake-up is the rise in remanent polarization during early field cycling, in which a pinched hysteresis loop opens. Cells that have not woken up have less remanent polarization to read. Proposed causes are charges pinning domains until the field redistributes them, a field-driven change from a non-polar tetragonal phase to the polar orthorhombic one, and strain relaxation (APL Materials roadmap). An abstract by Pesic and colleagues says that during wake-up no new defects are generated and the existing ones redistribute, and that vacancy diffusion is the main cause of the phase change that raises the remanent polarization (abstract).

Fatigue and imprint

Fatigue is the loss of switchable polarization under electrical stress, and it is a major problem for ferroelectric non-volatile memories. A 2001 review of PZT-type films concluded that electron injection plays the predominant role over oxygen vacancy migration (Tagantsev and colleagues, abstract). In HfO₂ capacitors, wake-up and fatigue are the two regimes of device life (Pesic and colleagues, again).

Imprint, covered above as a retention problem, is also a sensing problem, and Micron’s NVDRAM paper names imprint, fatigue and disturb together as the known mechanisms it has to manage.

Endurance, side by side

Reported endurance of hafnia ferroelectric devices rose from 10⁴ cycles in 2012 to 10¹¹, and small production-type capacitors may exceed 10¹⁴. Flash sits at about 10⁶ on that roadmap, phase-change memoryPhase-change memory stores data in a material that switches between a crystalline, low-resistance state and an amorphous, high-resistance state when heated. at 10¹⁰, valence-change resistive memory at 10¹² and spin-transfer MRAM up to 10¹⁵. Hafnia’s high coercive field means cycling runs close to the breakdown field, which limits endurance, and wake-up and fatigue still have to be engineered down to the levels of perovskite ferroelectrics (Mikolajick and colleagues). Their flash figure is a broad one for flash in general. TLC and QLC NAND in today’s SSDs are rated far lower. Flash Foundations Part 2 gives those ranges by cell type.

Figure 4.5 puts eight numbers on one axis, and they are not all the same kind of number. Copper bars are research results from abstracts and reviews. A typical FeFET sits at 10⁴ to 10⁶. The embedded arrays sit at 10⁵, the vertical string at 10⁴ and hafnia capacitor arrays above 10¹¹. Teal bars are what Infineon and Texas Instruments rate their parts for, and the gray bar is an EEPROM datasheet. Dashed line marks the 10¹² that the IRDS asks of a FeFET. Research best beside a datasheet rating shows how far the transistor form has to go. Capacitor arrays and FeFETs are different devices.

Reads cost endurance

One more thing sits behind every capacitor number. Reads count. Every access, read or write, costs one cycle on the whole row it touches, so a rating of 10¹⁴ is a rating on accesses, and a part that is read often spends it on reads.

Parts and papers

Ferroelectric memory comes in three forms: as parts you could order, as arrays built into logic processes, and as demonstrations. Keeping those apart is most of the work of reading any announcement.

Small parts, for decades

Fujitsu’s FRAM mass production started in 1999. Its parts are rated 10¹⁰ to 10¹⁴ write cycles, -40 to 125°C, 1.7 to 3.6V and up to 108MHz (a survey of company disclosures by Hellenbrand, Teck and MacManus-Driscoll). RAMXEED’s August 2025 catalog lists FeRAM from 4Kbit to 8Mbit in serial (SPI, I2C) and parallel interfaces, endurance of 1, 10 or 100 trillion read/write cycles, and operating temperatures up to 125°C (catalog). Texas Instruments’ MSP430FR5994 microcontroller has up to 256KB of FRAM, writes a word in 125ns and is rated for 10¹⁵ read and write cycles (TI datasheet, again).

Why a robot joint wants it

A humanoid-robot joint or a battery controller is a good test of the datasheets. Consider a controller that writes small records all the time, can lose power at any moment and sits in a hot joint. A typical SPI serial EEPROM takes up to 5ms for each self-timed write cycle and is rated for 1,000,000 erase/write cycles (Microchip 25LC256). Part 1 says what EEPROM is. Infineon’s industrial F-RAM stores at bus speed with no write delay, and is rated for 10¹⁴ read/write cycles. For scale, Goldman Sachs Research’s public 2024 forecast put humanoid robot shipments at 1.4 million units by 2035 (Goldman Sachs). Humanoid.guide later reported that Goldman Sachs raised that 2035 shipment forecast to about 6.5 million units (Humanoid.guide).

Infineon’s product page goes further, marketing its automotive F-RAM as able to log data every 10µs for 20 years within its 10 trillion cycle endurance (Infineon). Infineon’s line is a vendor claim, and the datasheets add three cautions.

First, every read spends a cycle. Second, the automotive grade 1 part is rated for 10¹³ cycles and the industrial one for ten times as many. Third, a hot joint spends the retention budget: a 10-year rating at 85°C for the industrial part, 11,000 hours at 125°C for the automotive one. No write delay and very high endurance hold up, with retention counted across the temperatures the joint sees.

Arrays and papers

Demonstrations supply the rest of what this guide reports. They are the 28nm and 22nm FeFET arrays at 64kbit and 32Mbit and the hafnia FeRAM arrays at 64kbit. They also include an 8Gbit hafnia array in the APL roadmap’s first table, the capacitors scaled to 300nm, the two 3D NAND strings and Micron’s 32Gb NVDRAM. None of them is called a product on sale. A 2026 arXiv preprint called NORmal adds fabricated back-end-of-line 3D ferroelectric NOR arrays. They pair a dense mode that stores 3 bits per cell (MLC in the paper) with a fast mode that stores one bit (SLC), and they sense in under 7.5ns (arXiv). Its speedups over phone-storage offloading and high-bandwidth flash come from serving-level simulation of agent workloads and not from those arrays.

Figure 4.6 sorts the dated items in this guide by year and lane. Lane one is sparse, with a 1999 start and an 8Mbit catalog. Lane two is the hafnia and FeFET arrays from 2016 on. Lane three holds the 3D strings and the 32Gb paper, which is the farthest point from anything on sale.

Where it stops

Density is the sharpest limit. Orderable parts top out at 8Mbit. Hafnia 1T1C development is mostly in the 16 to 64kbit range on 2D structures at the 130nm node and older, and the APL Materials roadmap says Gbit-class hafnia arrays have already been published, with an 8Gbit array in its first table, while cell size still has to improve, and it drives cost the most (APL Materials roadmap).

Row one and the last row are about 4,000 to 1 apart, since 32Gb is 4,096 times 8Mbit (derived arithmetic).

FeFET endurance is limited on a different axis. FeFET endurance of 10⁴ to 10⁶ sits against the 10¹² needed, and the review names retention, endurance and variability. The NAND string has the polarity problem above. FTJ cyclability trades against low voltage. Hellenbrand, Teck and MacManus-Driscoll rate FRAM high in endurance and fast in read and write, moderate in retention, density and cost per bit, and note that phase-change and ferroelectric memory are less available as products than magnetic and resistive memory (Hellenbrand, Teck and MacManus-Driscoll).

Ferroelectric memory stands as a small, hard-working embedded and microcontroller memory that has been in production since 1999. Hafnia could change that, and the evidence so far is arrays of tens of kilobits in most 1T1C work, and then one 32Mbit FeFET array, an 8Gbit hafnia array listed in the APL roadmap and one 32Gb paper. Magnetic memory has a similar shape in Part 3 and resistive memory in Part 5. Beyond NAND lists the rest.