Beyond NAND, Part 1: NOR and Memory on the Processor Die

The memory map said that NOR flash can read any byte directly and that it survives the soldering oven, and then moved on. This first part of the Beyond NAND series is the account behind those two statements. A reader who finishes it can read a datasheet line for NOR on the serial peripheral interface (SPI), with its page program, sector erase, lanes and continuous read, and know what it costs, explain why a microcontroller with flash runs wait states and buffers, say what the sources give as the reason embedded flash stopped near 28nm, and say what a code memory has to survive to sit in a car.

The cost-per-bit argument and why NAND is cheap are in the memory map, and this part prints no price. Flash Foundations Part 2 covers how a NOR cell is programmed, and Part 3 covers why a NOR array pays for a contact per cell. The SRAMSRAM is fast memory of latching cells with several transistors each. It needs no refresh but takes far more area per bit than DRAM, so it serves as on-chip memory. cell and the processor cache are in Working Memory, Part 1. The families that replace embedded flash are linked where they come up below.

Each number carries its tag in the parenthesis after it: datasheet, application note, user manual, documentation, standard, vendor, trade, history, roadmap or paper. A vendor claim is a company’s own comparison or plan with no test described, a vendor relay is a vendor’s restatement of a standard, and derived means arithmetic on numbers already given, shown in the text. No prices, wafer costs or market shares appear, and clocks are in MHz, lane rates in Mb/s and totals in MB/s, or GB/s where a vendor gives it.

From EPROM to NOR, the code-memory line

Code has to live in a memory that keeps it with the power off and lets the processor fetch it. Three memories answered that, in order. They were erasable programmable read-only memory (EPROM), its electrically erasable successor (EEPROM) and NOR. Each erased at a different grain, and NOR is the one this series follows. The original papers are not free, so the history rests on a museum page, an IEEE history page and a magazine retelling, and each sentence names its outlet.

Erased by light: EPROM

IEEE’s milestone text on the floating-gate EEPROM dates Intel’s ultraviolet-erasable floating-gate EPROM to 1970, with a thick gate oxide in the range of 1,000 angstroms (ETHW, history). The Computer History Museum records that Intel announced the 1702 in 1971, a 2048-bit user-erasable PROM designed by Dov Frohman, reusable by erasing the pattern with ultraviolet light. Generations of UV EPROMs went on to store firmware for microprocessor systems, the museum adds (Computer History Museum, history).

Erased by voltage: EEPROM

That same IEEE milestone text says Eli Harari, at Hughes Microelectronics, showed in 1976 that a thin oxide of about 100 angstroms allowed an electrically erasable floating-gate EEPROM (ETHW, history). His EEPROM used Fowler-Nordheim tunnelingFowler-Nordheim tunneling is the quantum effect that lets electrons pass through the tunnel oxide when a strong electric field thins the barrier. for both write and erase. Erase grain changed with the method. Atmel’s application note says a traditional EEPROM is like flash except that erase and program are merged into one atomic write that acts on a single byte. An EEPROM can therefore update one byte without regard to its previous value or its neighbors. In flash, an erase acts on an entire page. Programming a byte that is already programmed, without erasing it, gives a bit-wise AND of the old and new values, the note adds. EEPROM cannot match flash’s speed when several bytes are stored at the same time (Atmel AT89LP application note, application note).

Cells differ too. Jim Handy of Objective Analysis told Semiconductor Engineering that the difference between EEPROM and NOR is whether it has one transistor per bit cell (NOR) or two (EEPROM). It adds that microcontrollers carry embedded flash based on EEPROM or NOR, and that both provide code storage (Semiconductor Engineering, trade, Handy quoted).

Why the series follows NOR

IEEE Spectrum tells the next step this way. Fujio Masuoka recruited four engineers in 1980 to design a cheaper, denser memory. His cell used a single transistor where conventional EEPROM needed two. He presented the design at IEDM in 1984, and that prompted Intel to begin development of flash based on NOR logic gates, which Intel introduced in 1988 as a 256-kilobit chip. Toshiba’s first NAND flashNAND flash is the memory that keeps data with the power off. Writing it is much slower than writing DRAM, and it must be erased before it is rewritten. reached the market in 1989 (IEEE Spectrum, history). The only primary hint for the Intel part is the title of its 1988 ISSCC paper, “An In-system Reprogrammable 256k CMOS Flash Memory” (Kunett, Baker and Fandrich, paper, title only).

NOR is the branch that kept byte-grain reads and became the code memory. NAND took the block and the capacity, which is the story in the memory map. From here on, this part follows NOR.

EEPROM in a microcontroller today

Microchip’s 24AAXX/24LCXX/24FCXX I2C family data sheet lists a write cycle of 5ms maximum for a byte or page write, with the erase included automatically, endurance of 1,000,000 erase/write cycles at 25°C (ensured by characterization and not tested), data retention above 200 years, and an automotive version rated from -40°C up to +125°C (Microchip, datasheet). Where a microcontroller has no EEPROM, vendors emulate one in flash pages. ST’s EEPROM emulation utility readme says the module emulates EEPROM in flash for applications that need non-volatile storage but have no dedicated EEPROM hardware, with power-loss recovery and optional cyclic redundancy check (CRC) and error correction codeError-correcting codes add parity bits to each block of data so the controller can find and fix bit errors on read. (ECC) (STMicroelectronics, vendor). Part 4 keeps the datasheet comparison of an EEPROM with ferroelectric memory.

Figure 1.1 lays the line out on one axis. Its marks are the dates the sources above give, and the row beneath each mark shows how much one erase clears. That is the whole chip under ultraviolet light, then one byte, then one block. NOR sits where Masuoka’s flash cell and Intel’s first NOR part meet, in 1984 and 1988 as Spectrum dates them, and NAND follows a year later. Every mark is a history value, and the 1988 mark rests on Spectrum and a paper title.

NOR and NAND at the pins, reads, writes and wear

Flash Foundations already teaches the NOR programming mechanism and why a NOR array needs a contact per cell. A system designer meets the consequence in four places. They are what random access buys, what NOR charges on the write side, how a modern NOR part and a modern NAND part from one vendor compare, and how long each lasts.

What the array decides

A NOR cell is programmed by hot electrons driven from source to drain and pulled onto the floating gate. It is erased by quantum tunneling that pulls them back out through the oxide. Renesas’s application note adds the part that matters for life. Current through the tunnel oxideThe tunnel oxide is the thin insulating layer between the channel and the charge-storage layer. Electrons cross it during program and erase, and it wears out. damages it with use (Renesas application note R10AN0038, application note). Flash Foundations Part 2 teaches the mechanism.

Size is decided by the array too. Micron’s technical note puts NAND cells at 4F² against 10F² for NOR, because each NOR cell needs a separate metal contact, and says NAND cells are 60% smaller (Micron TN-29-19, application note). Masuoka’s 1987 NAND paper reports, in its abstract, a NAND cell about 30% smaller in area per bit than a conventional EPROM at the same design rule (Masuoka et al., paper, abstract only). Those are two comparisons, one against NOR and one against an EPROM cell. Flash Foundations Part 3 teaches why.

What NOR gives and what it costs

Micron’s note gives random access time as 0.075µs for NOR and 25µs for the first byte of a NAND read, on the parts of its era. It says random access gives NOR its execute-in-place function, that NOR’s advantages are random access and byte write, and that a growing number of processors can boot straight from NAND, so execute in place stops being a consideration for those designs (Micron TN-29-19, application note).

NOR pays on the write side. A NOR part in the note’s comparison table writes 128µs per 32 bytes and sustains 0.250MB/s, and erases a 128KB block in about 1 second, where the NAND part sustains 7.5MB/s and erases in 500µs. Those tables also list a sustained read of 31MB/s (x8) or 62MB/s (x16) for NOR against 26MB/s or 41MB/s for NAND. Table 3 counts 44 pins for NOR’s random-access interface against 23 for the x16 NAND part, though the note’s text says 24 (Micron TN-29-19, application note). That note is revision B of April 2010, and its table compares a TE28F128J3 NOR with an MT29F2G08A NAND, parts of that era. Two Winbond parts from 2018 make a newer pair, and they come next.

The same split in two Winbond parts

Winbond’s W25Q128JV is a serial flash with 256-byte pages and 4KB sector erase (Winbond, datasheet). Its page program takes 0.4ms typical and 3ms maximum, a 4KB sector erase takes 45ms typical and 400ms maximum, a 64KB block erase takes 150ms typical and 2,000ms maximum, and a chip erase takes 40s typical and 200s maximum (Winbond datasheet, revision F, March 2018). The 0.4ms and 45ms figures are typical values, and the maxima are 3ms and 400ms. Winbond’s W25N01GV is NAND with 2KB pages and 128KB blocks, with a typical page program of 250µs and a typical block erase of 2ms (Winbond, datasheet).

Both parts are from one vendor, and both datasheets are 2018 revisions (F for the NOR part, L for the NAND part), so this pair is the newer comparison. The datasheet calls the W25Q128JV a serial flash memory and never says NOR, so treating it as the NOR half of the pair is the guide’s own reading. Its typical numbers show the same split as the old note. The NOR part programs a page in 0.4ms where the NAND part takes 250µs, and erases a sector in 45ms where the NAND part erases a block in 2ms. The Micron table and the Winbond pair are not combined in one ratio here, because they describe different eras and different parts.

Endurance and retention

Winbond’s W25Q128JV is rated for at least 100K program-erase cycles per sector, with more than 20 years of data retention (Winbond datasheet). Renesas defines retention as the time since the last write, typically 20 years for its products at a temperature of 85°C or lower, and says all its NOR devices except a single product support 100,000 program-erase cycles (Renesas application note R10AN0038, application note). Per Infineon’s NOR FAQ, retention is a typical 20 years after 10K program/eraseA program/erase cycle is one write of a block followed by its erase. Each cycle wears the oxide, and the cell type sets how many cycles it tolerates. cycles and 2 years after 100K, generally assuming a 55°C average temperature per JEDEC and counting from the last write, and the guaranteed values come from Infineon on request. It also says every sector or chip erase first pre-programs all bits to 0 automatically and then erases them to 1 (Infineon, vendor, knowledge-base article of December 13, 2017). Infineon’s Semper family page lists up to 2.56 million cycles of endurance and 25 years of data retention (Infineon, vendor, undated page).

Infineon’s FAQ puts retention at a typical 20 years after 10K cycles and 2 years after 100K, so ten times the cycling leaves a tenth of the retention (derived: 100K divided by 10K, 20 years divided by 2). The other specifications are given under their own conditions of cycling, temperature and product family, and none is a test of another vendor’s part.

Figure 1.2 puts the two comparisons side by side. On the left, from Micron’s note, NOR delivers its first byte in 0.075µs against 25µs, and sustains 0.250MB/s of writes against 7.5MB/s. On the right, from the Winbond pair, the NOR page program is 0.4ms against 250µs, and its sector erase is 45ms against 2ms. The left panel shows what NOR offers a code memory, and both panels show what it charges on the write side.

Execute in place and the logic in front of it

Execute in place (XIP) means the processor fetches instructions from the flash address range, with no copy to RAM first. NOR can do it because any byte can be read directly. The processor outruns the array, and buffers and caches in front of it hide the difference.

What execute in place needs

It needs random access, which is the 0.075µs against 25µs of the previous section (Micron TN-29-19, application note). It also needs the flash to answer fast enough to keep the processor busy, and that is where the trouble starts.

The processor outruns the array

NXP’s LPC178x/7x user manual sets the number of CPU clocks per flash access by the CPU frequency, with power boost off: 1 clock up to 20MHz, 2 up to 40MHz, 3 up to 60MHz, 4 up to 80MHz, 5 up to 100MHz, and 6 as the safe setting for any allowed condition. With power boost on, the 4-clock setting also serves 100 to 120MHz (NXP UM10470, user manual, revision 2 of September 17, 2012). At the top frequency of each of the five steps, the setting works out to 50ns per access (derived: 1 clock at 20MHz is 50ns, 2 clocks at 40MHz is 50ns, and so on to 5 clocks at 100MHz), and 4 clocks at 120MHz with power boost is about 33ns (derived). The guide reads the table as wait states growing with the clock while the array’s access time stays put. They are manual settings, with 6 clocks marked as the safe setting, and they are not measured access times. The 2012 revision of the manual is the one used, because it states the whole table.

Buffers and caches in front of the array

That manual also describes a flash accelerator with an array of eight 128-bit buffers. It prefetches as well, reading instructions from flash beyond the address the CPU is fetching. Buffers are invalidated at the start of any program or erase. The CPU is forced to wait if it touches flash while the flash is busy programming, which the manual warns can, under some conditions, cause a watchdog time-out (NXP UM10470, user manual). On NXP’s i.MX RT parts the Cortex-M7 core runs up to 600MHz with 32K/32K L1 instruction and data caches, and the FlexSPI block adds a 1KB receive prefetch buffer in front of external flash (NXP AN12437, application note).

How fast embedded flash reads

Renesas has published a run of figures for its 28nm embedded flash, and two of its releases disagree about the first. Its 2014 release says a 28nm prototype reached a 160MHz readout clock, with 20 years of data retention and 250,000 rewrite cycles for data storage (Renesas, vendor, February 18, 2014). Its 2015 release says Renesas had verified read operations at 160MHz in a prototype chip fabricated in the 40nm process. A year after the first release, Renesas reported 6.4GB/s of readout at over 200MHz and a write throughput of 2.0MB/s, on a prototyped 4MB program flash and 64KB data flash (Renesas, vendor, February 25, 2015). In June 2019 it reported 240MHz random-access read over junction temperatures from -40°C to 170°C on a 24MB test chip (Renesas, vendor, June 12, 2019). Between those, in March 2018, Renesas said it was sampling the RH850/E2x with up to six CPU cores at 400MHz and up to 16MB of flash (Renesas, vendor, March 27, 2018).

Of those, the 2014 and 2015 figures are prototype macros, the 2019 figure is a test chip, and the 400MHz is a product CPU clock. Because the 2015 release moves the 160MHz to the 40nm process, this part does not use it as the 28nm starting point, and it does not divide one figure by another to claim a wait-state count for any Renesas part, because the releases do not give one.

When the flash is off the chip

Raspberry Pi’s RP2040 is made on a 40nm process and has no flash on the die. Its datasheet calls it a stateless device with cached execute in place from external quad SPI (QSPI) memory, through a 16KB XIP cache that becomes ordinary SRAM when caching is switched off, and a 16MB window for XIP flash (Raspberry Pi RP2040 datasheet, datasheet). NXP’s i.MX RT parts execute in place from Hyper, Octal, QSPI or parallel NOR (NXP AN12437, application note).

Cars use the same arrangement, per Semiconductor Engineering. Application processors for driver assistance and high-end infotainment carry no embedded flash and use an external NOR chip on a bus. Without embedded flash a microcontroller needs a two-chip solution or a system-in-package. For the package route, Cypress’s Sam Geha said the part also has to survive high temperatures. The chip is 125°C, the die has to be at 150°C because it sits inside a package, and the package gets hotter by about 15°C (Semiconductor Engineering, trade, Geha quoted).

Figure 1.3 shows both halves. Left, the step rises with the CPU clock while the 50ns band stays flat, which is the wait-state arithmetic in one picture. In the right panel, the Renesas figures are not one measure. They are a 160MHz readout clock on a 2014 prototype that the 2015 release places on the 40nm process, a readout clock of over 200MHz on a 28nm prototype in 2015, a 240MHz random-access read clock on a 2019 test chip, and the 400MHz of the product CPU cores, which are different devices from different years. Both read clocks sit below the CPU clock. That panel shows why buffers and caches exist, though it shows no wait-state count.

Serial NOR, from SPI to xSPI

Serial NOR keeps execute in place over far fewer pins than the parallel interface in Micron’s note.

Why serial

Parallel NOR in Micron’s note needs a 44-pin random-access interface (Micron TN-29-19, application note). A serial part uses fewer. Winbond’s W25Q128JV datasheet lists CLK, /CS and the data pins IO0 to IO3 for quad SPI, and the part keeps execute in place with a continuous read mode that needs as few as 8 clocks to address memory, which the datasheet says allows true XIP (Winbond datasheet).

Lanes and clock

Winbond’s W25Q128JV runs a 133MHz clock, with equivalent rates of 266MHz for dual and 532MHz for quad I/O, and a 66MB/s continuous transfer rate (Winbond datasheet). Only simple arithmetic is needed: 133MHz moves 133Mb/s on one data lane, 266Mb/s on two and 532Mb/s on four, which is 16.6MB/s, 33.3MB/s and 66.5MB/s (derived: the clock in MHz times the lanes, divided by 8). Four lanes match the datasheet’s 66MB/s.

What JEDEC calls xSPI

JEDEC’s JESD251 defines the eXpanded Serial Peripheral Interface (xSPI) for nonvolatile memory devices. Infineon’s conformance note says it standardizes the 1S-1S-1S and 8D-8D-8D protocols, with Profile 1.0 at 32-bit addressing and Profile 2.0 at 45-bit addressing, and that an addendum to the standard adds a 4-bit bus width that its QSPI devices meet (Infineon knowledge-base article, vendor, September 26, 2019). JEDEC’s JESD251D page says the interface is meant for nonvolatile memory with high throughput and low signal count, has limited backward compatibility with legacy SPI, and that its electrical interface can deliver up to 400MB/s raw (JESD251D, standard, abstract only, and the document is a free download that needs registration). Sources disagree on when the standard was ratified, so no year is printed.

Where the parts go

Infineon’s Semper family lists xSPI (Octal and HyperBus) and QSPI interfaces at 512Mb to 2Gb, AEC-Q100 qualification, error correction code, up to 2.56 million cycles and 25 years of retention (Infineon Semper page, vendor). Winbond’s part is rated for 100K cycles per sector (Winbond datasheet). Both the RP2040’s 16MB XIP window and the i.MX RT list of supported memories show what a controller expects to find behind the interface.

Figure 1.4 sets the lane arithmetic beside the interface limit. Bars one to three are derived from one datasheet clock and double with each added lane. Bar four is JEDEC’s raw figure for the xSPI electrical interface. It is the interface’s limit, and no listed part is shown to reach it, so the bars carry different tags.

Why embedded flash stopped fitting

A microcontroller keeps its firmware in a block of memory on the same die as the processor. Infineon and TSMC describe embedded flash as the base of most microcontroller families on the market. Mostly trade quotes and vendor releases, plus a line each from two IRDS editions, are the sources for why it stopped scaling, so every sentence names its outlet.

Embedded flash is a family

Floating-gate flash from Silicon Storage Technology (SST), a Microchip subsidiary, stores charge in the gate. Charge-trap cells from Cypress and Renesas store charge in the nitride layer of a stack. NXP and Infineon have other embedded technologies (Semiconductor Engineering, trade). Renesas calls its cell SG-MONOS, after the metal-oxide-nitride-oxide-silicon stack, and its 2019 release says the 28nm generation shrank the cell from 0.053µm² to under 0.045µm² (Renesas, vendor).

What the cell adds to a logic process

Embedded flash is added to a logic process with extra masks. Geha told Semiconductor Engineering that adding embedded flash is very expensive. At 40nm it generally needs 8 to 12 or 13 extra masks over CMOS, and at 28nm 9 to 18 (Semiconductor Engineering, trade, Geha quoted). GlobalFoundries and Microchip said on September 27, 2023 that SST’s ESF3 SuperFlash went into production on GF’s 28SLPe process with 10 masks added, a 0.04µm² bitcell, operation from -40°C to 125°C, read access under 25ns, 10µs program, 4ms erase and endurance above 100,000 cycles, in macros of 4Mb to 32Mb (GlobalFoundries and Microchip, vendor). Those are an executive’s figures for embedded flash in general and a vendor’s figure for one cell on one process. They are stated separately and are not combined into a range.

The 28nm wall

Handy said that no one had yet figured out how to make NOR processes smaller than 28nm. Geha said the cells work fine at 40nm, can work at 28nm though it becomes more complicated, and do not work below that because they cannot be integrated with finFETs. It reports that embedded flash was expected to scale to 28nm and perhaps 22nm, while standalone leading-edge NOR was at 45nm with 32nm and 28nm in research (Semiconductor Engineering, trade, Handy and Geha quoted, July 19, 2018).

SemiWiki’s account shows how long the 28nm step took. It reported in September 2016 that Renesas and TSMC were working on 28nm embedded flash (eFlash) for microcontrollers, that the announcement expected samples in 2017 and full production in 2020, which the article said would be eight years after the 40nm node went to production, and that once reliability goals were met 28nm would raise program memory capacity 4 times over 40nm (SemiWiki, trade). Renesas said in March 2018 that it was sampling what it called the first 28nm on-chip flash microcontroller (Renesas, vendor claim). IRDS 2023’s mass data storage text says embedded NOR flash used for code storage has reached a scaling limit at 28nm (IRDS 2023, roadmap). Infineon and TSMC said in November 2022 that most microcontroller families on the market were based on embedded flash and that AURIX TC4x samples then shipping used TSMC’s 28nm eFlash (Infineon and TSMC, vendor).

Two chips instead of one

When a controller moves to a node without embedded flash, the code goes to an external NOR beside it, as the RP2040 and the automotive processors above do. Semiconductor Engineering adds that the two-chip route gives some flexibility to use chips from several vendors, and that it takes up board space, consumes more power and adds some potential latency and security issues (Semiconductor Engineering, trade).

What the die turned to

The sources name several replacements, and each family has its own part later in the series. IRDS 2022 sees spin-transfer-torque MRAM (STT-MRAM) as a possible replacement for embedded NOR in low-power Internet of Things (IoT) parts, and says NOR is expected to keep dominating higher-density embedded code because it is still substantially more cost-effective (IRDS 2022, roadmap). TSMC’s page says its embedded resistive RAM (RRAM), offered as an alternative to eFlash, is in high-volume production at 40nm, 28nm, 22nm and 12nm, and that its 22nm and 16nm embedded MRAM have passed AEC-Q100 automotive qualification (TSMC, vendor, undated).

Samsung announced on March 6, 2019 that it had begun mass production of embedded MRAM on a 28nm fully depleted silicon-on-insulator (FD-SOI) process and that writing is roughly a thousand times faster than eFlash because MRAM needs no erase (Samsung, vendor claim). NXP’s release of March 11, 2025 says its S32K5 pairs 16nm FinFET with embedded MRAM, with writes to its MRAM more than 15 times faster than to embedded flash, and plans to begin sampling to lead customers in Q3 2025 (NXP, vendor claim, sampling a plan).

Infineon’s AURIX TC4xx comes in flash and RRAM forms. Its knowledge-base article says program memory in both targets 20-year retention with endurance up to 1,000 program cycles, data memory targets up to 250,000 cycles, a flash cycle is erase plus program while an RRAM cycle is program only, and flash logical sectors are 16KB (Infineon, vendor, September 9, 2026). ST said it was sampling 28nm FD-SOI microcontrollers with embedded phase-change memory, meeting AEC-Q100 Grade 0 requirements with operation up to +165°C, and with firmware retention through high-temperature soldering reflow (ST, as relayed by SEMI, vendor, undated copy), and its Stellar SR6 release of June 16, 2021 says the first parts have up to 20MB of phase-change memory and a dual-image mode that holds two 20MB images for updates, with access faster than 1T NOR flash (ST, vendor claim). Part 2 follows ST’s account, Part 3 the MRAM parts and Part 5 the resistive ones.

Figure 1.5 sorts the releases by date. Embedded flash is on the top lane from the first Renesas 28nm release in 2014 to the 28nm ESF3 production release in 2023, and the replacements sit on the lower lane from 2019 to 2025. Both lanes overlap for years, and flash was still being announced at 28nm while vendors were announcing MRAM at 28nm and 16nm. This figure records what vendors announced and says nothing of what shipped in volume, and the March 2025 mark is a stated sampling plan.

The soldering test, the car grades and the update

A code memory has to pass four tests. It must survive the solder oven, meet its temperature grade, pass the qualification bakes and take a field update.

The soldering test

A microcontroller is soldered to its board and its code has to come out intact. IRDS 2022 says flash is well established for enduring board soldering at about 250°C without losing its preloaded code, which many emerging memories had not yet been able to demonstrate, and it says phase-change alloys made compliant with reflow gave up write speed (roadmap). Restating the IPC/JEDEC J-STD-020 classification, Texas Instruments’ restatement has a peak reflow classification of 260°C for packages under 1.6mm thick, and 260°C, 250°C or 245°C for packages 1.6mm to 2.5mm thick by volume, from small to large. Above 2.5mm the values are 250°C, 245°C and 245°C. That profile ramps from liquidus to peak at no more than 3°C per second and should take no more than 8 minutes from 25°C to peak (Texas Instruments SPRABY1A, vendor relay of a standard, December 2018). IRDS’s 250°C and the standard’s classification are separate statements, and neither is “the” reflow temperature.

What a car grade asks

AEC-Q100 Rev J, dated August 11, 2023, defines the temperature grades by ambient operating range: Grade 0 is -40°C to +150°C, Grade 1 is -40°C to +125°C, Grade 2 is -40°C to +105°C and Grade 3 is -40°C to +85°C (AEC-Q100 Rev J, standard). High-temperature operating life runs 1,000 hours at an ambient 150°C for Grade 0, 125°C for Grade 1, 105°C for Grade 2 and 85°C for Grade 3. Devices that contain nonvolatile memory (NVM) must be endurance-preconditioned per AEC-Q100-005 first, and the NVM endurance, data retention and operational life test is B3, run on 77 devices from each of 3 lots (AEC-Q100 Rev J, standard).

UMC’s David Uriu, quoted by Semiconductor Engineering in 2018, listed solder reflow, high reliability and a shelf life above 20 years as the bar an emerging memory for automotive microcontrollers has to clear, and said Grade 0 requires 150°C. The article itself put STT-MRAM temperature specifications at the time at 85°C to 105°C (Semiconductor Engineering, trade, Uriu quoted). ST’s embedded phase-change memory, told above, is stated at Grade 0 with operation up to +165°C. The AEC range for Grade 0 is -40°C to +150°C ambient. The 165°C is ST’s statement.

How retention is qualified

In AEC-Q100-005, an NVM is qualified by first preconditioning the device with program/erase cycling. High-temperature cycling runs at 85°C or above with the total cycling time at most 15% of the accelerated product life, and low-temperature cycling runs at 55°C or below. Low-temperature retention storage then runs at a maximum of 55°C for at least 1,000 hours. It keeps the high and low flows separate because some degradation heals with temperature (AEC-Q100-005 Rev D1, standard, January 9, 2012). Error correction and on-chip wear levelingWear leveling spreads erases evenly over all blocks. Dynamic leveling picks young blocks for new writes, while static leveling also moves cold data off them. must be disabled during endurance cycling so that every cell is stressed, although for very large or deeply scaled arrays, or parts built with ECC, the supplier may ask the user’s approval to cycle with ECC active and then supply bypass data. With user approval a reduced array may be tested if it receives no fewer than the maximum specified cycles (AEC-Q100-005, standard).

Appendix B converts a mission profile into an equivalent bake with the Arrhenius form tu = t·exp[Eaa/kB·(1/Ts-1/Tu)]. Here t is the use time in hours at a use temperature Tu, tu is the equivalent stress time at the bake temperature Ts, both temperatures are in kelvin, Eaa is the activation energy, 1.1eV in the example, and kB is Boltzmann’s constant in eV/K. Its example table turns 131,400 hours of use at several temperatures into 453 hours at 150°C, or 84 hours at 175°C (AEC-Q100-005, standard). That is 15 years compressed by about 290 times (derived: 131,400 divided by 8,760, and 131,400 divided by 453), and recomputing the table’s rows with the stated formula gives about 455 hours, within 1% of the table (derived). Retention figures from the NOR section come back here. Retention is counted from the last write, and it depends on the cycles and the temperature (Infineon NOR FAQ; Renesas application note R10AN0038).

The update needs two copies

NXP’s LPC178x manual says its flash allows no access during program and erase, and the Infineon material below makes the same statement for a single bank. Infineon’s AURIX TC3xx documentation says software over the air splits the program flash into two groups of banks, A and B. One group is read and executed while the other is written, and when the update completes only the address mapping is swapped, so no data is copied and the executed address range stays the same. Read-while-write is not supported within a single physical bank (Infineon AURIX TC3xx documentation, documentation, describing the TC375). A knowledge-base article of October 10, 2024 says the same for the family, that read-while-write works across banks and is unsupported within a single program flash bank (Infineon, vendor).

Others do it in their own way. Renesas’s 2019 test chip divides its code flash into a storage area for the software in use and one for the updated software, and says it can switch between them in under 1ms at ignition off (vendor, June 12, 2019). ST’s Stellar SR6 does it with the dual-image mode described above. Infineon’s TC4xx pairs host program banks when over-the-air update is supported (knowledge-base article, vendor).

How long an update takes

Three numbers size the effect. Writing 20MB at the 0.250MB/s sustained write of the NOR part in Micron’s note would take 80 seconds. Writing 24MB at the 6.5MB/s that Renesas’s 2019 test chip programs in its high-speed write mode would take about 3.7 seconds. NXP said with TSMC on May 16, 2023 that its automotive embedded MRAM can update 20MB of code in about 3 seconds against about a minute for flash, with up to one million update cycles, solder reflow support and 20-year retention at 150°C, which implies about 6.7MB/s (derived, NXP, vendor claim). These are three different devices from different decades, so they size the effect and do not rank products. Part 3 holds the MRAM account.

Figure 1.6 shows two of those requirements. Left, the reflow band sits above every grade maximum, so a Grade 0 part still has to come through a hotter excursion on the way to the board. Right, one group of banks keeps executing while the other is written, and the swap changes only the address map, so an update does not stop execution.

Part 2 takes the next family, phase-change memory.