eMMC Explained: The Flash Storage Inside Cheap Devices

Storage in a budget tablet, a smart TV or a car’s infotainment unit is usually eMMCAn eMMC is managed NAND flash for mobile applications: flash memory and its controller in one embedded memory system. Its parallel interface sends data one direction at a time., short for embedded MultiMediaCard. In JEDEC’s definition it is flash memory and a flash controller in one package, so the host processor never has to manage raw NAND. Phones used it before UFS, and it still sells wherever a few hundred megabytes per second is enough.

Part 1, UFS Explained, set eMMC beside UFS and NVMe in one section. This part takes eMMC on its own terms. It covers what the eleven wires of its bus do, why its speed stops at 400MB/s, what the partitions and registers inside a part are for, and what a maker’s datasheet promises against the standard’s limits.

JEDEC sells the standard to non-members, so the figures here come from its public pages and releases, from the Linux kernel, and from the makers’ own datasheets. A maker’s rating is that maker’s claim.

eMMC puts the controller in the package

eMMC takes its name from a removable card. According to SanDisk’s 1998 annual report, SanDisk and Siemens introduced the MultiMediaCard in November 1997 as a small card with a simple serial interface for mobile devices, and SanDisk was a founding member of the MultiMediaCard Association (MMCA) that kept the format. Its soldered successor kept the card’s protocol. Samsung dates the eMMC standard to 2006, when JEDEC and the MMCA developed it together. Both bodies then worked on versions 4.2 and 4.3, and in September 2008 the MMCA’s e-MMC specifications moved into JEDEC, which has maintained them since.

Inside the package, a controller does the work that an SSD controller does. Kioxia’s e-MMC product brief puts error correction, wear leveling, logical-to-physical address translation and bad-block management inside the one ball grid array (BGA) package. By the standard’s terms eMMC is managed memory with indirect access to the array. It runs its own background management, and the host’s flash layer stays simple. A host reads and writes logical blocks, as it would on an SSD, and never sees a NAND page or a bad block.

That separates eMMC from the raw NAND a board would otherwise carry. A processor with a raw NAND interface needs its own error correction and wear leveling in software, and every new NAND generation means new driver work. With eMMC, the NAND can change from one part number to the next while the host sees the same interface. How NAND stores a bit and why it needs that management is in Flash Foundations.

Eleven wires carry the whole eMMC bus

An eMMC bus is parallel. The eMMC 5.1 standard, JESD84-B51, gives it eleven bus wires and a hardware reset. The eleven are a clock (CLK), a command line (CMD), eight data lines (DAT0 to DAT7) and a data strobe (DS), and the reset line (RST_n) sits beside them. Commands and their responses travel one bit at a time on CMD, while data moves over one, four or eight data lines at once. A device starts in one-bit mode, and the host widens the bus to four or eight bits after it has read what the device supports.

Reads and writes share the data lines and take turns on them. During a write the host drives the lines, and during a read the device drives them, so the bus never carries both at the same moment. UFS works differently, because its serial lanes give each direction its own path. Only HS400 uses the strobe. In HS400 the device generates the strobe for data it sends, and the host samples the read data on its edges.

Two supplies feed a part. A core supply (VCC) powers the NAND at 2.7 to 3.6V, and an I/O supply (VCCQ) powers the interface at 1.70 to 1.95V or 2.7 to 3.6V, with a 1.1 to 1.3V range also defined. That choice limits speed, because the standard does not allow the 200MHz modes at a 3.3V VCCQ. Any board that runs its eMMC I/O at 3.3V tops out at the 52MHz modes.

Bus speed modes from 26 to 400MB/s

Each step up in eMMC speed raised the clock or used both of its edges. Five modes appear in the standard’s bus speed table, each assuming the full eight-bit bus. Legacy mode clocks at up to 26MHz and moves 26MB/s. High Speed raised the clock to 52MHz for 52MB/s, and its double data rate (DDR) variant moves data on both clock edges for 104MB/s. HS200 runs single data rate at 200MHz for 200MB/s, on a four- or eight-bit bus. HS400 runs double data rate at 200MHz for 400MB/s, on the eight-bit bus only. It first appeared in JESD84-B50 for eMMC 5.0, at 1.8V.

Figure 3 shows the rate climbing from 26MB/s to 400MB/s in four steps and then stopping. Each data line carries one bit per clock edge, so 8 lines × 200MHz × 2 edges / 8 bits per byte = 400MB/s, the HS400 maximum. Going faster on a parallel bus means either a faster clock, which makes the eleven wires harder to keep in step, or more data lines, which means more balls and more board routing. JEDEC did neither and moved phones to UFS instead.

HS200 and HS400 also need the host to find the right moment to sample the data. At 200MHz, delay along the board traces is a large part of a clock period, so the host runs a tuning sequence to learn where each data bit is stable. eMMC 5.1 added Enhanced Strobe, an optional mode in which the device supplies the strobe for command responses too. With it, a host can enter HS400 without the tuning step. A part reports support in byte 184 of its extended register set (EXT_CSD), which the Linux kernel’s MMC header names STROBE_SUPPORT.

How eMMC grew, version by version

Version numbers describe the protocol and the bus, not the flash inside. JEDEC published eMMC 4.4 on April 14, 2009, with a doubling of interface performance, flexible partition management and improved security options. On May 6, 2010, version 4.41 added the high priority interrupt and host-controlled background operations.

On June 15, 2011, eMMC 4.5 raised the interface from 104MB/s to 200MB/s with HS200. It also added packed commands, which group several reads or several writes into one transfer. Version 4.5 also brought a provision for a volatile data cache, power-off notification and Dynamic Device Capacity. eMMC 5.0 followed on October 1, 2013, with HS400 and its 400MB/s.

Command queueing arrived with eMMC 5.1 on February 24, 2015, where every earlier version ran one command at a time. No later version added a feature of that size. JEDEC’s standard page lists 5.1A in January 2019, and 5.1B in September 2025, which replaces all past versions. No speed mode has come since 5.0, so a part sold today as eMMC 5.1 runs at the same 400MB/s maximum as a 2013 part.

Partitions an eMMC device carries

An eMMC device is not one flat block of storage. Its standard divides it into partitions, each with its own job, and the host switches between them with a register write instead of an address offset. Two boot partitions, each sized in multiples of 128KB, hold the code a system loads first. During the defined boot modes, a device streams their contents to the host as soon as it powers up, before any driver has loaded.

A replay protected memory block (RPMB) is a small partition for data that must not be rolled back, such as a counter that stops an attacker restoring an old firmware image. An authentication key is programmed into the device once, and every read and write to the RPMB carries a message authentication code that the device checks. Below these, the host can set up to four general purpose partitions and one enhanced segment of the user data area, defined by a start address and a size.

Those host settings are one-time programmable. A maker sets the boot and RPMB sizes at the factory, and the host gets one chance in the device’s life to set the general purpose partitions and the enhanced area. The standard leaves the meaning of “enhanced” to the system maker, and in practice it marks more reliable storage. In Kioxia’s 2023 release, setting its whole e-MMC area as enhanced gave a 3.3 times improvement in terabytes written (TBW), at the cost of user capacity. Kingston sells its EMMC32G-TS0A-01002 factory configured in pseudo-SLC (pSLC) mode for the same reason.

Linux shows the partitions as separate devices. In the kernel’s documentation, the two boot partitions are /dev/mmcblkXboot0 and /dev/mmcblkXboot1, read-only by default because they often hold the bootloader. Writing them by mistake can leave a board that no longer starts.

Command queueing arrives in eMMC 5.1

Before version 5.1, an eMMC device took one command at a time. Without a command queue, Samsung explains, a device has to wait for one process to finish before the next begins. A phone loading an app while it saved a photo had to put the two in a line.

eMMC 5.1 splits a command into queueing and running. First the host sends CMD44 with a task’s parameters and CMD45 with its address, and the device adds the task to its queue. Later, the host runs any queued task with CMD46 for a read or CMD47 for a write. A 32-bit Queue Status Register shows which tasks are ready. Each device reports its queue depth in EXT_CSD byte 307, and the standard allows up to 32. UFS had the same 32 before its multi-circular queue arrived, as Part 1 covers in How UFS queues commands.

Command queueing is optional in 5.1, so a part labeled 5.1 may not have it. Kioxia’s 2023 parts support command queueing and secure write protection, both of which the standard leaves optional. Only a datasheet that names command queueing in its feature list, as Kingston’s does, settles the question.

Most of the rest of the 5.1 feature set keeps a part healthy in a device nobody services. A high priority interrupt lets the host stop a long write so that an urgent read, such as a page the operating system needs, can run first. An optional volatile cache holds writes before they reach NAND. Field firmware update lets the host load new controller firmware in a finished product and tell the device to install it.

Data removal has four commands. Erase and Trim free blocks, Discard tells the device it may drop write blocks, and Sanitize physically removes data from the unmapped part of the user area and holds the device busy until it is done. Older Secure Erase and Secure Trim are kept only for compatibility, and new designs on 4.51 and later are told to pair Erase or Trim with Sanitize instead.

Health registers tell the host how worn a part is. Byte 267 of EXT_CSD reports the state of the reserved blocks, with 01h for Normal, 02h for Warning once 80% of them are used, and 03h for Urgent. Bytes 268 and 269 estimate life used in 10% steps, from 01h for 0 to 10% up to 0Ah for 90 to 100%, with 0Bh once the estimated life is exceeded. Linux names them PRE_EOL_INFO and DEVICE_LIFE_TIME_EST in its MMC header, so a script can read them from a running board.

Real parts against the 400MB/s limit

An eMMC datasheet rates sequential reads and writes measured inside the part, and every rating sits below the bus limit. Samsung announced eMMC 5.1 in 16GB, 32GB and 64GB, with the 64GB part rated up to 250MB/s sequential read and 125MB/s sequential write, and 11,000 random read and 13,000 random write IOPS. Kingston rates its 32GB EMMC32G-TS0A-01002 at 310MB/s read and 200MB/s write in HS400.

Small parts are much slower. Kingston’s 8GB EMMC08G-ML36-01B00 is rated 115MB/s read and 20MB/s write, a tenth of the 32GB part’s write rate on the same bus. SK hynix’s automotive eMMC 5.1 datasheet shows the same pattern, from 25MB/s write and 200MB/s read at 8GB up to 100MB/s write and 250MB/s read at 32GB and 64GB. A device built with the smallest capacity in a range gets the slowest storage in it, whatever the box says about eMMC 5.1 and HS400.

Most packages share one footprint. Samsung’s eMMC 5.1 comes in a 153-ball package of 11.5 × 13 × 0.8mm in capacities from 8GB to 256GB. Kioxia’s brief gives the same 11.5 × 13mm 153-ball package, with an 11 × 10mm option for 4GB, a lineup from 4GB to 128GB, and a 400MB/s maximum on its BiCS FLASH parts. Kingston’s 32GB part measures 11.5 × 13.0mm with a 1.0mm maximum height. A shared footprint lets a board maker choose between suppliers without a new board.

Controllers come from flash makers and from independent designers. In Silicon Motion’s company profile, two eMMC 5.1 controllers are in mass production, the SM2730 and the SM2738, each with one NAND channel and two chip enables. A 4KB low-density parity-check (LDPC) code protects data on the SM2738, where the SM2730 uses a 1KB one.

Why makers still sell eMMC

eMMC stopped gaining features in 2015, but it did not stop selling. Kioxia’s e-MMC page gives two reasons it stays. Some products need lower densities than UFS offers, and some processors have no UFS interface. Its product brief draws the line in numbers, with eMMC for 4GB, 8GB and 16GB, and UFS for 32GB to 1TB or any design that needs more speed.

Lists of where eMMC goes are long. Kioxia names IoT devices, smart TVs, tablets and 2-in-1s, automotive, streaming media and smart speakers, and its 2023 release adds personal computers, point of sale devices, handhelds and network cards as the rest of the market moves to UFS 4. Phison names e-readers, digital cameras, digital TVs and set-top boxes for its eMMC, and SK hynix lists infotainment and driver assistance (ADAS) in cars. Kioxia began sampling new 64GB and 128GB eMMC 5.1 parts in September 2023, with mass production planned for 2024, and claimed 2.5 times the write and 2.7 times the random read speed of its previous generation.

Boards built for robots and edge computers use it too. NVIDIA’s Jetson AGX Orin carries 64GB of eMMC 5.1 next to its LPDDR5.

Laptops are the other place eMMC turns up. Google’s Chromebook Plus program requires at least 128GB of storage, and PCMag reported that eMMC, UFS or an SSD can meet it. A Chromebook Plus label says how much storage a laptop has, not which kind, so the spec sheet is the place to check whether it is eMMC, UFS or an SSD.

What to watch as UFS takes over

Samsung’s comparison is the one that moved phones to UFS. In its own tests, its UFS 2.0 reached 1.40 times the sequential read of its eMMC 5.0, 1.66 times the sequential write, 2.71 times the random read and 1.07 times the random write. Random reads gained most and random writes least.

eMMC has no newer version to wait for. JEDEC’s September 2025 revision is still numbered 5.1, and it keeps the 2015 feature set current instead of adding a faster mode. How many products keep eMMC is the open question. Kioxia puts the boundary at 4GB to 16GB, and every processor family that gains a UFS controller moves it for the devices built on that family. Until then, a buyer reading a spec sheet has three numbers worth checking: the eMMC capacity, because the small parts write at a fraction of the large ones, the maker’s rated write speed, and whether the part names command queueing.

Part 3 of Flash in Devices turns to SD and microSD cards and the speed labels printed on them. Part 5, Flash in Phones and Tablets, covers how eMMC and UFS are packaged with a phone’s LPDDR memory.