Bit Market · Sourced milestones
Photon Fabric
Optics for memory and storage, as a record of progress: the first designs for DRAM wired with light, the chiplets that put optics in the package, SSDs with an optical port, and the co-packaged switches that show the same optics at scale. 15 milestones from 2008 to 2026, each linked to the paper or release it comes from.
Chart of optical link bandwidth by year
Optical links to memory went from 2Tb/s in 2020 to 8Tb/s in 2025
- Record: the fastest optical link to memory shown working by then
- Hollow: a paper’s design target, not a measurement
- Optical links to memory
- SSDs with an optical port
- Co-packaged optics switches (context)
3 records, oldest first. Each one is hardware that moved more data over light than any earlier link to memory shown working.
3/2020
2Tb/s
- Who
- Intel and Ayar Labs
- Stage
- Lab demo
11/2023
4Tb/s
- Who
- Ayar Labs and Intel
- Stage
- Lab demo
8/2025
8Tb/s
- Who
- Ayar Labs
- Stage
- Lab demo
How to read it
This page is called Photon Fabric. It is not Photonic Fabric, the optical interconnect Celestial AI built and Marvell now owns; rows about that product name it and its maker.
Each row is a milestone: a part shown at one stage of its progress, from a paper that designs it, to a lab demo with a measured number, to sampling and shipping. The page holds 15 milestones from 15 public sources, 5 of them papers. A row sits at the date its own source prints, to the month at least; a paper is dated by its conference or submission month.
The chart plots the optical bandwidth of one chip, module or switch in terabits per second, on a log scale, where each gridline step multiplies the value. The record line follows only hardware shown working on a link to memory. A paper’s design target is a plan, not a result, and a switch moves network traffic rather than memory, so both sit on the chart for scale without setting a record. Energy per bit is in the table, where lower is better.
Every number is the figure the source states, with its unit. A value marked derived was worked out from what the source states, such as terabytes per second turned into terabits, or watts divided by bits per second. Sources are the makers and the journals themselves; news sites and trade press can point to a milestone, but the row cites the primary page.
Every milestone and its source
Newest first. The Lane chips above filter this table and the chart together.
- means the source does not state this figure.
- D Derived: worked out from what the source states (a unit change, or one figure divided by another), not printed by it.
Tap any column heading to sort the table by it. Tap it again to reverse the order.
| Milestone | Who | Lane | Stage | Date | Link bandwidth | Energy per bit | Source | Note |
|---|---|---|---|---|---|---|---|---|
| A Photonic-CXL Memory Appliance for Scalable KV Cache Management in LLM Inference | Jing Ding and colleagues (Marvell) | Optical links to memory | Paper | 7/2026 | 7.2Tb/s | not published | arXiv preprint 2026 paper | Preprint by Marvell engineers. Optics give 16 hosts 32 TB of shared memory with no switch; emulation shows over 50 percent lower latency than an electrical CXL pool. |
| NVIDIA Spectrum-X Ethernet Photonics Ramps to Production | NVIDIA | Co-packaged optics switches (context) | Shipping | 6/2026 | not published | not published | NVIDIA 2026 release | Context: networking, not memory. The co-packaged optics switch is in full production, with CoreWeave, Lambda and Oracle Cloud among the first adopters. |
| Broadcom Announces Tomahawk 6 Davisson, the Industry’s First 102.4-Tbps Ethernet Switch with Co-Packaged Optics | Broadcom | Co-packaged optics switches (context) | Sampling | 10/2025 | 102Tb/s | not published | Broadcom 2025 release | Context: Broadcom’s third co-packaged optics switch, 200 Gb/s per link, double Bailly’s line rate. Sampling to early access customers; a 70 percent cut in optics power, no watts per bit given. |
| Let’s Get Serious: TeraPHY Optical Engine Passes the Test for AI Scale-Up at Volume | Ayar Labs | Optical links to memory | Lab demo | 8/2025 | 8Tb/s | not published | Ayar Labs 2025 release | The third TeraPHY generation after 2 and 4 Tbps, and the first UCIe optical retimer chiplet; it has finished engineering validation testing. |
| Photonic Fabric Platform for AI Accelerators | Jing Ding and Trung Diep (Celestial AI) | Optical links to memory | Paper | 7/2025 | 7.2Tb/s | not published | arXiv preprint 2025 paper | Preprint by Celestial AI engineers. HBM3E, an on-module photonic switch and external DDR5 in one package give up to 32 TB of shared memory and 115 Tbps of switching. |
| Kioxia, AIO Core and Kyocera Announce Development of PCIe 5.0-Compatible Broadband Optical SSD for Next-Generation Green Data Centers | Kioxia, AIO Core and Kyocera | SSDs with an optical port | Lab demo | 4/2025 | not published | not published | Kioxia 2025 release | A prototype that works at PCIe 5.0, twice the bandwidth of the 2024 PCIe 4.0 one. Part of the NEDO green data center project JPNP21029. |
| NVIDIA Announces Spectrum-X Photonics, Co-Packaged Optics Networking Switches to Scale AI Factories to Millions of GPUs | NVIDIA | Co-packaged optics switches (context) | Announced | 3/2025 | 400Tb/s | not published | NVIDIA 2025 release | Context: networking, not memory. Up to 512 ports of 800Gb/s (400Tb/s); NVIDIA claims 3.5x better power efficiency with 4x fewer lasers. |
| Broadcom’s journey to CPO at scale: performance KPIs & fiber reliability | Broadcom | Co-packaged optics switches (context) | Lab demo | 10/2024 | 51.2Tb/s | 6.25pJ/bit, derived | Broadcom 2024 release | Context: Broadcom’s co-packaged optics switch, 5 W of optics power per 800 Gb/s including the laser, 60 to 70 percent below a DSP-based transceiver. |
| Kioxia Develops Broadband SSD with Optical Interface for Next-Generation Green Data Centers | Kioxia | SSDs with an optical port | Lab demo | 8/2024 | not published | not published | Kioxia 2024 release | A prototype shown at FMS 2024. Light in place of copper lets storage sit farther from compute, toward disaggregated systems. |
| Ayar Labs Showcases 4 Tbps Optically-enabled Intel FPGA at Supercomputing 2023 | Ayar Labs and Intel | Optical links to memory | Lab demo | 11/2023 | 4Tb/s | ≤5pJ/bit | Ayar Labs 2023 release | Two TeraPHY chiplets of 4 Tbps each on an Intel Agilex FPGA fabric die, at under 5 pJ/b and 5 ns per chiplet. |
| PIPES Researchers Demonstrate Optical Interconnects to Improve Performance of Digital Microelectronics | Intel and Ayar Labs | Optical links to memory | Lab demo | 3/2020 | 2Tb/s | not published | Ayar Labs 2020 release | An Intel FPGA with Ayar Labs’ TeraPHY optical chiplet in its package. Ayar says the first TeraPHY came from DARPA POEM, a processor to DRAM optics program. |
| Intel Demonstrates Industry-First Co-Packaged Optics Ethernet Switch | Intel | Co-packaged optics switches (context) | Lab demo | 3/2020 | 1.6Tb/s | not published | Intel 2020 release | Context: 1.6 Tbps silicon photonics engines in the package of a 12.8 Tbps Barefoot Tofino 2 switch. |
| Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics | UC Berkeley and MIT | Optical links to memory | Paper | 6/2010 | not published | not published | ISCA 2010 2010 paper | A design study that rebuilds the DRAM chip and its channel around photonic links running 10 Gb/s per wavelength. |
| Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics | MIT and UC Berkeley | Optical links to memory | Paper | 8/2008 | not published | 0.25pJ/bit | Hot Interconnects 2008 2008 paper | A design study for photonic links between a manycore processor and DRAM, built in standard CMOS. The energy per bit is projected, not measured. |
| Corona: System Implications of Emerging Nanophotonic Technology | HP Labs and University of Wisconsin | Optical links to memory | Paper | 6/2008 | 80Tb/s, derived | not published | ISCA 2008 2008 paper | A design study for a manycore chip with optically connected memory, aiming at 10 TB/s of off-stack memory bandwidth for a 10 teraflop processor. |
- Optical links to memory. Light between a processor and its memory: from design studies to chiplets in the package.
- SSDs with an optical port. Drives that swap the copper host link for light, so storage can sit farther from compute.
- Co-packaged optics switches (context). Network switches with the optics in the package. They carry no memory; they show what the same optics do at scale.
What it will not tell you
This is a record of milestones with a dated public source, not a market map. A company that has shown nothing in public is not here, a prototype is not a product, and a deal or a revenue target is not a milestone, so acquisitions are left off. Fibre Channel, storage’s long-running optical link, waits for a source that dates each speed to the month.
A paper or a release written by a company’s own engineers describes that company’s part under the tests they chose. For how memory and flash work underneath, see Flash Foundations and Beyond NAND. For flash and memory in robots, see Cogs and Cache; in space and SI datacenters, Signals; and for the makers’ results each quarter, the Earnings Desk.