Storage and Memory in Practice, Part 1: DDR5 for Builders

AMD’s AM5 processors and Intel’s 12th, 13th, and 14th generation and Core Ultra 200S desktop chips all run DDR5 memory. A kit’s label packs most of what a builder needs into one line, with a data rate, a set of timings, a voltage, and a profile name. This guide explains those numbers, sets out what each platform officially supports, and walks through the memory problems that stop a new build from booting or staying stable, with checks for both Windows and Linux.

The speed on the box is rarely a speed the processor promises. AMD rates the Ryzen 9 9950X3D for DDR5-5600 with two modules, and Intel rates the Core Ultra 200S for DDR5-6400 only with clocked modules on a board that has one slot per channel. Intel’s figure for two modules on a four-slot board is DDR5-5600. Anything faster comes from an overclocking profile stored on the module, and that gap sits behind several of the failures covered near the end.

What the numbers on a kit mean

DDR5 is defined by JEDEC’s JESD79-5 standard. Its current public revision is JESD79-5D, version 1.41 from November 2025, and it covers memory chips from 8Gb through 32Gb. When JEDEC published the first DDR5 standard in July 2020, it said the memory was expected to launch at 4.8Gbps. The JESD79-5A update in October 2021 extended the core timings to 6,400MT/s, and JESD79-5C in April 2024 expanded the timing definitions from 6,800MT/s to 8,800MT/s.

Data rate

Advertised speed is the data rate in megatransfers per second (MT/s). DDR5-6000 moves 6,000 million transfers per second. DDR stands for double data rate, so the memory clock runs at half that figure. Igor’s Lab shows this in its Ryzen 7000 testing, where a 6,400MT/s profile runs a 3,200MHz memory clock.

Timings and true latency

A timings line reads like 30-38-38-96. Its first number is the column address strobe (CAS) latency, or CL, counted in memory clock cycles. Because a cycle gets shorter as the data rate rises, CL alone says little. CL multiplied by the clock period is the figure to compare, and it works out to CL x 2,000 / data rate, in nanoseconds.

Micron’s DDR5 SDRAM core datasheet shows why that matters. Its DDR5-4800B, DDR5-5600B, and DDR5-6400B speed bins use CL40, CL46, and CL52, and all three list a 16ns minimum for the read delay the datasheet calls tAA. CL climbs with every bin while the time in nanoseconds stays flat.

A retail kit’s profile is different. G.Skill’s spec sheet for the Trident Z5 NeoX F5-6000A3038F16GX2-TZ5NXRK puts its EXPOXMP from Intel and EXPO from AMD are memory profiles stored on a module that set faster speeds and timings than the standard ones when turned on in the BIOS. profile at 30-38-38-96 at 6,000MT/s and 1.35V, which works out to 10ns. That kit’s SPD default is 4,800MT/s at 1.10V, and the table below sets both kinds of figure side by side.

Source: Micron DDR5 SDRAM core datasheet, Tables 361, 363, and 365, Micron’s DDR5 white paper for the 1.1V supply, and the G.Skill F5-6000A3038F16GX2-TZ5NXRK specification. The ns column is calculated.

I’d read the timings line before the data rate. Kits with the same DDR5-6000 label can differ, and AMD’s own EXPO testing ran DDR5-6000 at CL28, CL30, and CL36, which works out to about 9.3ns, 10ns, and 12ns.

The three JEDEC bins each land just past the dashed 16ns line. The DDR5-6000 profiles all sit well under it, at about 9.3ns to 12ns, and that gap is the latency a faster kit buys.

XMP and EXPO are overclocks the kit stores

Every DDR5 module carries a serial presence detect (SPD) chip that tells the system how to run it. Micron’s client module white paper describes an SPD hub on each DDR5 module, with an optional temperature sensor. The SPD always holds JEDEC settings, and according to Intel’s XMP page, XMP modules first boot at those default JEDEC settings. A faster profile only runs once someone turns it on in the BIOS.

Intel XMP 3.0

Intel’s Extreme Memory Profile (XMP) 3.0 is the DDR5 version. It supports up to five profiles, three written by the vendor and two that the user can rewrite. XMP 2.0 was the DDR4 version, with two profiles. Corsair’s DDR5 FAQ puts its own modules at up to two preconfigured profiles, with room to save two custom ones.

AMD EXPO

AMD Extended Profiles for Overclocking (EXPO) is AMD’s counterpart, created for Ryzen processors on socket AM5. AMD now lists an EXPO tier for Ultra Low Latency memory as well. AMD also publishes a memory compatibility list that shows whether a tested kit supports EXPO, holds the Ultra Low Latency certification, or is XMP-compatible.

On an MSI AM5 board, the EXPO item loads the module’s EXPO profile “with optimized timing and voltage settings supported by installed memory module.” That makes it a one-click overclock, and AMD treats it as one. Its EXPO page says operating memory outside AMD’s published specifications “will void any applicable AMD product warranty, even when enabled via AMD hardware and/or software.”

What the profile does not set

A profile sets the memory’s speed, timings, and voltage. Everything else comes from the board’s firmware. When AMD addressed burned AM5 processors in 2023, Tom’s Hardware reported that the EXPO profile itself does not raise the SoC voltage. Board vendors applied their own higher value when EXPO was enabled. AMD’s 2023 changes to that voltage are covered under troubleshooting below.

Ranks, slots, and the four-module penalty

Each DDR5 module splits into two independent subchannels. Micron’s white paper says each subchannel has up to two physical package ranks. A rank is a set of memory chips that answer together. Modules are sold as single-rank (1R) or dual-rank (2R), and the rank is printed in the part’s specification, such as 1Rx8 or 2Rx8.

One or two modules per channel

AMD’s AM5 product pages and Intel’s Core Ultra 200S brief both list two memory channels. A dual in-line memory module (DIMM) is the stick itself. A board with four slots can hold two modules on each channel, which AMD’s pages write as 4x. Both companies cut the official speed for the second module, and in Tom’s Hardware’s view two-module setups are better for signal routing and less stressful on the processor’s memory controller.

AMD’s figures follow the module count. The Ryzen 7 7800X3D page lists DDR5-5200 for two modules of either rank and DDR5-3600 for four. The Ryzen 9 9950X3D lists DDR5-5600 for two and DDR5-3600 for four.

Intel’s figures follow the slot count. Its datasheets define one DIMM per channel (1DPC) as a board with one slot routed per channel, and two DIMMs per channel (2DPC) as a board with two. A four-slot board is a 2DPC board in Intel’s terms even with only two modules in it. Intel’s 13th generation desktop datasheet lists DDR5-5600 for a 1R module and DDR5-5200 for 2R on a 1DPC board. The figures fall on a 2DPC board to 4,400MT/s with one module per channel, 4,000MT/s with two 1R modules, and 3,600MT/s with two 2R modules. Kingston’s population tables set the same Intel rules out by socket count. Every platform appears in one table in the Optimal setups section below.

The middle panel is the layout most builds use. For AMD it matches the two-slot board, since both hold two modules. For Intel it belongs with the four-module board, since both route two slots per channel.

Matching part numbers

Intel adds a condition to its 2DPC figures, and the maximum 2DPC frequency holds when the same DIMM part number fills the channel. In Intel’s words, “Frequency is not guaranteed when mix DIMM’s populated.” That note is the basis for the mixed-kit fix below.

24GB and 48GB modules

DDR5 also brought non-binary capacities. SK hynix shipped samples of 24Gb DDR5 chips in December 2021 and said the density enables 48GB and 96GB modules, so 24GB and 48GB sticks are no longer odd sizes. Intel’s datasheets cover 16Gb and 24Gb dies on 13th and 14th generation processors, and 16Gb, 24Gb, and 32Gb on Core Ultra 200S. On both LGA1700 generations, Intel’s datasheet says 24Gb support came after launch.

Capacity limits differ by processor. The Ryzen 7 7800X3D tops out at 128GB and the Ryzen 9 9950X3D at 256GB, according to AMD, while Intel rates the Core Ultra 200S for 192GB.

If I needed 64GB or 96GB, I’d buy it as two larger modules before four smaller ones. Every official table here rewards one module per channel.

What memory training does at boot

A DDR5 system can’t just apply a speed and go. The memory controller has to measure and tune the signal paths first, and that process is called training. Micron’s client module white paper says DDR5 “adds abilities to train the CS and CA buses,” the chip select and command and address lines, on top of data line training. Micron’s feature white paper describes a multipurpose command used “to perform functions like interface initialization, training and periodic calibration.”

Training is not a one-time event either. In Micron’s description, a DQS interval oscillator “helps signal to the system when it may need to retrain.” So the system keeps checking itself while it runs.

Why the first boot is slow

ASRock’s installation guide tells AM5 builders to “expect long POST time on AM5 platform at first boot.” It adds that boot time depends on the configuration, including the number of memory modules installed. POST is the power-on self test that runs before the operating system loads. This training can show as a black screen or a pause on the maker’s splash screen, and Crucial has seen it take up to 15 minutes. Later boots skip the wait until the hardware or the memory settings change. The same ASRock page asks AM5 builders to follow the board’s memory slot priority, which the slot fix below covers.

Steps 03 and 04 are the slow part, and they run in full only when something has changed. A first boot with a new kit runs all six steps, which is why it can sit on a dark screen long enough to look like a fault.

As the profile section above explains, a kit starts out at its JEDEC settings. Changing any memory timing can also leave a system unbootable. For that case, MSI’s manual says to clear the CMOS data and load the default settings.

Memory Context Restore

MSI’s AM5 BIOS manual describes Memory Context Restore this way: “If enabled, the POST latency will be minimized.” An MSI support answer explains how the setting lets the BIOS skip the memory self-check once the first boot has completed it. A moderator’s guide on ASUS’s ROG forum gives the same advice for ASUS AM5 boards and adds a caution to turn it off for a while after changing kits or memory settings so the board can retrain fully.

The same MSI manual lists Memory Try It!, which “can improve memory compatibility or performance by choosing optimized memory preset.” On a board from another maker, check the manual for its equivalent settings.

What sits on a DDR5 module

A DDR5 stick carries more than memory chips. Its own power regulator, an SPD hub, and on some modules a clock driver sit on the module’s circuit board too.

The PMIC and the SPD hub are on every DDR5 desktop module. The clock driver is the part that makes a module a CUDIMM.

The PMIC

DDR5 moved power regulation onto the module. JEDEC’s 2020 announcement listed a voltage regulator on the DIMM and a supply drop from 1.2V to 1.1V. JEDEC’s UDIMM standard, JESD308, says the module’s power management integrated circuit (PMIC) generates all the voltages the module needs from a 5V input. Micron’s white paper lists the DDR5 supplies as 1.1V for VDD and VDDQ and 1.8V for VPP.

For a builder, this means the board supplies 5V and each module makes its own memory voltages.

The clock driver on a CUDIMM

A clocked unbuffered DIMM (CUDIMM) adds a clock driver chip, or CKD, to the module so the clock is regenerated on the stick instead of arriving straight from the processor. JEDEC’s JESD82-531 standard defines the DDR5 CKD “for re-driving the DCK for CUDIMM, CSODIMM, and CAMM applications,” and the current version, 1.22, is dated January 2026. JEDEC’s SPD contents standard lists CUDIMM as its own base module type, separate from the ordinary unbuffered DIMM (UDIMM).

JEDEC published the CUDIMM and CSODIMM module standards, JESD323 and JESD324, in 2024. In that October 2024 announcement, JEDEC said that “by regenerating the clock signal locally on the DIMM, a CKD ensures stable operation even at elevated clock speeds.” It said the clock driver lifts DIMM data rates from 6,400MT/s to 7,200MT/s in the first version of the standard and targets up to 9,200MT/s later.

Micron announced CUDIMM and CSODIMM modules on the same day, rated up to 6,400MT/s. Micron said they are 15% faster than DDR5 without a clock driver, with the comparison made against 5,600MT/s. Micron also said Intel validated its modules up to 64GB on Core Ultra Series 2.

Core Ultra 200S is the platform that officially rates CUDIMM speeds. Intel rates it for DDR5-6400 with one CUDIMM per channel in 1Rx8, 1Rx16, and 2Rx8 configurations, against DDR5-5600 for ordinary UDIMMs. The CUDIMM figure rises on the higher 200S Plus models to 7,200MT/s. Both CUDIMM figures apply to boards with one slot per channel. The official figure for a four-slot board is 5,600MT/s for UDIMMs and CUDIMMs alike. AMD’s product pages list UDIMM as the supported subtype for the Ryzen chips covered here and don’t list CUDIMM speeds.

On-die ECC is not ECC memory

Error correction code (ECC) catches and fixes flipped bits. DDR5 also puts ECC inside the memory chips themselves, which is a different thing. Micron’s feature white paper describes it as single error correction that pairs 128 data bits with 8 parity bits. It corrects errors during reads before the data leaves the chip, and those 8 parity bits “do not allow for double-bit detection.” JEDEC framed on-die ECC as a scaling feature that enables “manufacturing on advanced process nodes.”

ECC memory

ECC memory is a separate system-level feature. Micron’s introduction to DDR5 splits each DIMM into two 40-bit channels, “32 bits plus ECC.” JEDEC’s CUDIMM raw cards include x8 layouts “with EC4,” which JEDEC glosses as 4-bit error correction. The processor and the board must both support it.

AMD’s pages for the Ryzen 7 7800X3D and Ryzen 9 9950X3D list ECC support as “Yes (Requires mobo support).” Intel’s matrices add that DDR5 ECC “is supported only when all memory populated in system supports ECC.” Core Ultra 200S supports ECC up to 6,400MT/s.

Optimal setups: AMD versus Intel

AMD and Intel publish a maximum supported speed for each layout. Anything above it is an overclock, even when the BIOS applies it in one click, and AMD’s warranty language treats it that way.

What AMD and Intel officially support

This table lists the official maximum data rate for each layout, as of October 2026. 1R and 2R mean single-rank and dual-rank modules. A two-module build on a four-slot board falls under the middle column.

Source: AMD Ryzen 7 7800X3D and Ryzen 9 9950X3D product pages, plus the DDR support matrix in volume 1 of Intel’s 12th generation, 13th and 14th generation, and Core Ultra 200S datasheets. AMD’s figures stay the same on two-slot and four-slot boards. Intel’s change with the slots routed per channel. AMD’s pages list no CUDIMM speeds.

Intel also tells builders which slot to fill. When a single module sits on a two-slot channel, Intel’s rule is to populate the far slot.

AMD’s first two bars match, since both boards hold two modules. Intel’s drop from the first bar to the second because a four-slot board is a 2DPC board even with two modules in it, and on LGA1851 only the two-slot bars pass 5,600MT/s.

The AM5 sweet spot

AMD’s official number for Ryzen 7000 is DDR5-5200, but its own example kit is faster. The Ryzen 7 7800X3D page cites game testing on a G.Skill DDR5-6000C30 kit with EXPO, and AMD’s EXPO testing in March 2026 used DDR5-6000 on a Ryzen 7 9700X.

AMD’s clearest statement of the sweet spot came through a second-hand report. Before Ryzen 7000 went on sale, Tom’s Hardware reported that AMD’s Robert Hallock called DDR5-6000 the sweet spot for Zen 4 “based on cost, stability, performance, availability, and ease.” Hallock recommended leaving the fabric clock (FCLK) on auto and keeping the memory clock (MCLK) and the memory controller clock (UCLK) at 1:1, a setup Tom’s wrote as Auto:1:1. Tom’s said the default FCLK on Zen 4 is 1,733MHz. MSI’s AM5 BIOS exposes these as FCLK Frequency and UCLK DIV1 MODE.

Igor’s Lab found that above DDR5-6000, the UCLK drops to half the memory clock on its own. Both of these are secondary sources, and AMD’s spec pages don’t state a 1:1 limit.

Intel’s gear modes

Intel runs its memory controller at a ratio of the DRAM speed that it calls a gear, and it can switch gears on the fly. Intel’s 13th generation datasheet defines Gear 1 as 1:1, Gear 2 as 1:2, and Gear 4 as 1:4, and it lists DDR5-5600 on a 1R UDIMM in Gear 2 at the top performance point. Core Ultra 200S drops Gear 1 and runs only Gear 2 and Gear 4. The top point runs Gear 2 at 5,600MT/s for UDIMM, 6,400MT/s for CUDIMM, and 7,200MT/s on 200S Plus, with both CUDIMM figures limited to two-slot boards.

Picking a kit

Source: AMD product and EXPO pages, Intel’s DDR support matrices and SAGV tables, and Tom’s Hardware’s report of AMD’s Robert Hallock (secondary). A CUDIMM kit’s rated speed above 5,600MT/s on a four-slot Core Ultra 200S board runs as a profile, outside Intel’s official figure. Every kit size fits within the 128GB, 192GB, and 256GB maximums listed earlier. The 24GB and 48GB sizes need 24Gb die support, which Intel added after launch on both 13th and 14th generation chips.

Checking the setup from Linux

EXPO, XMP, training, and the other memory settings in this guide live in the board’s firmware, so they work the same whichever operating system boots afterward. Linux adds a way to check what the firmware actually set.

dmidecode prints the firmware’s DMI table, also called SMBIOS, and sudo dmidecode --type memory shows only its memory entries. Each installed module appears as a Memory Device entry with two speed fields, which the SMBIOS specification defines. Speed is the module’s maximum capable speed, and Configured Memory Speed is the speed it’s set to run, both in MT/s. Configured Memory Speed is the one to check after turning on a profile. The man page warns that the table comes from the firmware rather than from probing the hardware, so it can be wrong.

lshw reports the same memory configuration, and it must run as root or it reports only part of it. On DDR5, the kernel’s spd5118 driver supports the temperature sensor that many DDR5 modules carry, and it can also read a module’s SPD data through an eeprom file.

When it won’t boot or won’t stay stable

A memory problem on a new build can show up as a black screen, a reboot loop, or crashes under load. The fixes differ, so diagnose before changing anything. Start from a known baseline, which means the BIOS defaults with no profile loaded, and change one thing at a time. Work down one path of the tree below and stop at the first change that fixes the problem.

A long black screen on the first boot

A new build shows nothing on screen for a long stretch, and the fans spin. This is often normal. ASRock tells AM5 builders to expect a long POST at first boot, and the first boot of an XMP kit happens at JEDEC speed, per Intel. On ASUS AM5 boards, the ROG forum guide says training shows as Q-code 15 or a yellow DRAM light.

Leave it powered for at least 15 minutes, the longest wait in Crucial’s article, before pulling parts. If later boots stay slow, check whether your board offers Memory Context Restore, which lets the BIOS skip the memory check after the first full training.

The DRAM light stays on

The board’s DRAM diagnostic LED stays lit and the system never reaches the BIOS. In the words of ASUS, a DRAM LED that stays on after power-up “indicates no Memory or Memory faulty.” On a first boot, rule out training before treating the light as a fault, since a lit DRAM light can also mean the board is still training.

Its FAQ orders the fixes like this. Reseat the modules, clean the contacts, check the board’s qualified vendor list (QVL), and follow the manual’s slot layout. Then boot with one module and add the others one at a time, try different memory, clear CMOS, and update the BIOS with BIOS FlashBack.

Two modules in the wrong slots

A build with two modules boots slower than expected, or not at all. Two modules on a four-slot board belong in specific slots. On the example board in its install FAQ, ASUS puts one module in DIMM_A2 and two modules in DIMM_A2 and DIMM_B2. Corsair’s advice is that you “have to first install your DIMMs in the primary set of memory channels.”

Slot names vary between boards, so check the manual. Intel’s own rule for one module on a two-slot channel is to use the far slot.

Four modules won’t run at the kit’s speed

A four-module build won’t boot or won’t stay stable with the profile on. This is expected behavior, not a fault. AMD rates every AM5 chip covered here at DDR5-3600 with four modules, and Intel’s 2DPC figures fall to between 3,600MT/s and 4,400MT/s on 12th through 14th generation chips. Corsair puts the limit in the processor: its memory controller caps the speed a board can reach, “particularly with four DIMMs or two dual-rank DIMMs.”

Drop the speed toward the official 2DPC figure until the system is stable. Two larger modules are the cleaner fix.

Two kits mixed together

Someone adds a second kit to fill four slots, and the profile won’t apply or the system won’t boot. Corsair warns that combining kits, “even if they are rated with the same speed,” risks “system stability problems, the EXPO or XMP being prevented from enabling, or even your system being unable to boot.” Intel guarantees 2DPC speeds only when the same part number fills the channel.

Test each kit alone first. If both pass alone and fail together, run them at JEDEC speed, or replace them with one matched kit.

The profile boots but crashes under load

The system runs with EXPO or XMP on, then crashes in games, throws errors in a memory test, or reboots. The profile is an overclock that the processor’s memory controller may not hold. Confirm it by turning the profile off. If the crashes stop at JEDEC settings, the profile is the cause.

Corsair suggests two fixes: enter the rated settings by hand, or run defaults until the board vendor releases a BIOS update that improves stability. Its help center adds a third for high-frequency kits, which is to loosen the timings. MSI boards also offer Memory Try It!, a set of memory presets for compatibility or performance. Stepping one speed grade below the profile is another option.

High SoC voltage on early AM5 BIOSes

In 2023, some AM5 processors failed physically. AMD’s statement, as reported by Tom’s Hardware and TechPowerUp, said AMD had root-caused the issue and distributed a new AGESA to keep the CPU within its specification limits, “including a cap on SOC voltage at 1.3V.” It added that none of the changes affect overclocking memory “using EXPO or XMP kits.” Tom’s describes AGESA updates as the building block for the BIOS firmware that board makers distribute. Tom’s also reported that the failures happened when the SoC voltage went above 1.3V, set either by the user or automatically by the board when EXPO was enabled.

Update the BIOS to a current release. Then check the SoC voltage in the BIOS with EXPO enabled, and keep any manual setting at or below 1.3V.

Raptor Lake crashes that look like memory faults

A 13th or 14th generation desktop crashes or fails stress tests, and the memory gets the blame. Intel traced this “Vmin Shift Instability” to “a clock tree circuit within the IA core,” the processor core itself, which is “particularly vulnerable to reliability aging under elevated voltage and temperature.” In Intel’s account, memory was not the cause. Intel ran its microcode performance tests with DDR5 at 5,200MT/s and 5,600MT/s, and it says Core Ultra 200S (Arrow Lake) is unaffected.

Intel’s support article recommends Intel Default Settings and the latest BIOS with microcode 0x12F or later. It also extends the warranty on eligible affected processors by two years, to up to five years from purchase. Before replacing memory on these chips, update the BIOS, load Intel Default Settings, and test the memory at JEDEC speed. If the faults persist with known-good memory at defaults, look at the processor.

Reading memory errors on Linux

Linux has two routes for memory errors. The kernel’s EDAC subsystem collects corrected errors (CE) and uncorrected errors (UE) from the memory controller, counts them under /sys/devices/system/edac, and writes them to the system log. Those errors come from ECC, which needs extra bits on the module, so the counts mean something only on ECC memory. On the desktop platforms here, that means ECC modules and, on AM5, a board that supports them. On x86 processors, the same errors can also arrive as machine checks. A corrected error becomes a log entry, while an uncorrected one typically causes a machine check, often with a panic.

To read them, journalctl -k shows only kernel messages, per its man page. rasdaemon watches the kernel’s RAS error events and stores them in a database. Its ras-mc-ctl tool prints the corrected and uncorrected counts with --error-count, or a summary of logged errors with --summary.

A desktop on non-ECC modules has no correction bits to report from, so a clean count there proves nothing. Use a memory test instead.

Which memory test to run

These tools load memory in different ways, so run more than one. Run each one at JEDEC defaults first, then with the profile on. A failure at defaults points at hardware, and a failure only with the profile points at the overclock.

The tests in the first panel boot on their own, with no operating system in the way. The other two panels run as programs, one set inside Windows and one inside Linux. Using one from each kind puts two different loads on the same memory.

Tests that boot outside the operating system

MemTest86 boots from a USB drive and tests memory without the operating system in the way. It runs 14 test algorithms, including SIMD, row hammer, and DMA tests, and its support list includes DDR5, ECC, and CAMM2. PassMark offers it as a free edition alongside paid Pro and Site editions.

Its hammer test reads two addresses over and over, then checks other addresses for flipped bits. Since version 6.2, an error on that first full-speed pass triggers a second pass at a slower rate that memory vendors treat as the worst case, 200,000 accesses per 64ms. Errors on both passes are reported as normal, while an error on the first pass alone produces a warning instead.

Windows has its own option. Windows Memory Diagnostic runs after a restart, with Standard tests by default, per Microsoft. Extended tests are more thorough and take longer, and Microsoft suggests them when the Standard tests show no issues. Press F1 on the test screen and change the Test Mix to Extended.

Stress tests inside Windows

TestMem5 is a PC memory stress test, and CoolCmd’s GitHub repository maintains an updated build of the original. OCCT is billed by its maker as a free stability, stress test, benchmark, and monitoring tool. Alexander Yee wrote y-cruncher and warns that it may expose instabilities other stress tests miss, since it loads the CPU and the whole memory subsystem at once.

Windows also logs hardware faults. Microsoft describes its Windows Hardware Error Architecture (WHEA) as support for “hardware error reporting and recovery,” so WHEA entries in the event log are worth checking after a crash.

Testing on Linux

Memtest86+ is a free, open-source, stand-alone tester, and it isn’t an edition of MemTest86. It runs from a FAT32 USB drive, and on Linux you write its ISO straight to the drive with dd. Version 9.00 adds a bus stress test aimed at DDR5 that, per the project, can uncover XMP or EXPO training issues. It loops until you stop it, and one successful pass has tested all the memory. If it finds errors on an overclocked system, retest at default settings first, then remove modules one at a time to find the faulty one.

Inside Linux, memtester is a userspace stress test for the memory subsystem. Run it as root so it can lock the memory it tests, and expect it to cover less than the installed total, since the operating system keeps some. stressapptest, used at Google, is a memory interface test that pushes randomized traffic from the processor and I/O to create a realistic high load.

The kernel has a basic test of its own. The memtest= boot parameter sets a number of passes at startup. Each pass fills memory with a pattern, checks it, and reserves any bad regions it finds.

What to watch

As of October 2026, the CKD is where desktop memory speed is moving. JEDEC’s first CUDIMM standard stops at 7,200MT/s, and future versions target up to 9,200MT/s. Intel already rates Core Ultra 200S Plus for CUDIMM at 7,200MT/s on boards with one slot per channel. The open question is when CUDIMM speeds appear on AMD’s AM5 product pages.

JEDEC’s JESD79-5C timing tables already run to 8,800MT/s, above the 7,200MT/s of the first CUDIMM standard. Watch for the next CKD revision and for official speeds above 7,200MT/s.

AMD’s EXPO Ultra Low Latency tier is new, and its compatibility list will show which kits earn it. On Intel’s side, the current guidance for 13th and 14th generation chips names microcode 0x12F or later, so check each new BIOS’s release notes for memory changes.

For the chips inside the modules, see DRAM from the inside and current memory ICs. For kits, see Best RAM. The flat module that is replacing the DIMM in laptops is in CAMM2, LPCAMM2 and SOCAMM2.