What a Gigawatt Takes

Data center plans are now announced in gigawatts. Meta plans its Prometheus cluster at 1GW and expects its Hyperion site to scale to 5GW from 2028. A gigawatt is a power budget, though, and chips are made on wafers, every leading-edge one passing under an EUVEUV lithography prints with light of a far shorter wavelength than deep ultraviolet, made by striking droplets of tin with a laser. It needs mirrors and a vacuum instead of lenses, and ASML is its only maker. scannerA scanner is a lithography tool that moves the mask through a narrow slit of light while the wafer moves the opposite way in step, so only a small part of the pattern is exposed at a time. ArF immersion and EUV tools are scanners. many times.

In March 2026, SemiAnalysis founder Dylan Patel walked a gigawatt of NVIDIA’s Rubin systems back to the fab on the Dwarkesh Podcast. His chain runs from wafers to EUV exposures to scanners. This page follows it link by link, sets each link beside the makers’ own numbers and marks where the chain rests on his estimate alone. For the tools, money and years it takes to add memory supply, see The Memory Cycle, and for the clusters themselves, Racks and Rows.

Three kinds of wafer

Patel’s gigawatt needs about 55,000 wafers on a 3nm process, about 6,000 on 5nm and about 170,000 of DRAM. Those are his own estimates, and the transcript gives the totals without the model behind them. He names the three buckets but does not say which chips each one holds.

Three kinds of wafer

DRAM is the largest wafer count in a gigawatt

Wafers for one gigawatt of NVIDIA Rubin, by process

The copper DRAM bar is the longest by far, and HBMHigh Bandwidth Memory stacks DRAM dies on a base die and links them with thousands of vertical wires, giving a very wide, short path to a processor on the same package. explains why. Each Rubin GPU carries up to 288GB of HBM4 in NVIDIA’s own figures. Stacked memory is expensive in wafers. Micron’s chief executive said in March 2024 that HBM3E takes about three times the wafer supply of DDR5 to make the same number of bits on the same node. So every gigawatt of accelerators competes with phones and PCs for the same DRAM wafers, and it takes more wafers for each bit it gets.

Against one maker the scale is clearer, since SK hynix plans to reach roughly 620,000 DRAM wafers a month by 4Q26, according to TrendForce, which cites The Bell. On that plan, one gigawatt’s DRAM is about eight days of that maker’s whole DRAM output.

Why a GPU takes HBM anyway

JEDEC’s HBM4 standard gives each stack a 2,048-bit interface at up to 8Gb/s, for up to 2TB/s. Rubin’s stacks run at about 10GT/s on the same 2,048 bits by Patel’s figure, roughly 2.5TB/s each, which is faster than the standard’s top speed.

Why a GPU takes HBM anyway

HBM buys bandwidth with width along the GPU’s edge

The same 11 to 13mm of GPU edge, wired to HBM4 and to DDR

The dense copper bundle on the left shows the trade. In Patel’s description a chip is a fixed size and all of its I/O leaves through its edges, and each stack takes roughly 11 to 13mm of that edge. In the same length a DDR interface is maybe 64 or 128 bits wide. So a GPU takes HBM for its bandwidth even though each bit costs more wafer, and Patel’s measure for that trade is “bandwidth per wafer.”

From wafers to exposures

A chip is printed layer by layer, and each critical layer takes its own pass under a scanner. In Patel’s count a 3nm wafer has about 70 lithography layers, and about 20 of them are EUV. Multiply 55,000 wafers by 20 passes and the logic alone needs 1.1 million EUV passes. Adding the 5nm wafers and the memory brings his total to about 2 million passes per gigawatt. How one pass prints a layer is in Photolithography, Part 1.

From wafers to exposures

Twenty EUV passes a wafer add up to about 2 million

One 3nm wafer’s layers, then Patel’s count for one gigawatt

In the stack, the teal EUV layers are a minority of the whole, and each one is a full pass of the wafer. That layer count is the softest link so far, since the 20 is Patel’s own figure with no maker number beside it and the 2 million carries the same doubt.

How fast a scanner runs

Patel turns passes into tools with two assumptions. An EUV scanner exposes roughly 75 wafers an hour, and it runs about 90% of the time. At that rate, running around the clock all year, one tool makes about 591,300 passes. Two million passes then take about 3.4 tool-years, which is his three and a half tools per gigawatt.

ASML rates its scanners much faster. Its 2025 annual report says it delivered the NXE:3800E at full specification in 2025, which includes 220 wafers an hour. An energy table in the same report measured 230 wafers an hour that year, at a 30mJ/cm² dose. At the rated 220 and the same uptime, one tool makes about 1.73 million passes a year. A gigawatt then needs about 1.2 tools.

How fast a scanner runs

At ASML’s rated speed, a gigawatt needs 1.2 tools, not 3.4

EUV tool-years for 2 million passes, at 90% uptime

The left panel fills several tool blocks, and the right barely more than one. Patel’s 75 wafers an hour is about a third of the rated figure, 34%. ASML measures its rate at a stated dose, and the transcript does not say what dose or overheads the 75 assumes, so the gap cannot be split into its causes here. At the rated speed, a gigawatt needs 1.2 tools instead of 3.4.

What a scanner costs

Next to what they hold up, the tools are cheap. A gigawatt of SI data center costs roughly $50 billion in Patel’s count, and the three and a half scanners behind it about $1.2 billion, at a selling price of $300–400 million each. In his telling the first EUV tools sold for about $150 million, and the price is heading to $400 million by 2028. ASML prints no price list, but its annual reports give EUV units and sales, so an average per system can be worked out.

What a scanner costs

ASML’s average EUV system rose to about $268 million by 2025

EUV system sales divided by units, in US dollars at each year’s average euro rate

Worked out that way, ASML’s low-NA scanners averaged about $164 million a system in 2020 and $268 million in 2025, converted at the Federal Reserve’s annual euro rate. Its High-NA systems averaged about $327 million in 2025. Patel’s $300–400 million sits above ASML’s low-NA average for any year so far, and near High-NA. At ASML’s 2025 average, his 3.5 tools come to about $0.94 billion against his $1.2 billion.

These averages are sales divided by units, so they mix configurations and any upgrades booked with a system, and they are not list prices. Lithography is about 30% of the cost of an advanced logic chip by Patel’s figure, though the step adds no material to the wafer. The tools are a small cost that holds up a far larger one, and that is his case for ASML as the limit.

Scanner energy is small by comparison, at 5.5kWh per wafer pass for the NXE:3800E in ASML’s 2025 report, down from 12.8kWh for the NXE:3400B in 2018. At that rate Patel’s 2 million passes take about 11GWh, or about 11 hours of a gigawatt data center’s draw.

Why the limit is expected to reach the scanner

Each earlier limit on SI compute had a short lead time. Patel names CoWoS packaging, power and data centers as the earlier limits and calls all three shorter lead-time items. A data center takes less than a year, and he has seen Amazon build some in as little as eight months. A new fab takes two to three years of construction in his account.

Why the limit is expected to reach the scanner

A data center goes up in under a year, a fab in two to three

The earlier limits Patel names, the one he expects next, and two lead times

Scanners sit at the end because, in Patel’s words, the tools have really long lead times of their own. He expects the limit to fall to ASML by 2028 or 2029, a forecast rather than something that has happened yet. How CoWoS packaging works, and why it ran short, is in Photolithography, Part 5.

Where the limit sits

Patel’s case that scanners become the limit rests on how few exist. He said ASML can make about 70 EUV tools a year now and 80 next year, and a little over 100 by the end of the decade. In its second-quarter 2026 results ASML put its 2026 low-NA EUV capacity at around 65 systems, with 30% more planned for 2027. Capacity is what ASML can build in a year, and recognized units are what it booked, so the two need not match.

Where the limit sits

Patel’s 2026 count sits just above ASML’s own capacity

EUV systems a year: recognized, planned capacity and Patel’s estimate

The dashed gray bars are Patel’s and the teal ones are ASML’s, and his 70 for 2026 sits just above ASML’s capacity of about 65, and well above the 48 it recognized in 2025. The Fab Tracker lists the same counts beside the rest of the lithography fleet.

His installed base is easier to check, and ASML’s own counts put it higher. ASML marked its 100th EUV shipment at the start of 2020, after recognizing 18 systems in 2018 and 26 in 2019. It then recognized 31 EUV systems in 2020, 42 in 2021 and 40 in 2022, and 53 in 2023, 44 in 2024 and 48 in 2025. That is about 358 in all, against Patel’s 250 to 300. That sum mixes a shipment count with booked sales and takes in every tool delivered since the first, so it can only overstate the tools in use today.

At Patel’s rate per gigawatt, each year’s 65 or so new scanners add EUV time for about 19GW of SI chips a year. By Patel’s count the industry reaches about 700 tools by 2030, enough for 200GW if every tool worked on SI chips, which he notes they do not. He still called that supply completely compatible with the gigawatt a week Sam Altman wants by 2030.

The makers check the chain only in part. ASML’s rating, tool counts and sales are firm, and Micron’s wafer penalty is for HBM3E, the generation before Rubin’s HBM4. No maker number checks Patel’s 55,000, 6,000 or 170,000 wafers, the EUV layers per wafer or the real scanner rate.

Three numbers would settle most of it: a maker figure for EUV layers on a 3nm wafer, production throughput for the NXE:3800E rather than its rating, and how much of ASML’s planned 2027 capacity becomes recognized systems. Until then, read a gigawatt announcement as a wafer order, and the memory count is the big number in it.