Week endingFriday, October 9, 2026Covers October 3 to October 9, 2026 · 16 items
Samsung published preliminary third quarter guidance on Thursday, and it points to profit far above a year earlier. It is the week's main company news for memory, and the final results are still to come.
The rest of the week was mostly research. A perspective paper argues that future NAND scaling will need several kinds of cell, another shows ferroelectric NAND used for database search, and further papers cover RowHammer mitigation, zoned SSD placement and CXL memory. Eyes on Flash added a run of Beyond NAND guides, two myth guides and a DRAM die timeline.
Samsung Electronics released preliminary sales and operating profit guidance for the third quarter. The company's own comparison shows operating profit well above both the second quarter and the same quarter a year ago. Final results come later.
Samsung Electronics ·
The authors argue that tall stacks are limited less by process steps than by charge migration, coupling and read disturb, and that charge trap, ferroelectric and other cell types will each fit different tiers of storage.
arXiv ·
A Georgia Tech led team with Samsung authors uses a ferroelectric NAND array to compare stored entries against a query inside the array, aiming at large database search. It is a device and system study, not a product.
arXiv ·
Researchers at Sungkyunkwan University and Samsung look at how the word line waveform and a trap cut structure make hot carrier injection programming more reliable in V-NAND flash. The paper is an accepted manuscript.
MORDOR delays the preventive refreshes that protect DRAM rows from read disturbance, so they interfere less with ordinary requests. It sits in the memory controller next to existing mitigation schemes.
RetainZ uses checkpoint retention policies to group data that will be freed together, so a zone reset reclaims more space with less copying. The results come from an emulated drive.
The authors replace a VM based emulator with a kernel module that serves cache hits natively and models NAND delay on misses, which they say keeps the two speed latency profile of a CXL SSD while cutting emulation overhead.
The study looks at how index layout and data placement across fast DDR and slower CXL memory change in memory database performance, and proposes an adaptive way to distribute data between the two tiers.
The paper in IEEE Transactions on Computer-Aided Design describes a repair architecture for faults in the vertical connections of stacked high bandwidth memory.
IEEE TCAD ·