Week endingFriday, August 28, 2026Covers August 22 to August 28, 2026 · 12 items
Hot Chips put memory on the main stage. The Sunday tutorial lined up Micron, Samsung and SK hynix on HBM base dies and packaging, with talks on 3D DRAM accelerators and high bandwidth flash alongside, and Samsung brought processing in memory to LPDDR. Nvidia then said it will put the memory controller inside the HBM stack with NVHBM, and SK hynix explained why hybrid bonding matters.
On the supply side, Kioxia and Sandisk said they plan a large Japan expansion, and SK hynix broke ground on its Indiana HBM packaging site. Marvell reported results, Micron reshuffled its top technical and operating roles, and three new papers looked at flash as an HBM tier, a software defined SSD and near memory compute.
The two partners said they intend large investments in Japan through the early 2030s, contingent on government support. The money is meant to expand output at the Yokkaichi and Kitakami plants they share and to back multi year bit growth.
Kioxia ·
Nvidia expanded NVLink Fusion with NVHBM, which moves the memory controller from the accelerator die into the HBM stack. It says memory partners will validate and offer it, and Amazon's Annapurna Labs is the first named collaborator.
Nvidia ·
At Dell Technologies Forum in Seoul, SK hynix showed HBM, SOCAMM2, MRDIMM and LPCAMM2 memory with a range of E3.S, E1.S and M.2 SSDs. Two of them are its first QLC enterprise and first QLC client drives.
SK hynix ·
SK hynix held a groundbreaking in West Lafayette for an advanced packaging facility, its first HBM production base in the United States. It says volume production of next generation HBM there is planned for the second half of 2029.
A newsroom tech note describes joining chips directly through copper with no solder bumps, which allows denser and cooler stacking. It says cost and technical hurdles will set how fast the method spreads, especially for HBM.
The Sunday program paired Micron, Samsung and SK hynix talks on evolving memory, the HBM base die and HBM packaging with sessions on a 3D DRAM accelerator and on high bandwidth flash from a system architect's view.
The Tuesday memory session carried Samsung's LPDDR5X-PIM, billed as the first LPDDR based processing in memory part for AI inference, and the XCENA MX1, a computational memory device that attaches over CXL.
Marvell reported its second quarter of fiscal 2027 and said data center demand drove the growth. The CEO said AI related bookings remain exceptionally strong.
Micron named Manish Bhatia to lead global operations and business units and Scott DeBoer to oversee its memory and storage roadmap and research labs. Sumit Sadana moves to an advisory role.
The paper treats stacked NAND as a capacity tier beside HBM. It adds a burst buffer controller, moves refresh off the read path and uses a read only translation table for model weights.
arXiv ·
The authors describe a software defined SSD that lets trusted applications define FTL policies and the exposed interface while keeping the translation layer isolated from a compromised operating system.
arXiv ·
The paper combines a vertical channel transistor DRAM cell with processing units placed on the peripheral die and the base die, aimed at models that mix attention, state space and expert layers.
arXiv ·