Week endingFriday, September 11, 2026Covers September 5 to September 11, 2026 · 12 items
CXMT published details of its LPDDR6 in mass production, the first appearance of the new low power DRAM standard in a flagship phone. SK hynix used its internal Future Forum to describe a stack of memory tiers, from 3D DRAM and HBM to high bandwidth flash, matched to each AI workload.
Phison reported controller demand tied to AI storage, Marvell lined up its PCIe 6.0 SSD controller and CXL memory products for an infrastructure show, and Kioxia took its gaming SSDs to Tokyo Game Show. Papers this week looked at high bandwidth flash, SSD firmware verification and HBM error correction, and Eyes on Flash refreshed two Flash Foundations parts and the Atlas.
CXMT's newsroom says the new low power DRAM, built to the JEDEC LPDDR6 standard, debuts in Xiaomi's 18 Fold and is now scaling to more customers. It claims gains in bandwidth and power over LPDDR5X, based on its own testing.
CXMT ·
Kioxia will exhibit at the show with the EXCERIA PRO G2 SSD, the official gaming SSD for the Asian Games esports events, plus a preview of portable SSD color options. It is a consumer showcase rather than a technology announcement.
Kioxia ·
Ahead of the mid September show, Marvell listed its CXL memory expansion, pooling and near-memory acceleration products, a PCIe 6.0 switch and a PCIe 6.0 NVMe SSD controller aimed at enterprise and AI storage.
Marvell ·
At an internal forum, SK hynix described combining 3D stacked DRAM, HBM and high bandwidth flash by workload, using system level co-design with partners across AI software and accelerators. The event was a strategy session, not a product launch.
In its monthly revenue notice, Phison said total and PCIe SSD controller shipments both rose, and that it sees itself moving from a NAND controller supplier toward an enabler of edge AI infrastructure.
Researchers built a formal verification framework in the Rocq proof assistant for SSD firmware that checks isolation, integrity and ownership, not just correct behavior. They show it on four FTL designs and release it as open source. It is a preprint.
arXiv ·
The authors present an open source simulator that injects high bandwidth flash timing and heat behavior into a real LLM run on a GPU, so designers can study HBM plus flash systems before hardware exists. It is a preprint.
arXiv ·
A controller design uses established inner codes plus a long outer code for rare repairs, aiming to protect HBM during AI inference at lower area and power than a direct long code. Results come from simulation and synthesis, and the work is a preprint.
arXiv ·
The authors model KV cache reuse for recommendation systems on high bandwidth flash and show that filtering low reuse users before admission cuts writes and stretches flash lifetime. It is an analytical model in a short preprint.
arXiv ·