Week endingFriday, July 24, 2026Covers July 18 to July 24, 2026 · 9 items
HBM4 moved from announcement to product this week. AMD launched its Instinct MI400 series with HBM4 and put its Helios rack into production, with Samsung reported as a key memory supplier, and Nvidia described how Rubin's HBM4 is meant to keep more of a model resident on the GPU.
On the market side, TrendForce said NAND should rebalance in the second half of next year, Samsung disputed a report about V10 NAND shipments to Nvidia, and South Korea's presidential office said Samsung and SK hynix will announce large deals with US firms. Three papers looked at CXL memory racks, in-NAND vector search and 3D memory for mixture of experts models.
DIGITIMES reports that Samsung denied a press report saying it had started supplying its V10 NAND to Nvidia and was preparing to expand output ahead of Nvidia's CMX storage rollout. The rest of the article is behind a paywall.
DIGITIMES ·
Reported by DIGITIMES; the company has not confirmed it yet.
An Nvidia developer post on the Rubin GPU says HBM4 widens the data path to the GPU and pairs it with a new memory controller. It says the large on-package memory keeps models resident and supports bigger KV caches without offloading.
Nvidia ·
The research firm's July update says NAND stays undersupplied through 2026 on AI demand and limited capacity additions. It expects strong server demand and process upgrades to rebalance the market gradually, with tightness easing in the second half of next year.
TrendForce ·
Reported by TrendForce; the company has not confirmed it yet.
At its Advancing AI event AMD launched the MI400 series, including the MI455X for frontier AI and the MI430X for sovereign AI and HPC. AMD says HBM4 and its bandwidth are central to running larger models. The post does not name the memory supplier.
The Korea Herald reports that AMD has started producing Helios and that Samsung is supplying the high bandwidth memory, as primary HBM4 supplier for the MI455X under an earlier agreement. Neither company has disclosed Samsung's share, and AMD's performance claims are its own.
Reported by The Korea Herald; the company has not confirmed it yet.
The presidential policy chief told reporters that the two memory makers will announce long-term supply contracts, investment partnerships and agreements of understanding with US technology companies during the president's Silicon Valley visit. Details were not given.
Reported by The Korea Herald; the company has not confirmed it yet.
HyMCache combines a little in-device DRAM with large SSD-backed capacity behind CXL, and uses prefetching and write buffering to keep reads fast. The authors test it on a prototype and report big DRAM savings against a distributed DRAM design; it is a preprint.
arXiv ·
D-NOVA embeds a retrieval pipeline directly in NAND strings using a new distance metric tailored to the string, plus an adapter that maps embeddings into a form the array handles well. Results are from the authors' evaluation and the work is accepted at MICRO.
arXiv ·
ThAME stacks non-volatile FeFET memory and DRAM chiplets and maps attention and expert layers to the memory that suits each, with a network designed for irregular token routing. The speedups are simulated, and the paper is accepted at ESWEEK.
arXiv ·