Weekly recap cover, week ending July 17, 2026An HBM stack of DRAM dies on a base die, joined by through-silicon vias, the lead topic of the week ending July 17, 2026; below it, one drawing for each topic the week covered: DRAM and HBM (1), SSDs and storage systems (2), Controllers and interfaces (1), Standards (1), Market and earnings (1), Research papers (3).THE WEEK IN MEMORY AND STORAGEWEEK ENDINGJuly 172026LEAD · DRAM AND HBM121113

Week endingFriday, July 17, 2026Covers July 11 to July 17, 2026 · 9 items

JEDEC Publishes SPHBM4, Micron Locks In Car Supply, and Silicon Motion Eyes PCIe Gen7

A quiet week for product launches, with the news coming mostly from standards and supply deals. JEDEC published SPHBM4, a version of HBM4 built to sit on ordinary organic substrates, and Micron said it has finished long-term supply agreements with a group of automotive suppliers.

On the controller side, Silicon Motion's enterprise chief said development of PCIe Gen7 controllers has already started, and a trade report said SK hynix began HBM4 shipments to Nvidia. Research this week leaned on AI serving, with papers on high bandwidth flash, CXL shared memory and Rowhammer defenses.

Top stories

ReportControllers and interfaces

Silicon Motion says PCIe Gen7 controller development has already started (opens in a new tab)

In an interview with Tom's Hardware, the head of Silicon Motion's enterprise storage business said work on PCIe Gen7 SSD controllers is under way and that Nvidia's Storage-Next effort is becoming a focal point for the company's data center plans.

Tom's Hardware ·

Reported by Tom's Hardware; the company has not confirmed it yet.

The rest of the week

SSDs and storage systems

Standards

Market and earnings

Research papers

  1. Paper designs a GPU system that uses high bandwidth flash for language model inference (opens in a new tab)

    FlashAccel adds high bandwidth flash stacks next to a GPU's HBM and reworks data layout and storage management so model weights and KV cache can live in flash. The gains come from the authors' own evaluation, and the work is a preprint.

    arXiv ·

  2. Paper scales unmodified multithreaded programs across machines with CXL shared memory (opens in a new tab)

    xDSM builds a distributed shared memory system on CXL that balances data between local DRAM and CXL memory and adjusts page sizes on the fly. The authors report it beating CXL-only baselines; it is a preprint.

    arXiv ·

  3. Paper adapts in-DRAM Rowhammer defenses to temperature instead of fixing a threshold (opens in a new tab)

    The authors argue the real Rowhammer threshold shifts with temperature and propose a runtime layer that resets each defense's threshold every epoch. Results come from simulation, and the work was presented at the DRAM security workshop.

    arXiv ·