Week endingFriday, August 7, 2026Covers August 1 to August 7, 2026 · 14 items
The Future of Memory and Storage conference in Santa Clara set the week. Sandisk and SK hynix released the first High Bandwidth Flash specification through the Open Compute Project, Kioxia and Sandisk unveiled a new QLC 3D flash technology, and Samsung showed concept models of zHBM and zNAND-O along with a wafer bonded V10 V-NAND.
Controller makers also showed PCIe 6.0 silicon, with Marvell announcing its Bravera SC6 and Silicon Motion showcasing its enterprise and client controllers. On the business side, WD reported fiscal fourth quarter results and CoreWeave signed a multi-year priority supply agreement with Solidigm.
The companies describe next generation quad-level-cell 3D flash that raises bit density over their eighth generation while targeting better performance and power efficiency for AI and cloud systems.
Kioxia and Sandisk ·
SK hynix executives opened FMS with a keynote on a memory hierarchy that adds 3D-stacked DRAM near accelerators, High Bandwidth Flash and CXL memory pooling, and showed the HBF specification work with Sandisk.
SK hynix ·
Kioxia's FMS lineup centers on the GP1 Series, with the CM10 and liquid cooled NX1 SSDs also on show. GP1 is aimed at expanding GPU memory with low latency flash.
Kioxia ·
At FMS, Samsung introduced a Bonding V-NAND architecture built with wafer bonding, plus concept models of zHBM and zNAND-O, a V-NAND based design aimed at edge AI.
The two companies released the HBF technical specification through the Open Compute Project, with Google and Tenstorrent taking part. HBF pairs high bandwidth with high capacity for AI inference.
The controller accepts NAND from multiple suppliers and is meant to move KV cache out of high bandwidth memory onto SSDs. Marvell also announced Structera X CXL memory expansion and new Photonic Fabric products.
The SM8466 is an enterprise PCIe 6.0 SSD controller, and the SM2524XT is a PCIe 5.0 DRAM-less controller. Both were part of Silicon Motion's FMS showcase.
The specification defines the base die that manages host traffic and controls a stack of NAND, along with host channels, interfaces, packaging, test and reliability for a flash device that sits next to processors.
WD, the hard drive company since the Sandisk separation, said revenue and margins grew and earnings per share more than doubled, citing growing storage demand from AI driven data creation.
CoreWeave gets priority access to Solidigm enterprise SSD capacity. Both companies describe storage as a growing constraint on AI cloud capacity planning as supply tightens.
PLoRA keeps LoRA adapters and KV cache in a pooled memory with compute beside it, so the GPU receives only reduced results over the link, and reports lower decode latency than a CPU DRAM staging baseline.
arXiv ·
ShimGen composes cluster level and global coherence protocols, such as CXL or AMBA CHI, including relaxed access modes, and the authors compare its output with a hand designed protocol.
arXiv ·
Aneto estimates how much of each cache miss stalls a processor using hardware counters, and is validated on an ARM server moving from local DDR to HBM.
arXiv ·
The authors evaluate heterogeneous DRAM processing-in-memory plus GPU designs for LLM decoding and argue that leakage and idle power, not just dynamic energy, must be modeled.
arXiv ·