Week endingFriday, October 23, 2026Covers October 17 to October 23, 2026 · 17 items
The week's company news was about money and capacity. SK hynix said it has ended the review of a Solidigm IPO while still saying Solidigm needs more production space in the United States, and Western Digital reported a first quarter that its management called ahead of expectations. Micron used an investor webinar to describe its next NAND generation, and SK hynix set the date for its own results.
The research list leaned toward how flash and DRAM serve AI. Several preprints look at keeping language model caches on SSDs without wearing them out, others put compute closer to DRAM, and a review surveys three dimensional DRAM. Eyes on Flash also put a DDR5 guide for builders live.
Micron's own slides give a first look at G11, which uses wafer on wafer bonding and is planned to ramp in volume in the second half of 2027. The company framed it as part of its technology plan for AI workloads.
Micron ·
SK hynix says weak market and share price conditions led it to stop reviewing an IPO for Solidigm. It says the need to fund new US fab capacity for AI memory demand is unchanged and that other financing options will be explored.
SK hynix ·
WD reported results for the quarter ended in early October, with its CEO saying demand for storage was strong and the company raised its quarterly dividend. The release also gives an outlook for the next quarter.
Western Digital ·
The study finds radiation eases one read disturb effect while worsening charge retention in cells at high states, which becomes the main reliability concern.
SK hynix invited investors to a conference call on its third quarter results, to be held in Korean with English interpretation. It will publish the results release before the call on the same day.
Gandalf argues that heavy cache writes can shorten an SSD's life from years to months. It decides which cache entries to admit using the type of attention that produced them, not only access history, so wear drops without hurting hit rate.
arXiv ·
VS-Flash looks at doing vector search for retrieval work close to the flash itself, using a computational memory semantic flash design, instead of moving all the data out to a host.
arXiv ·
SARP keeps an index of cached prefixes on the SSD so a serving system can match a new prompt quickly and recover its cache after a restart.
arXiv ·
M3D-FLOW targets generative normalizing flow models with a processing near DRAM design built as a monolithic three dimensional stack. It is accepted at IEEE TCAD.
arXiv ·
The authors split language model prefill and decode across a GPU and a processing near memory unit that share the same DRAM, aiming to avoid duplicating the model in memory.
arXiv ·
CXLResume keeps a service's state in memory that survives a restart, so the service can resume without rebuilding its data from storage.
arXiv ·
The paper in ACM Transactions on Architecture and Code Optimization sizes superblocks dynamically using a buddy allocator, a way to manage flash blocks in modern SSDs.
ACM ·
The review looks at three dimensional DRAM as a route past the limits of two dimensional scaling.
Nature Reviews Electrical Engineering ·
The paper from Photomask Technology 2026 covers active environmental control to make critical dimensions more repeatable when making masks for next generation HBM.
SPIE ·
HBFSim lets researchers compare placing flash stacks next to an accelerator against host DRAM, a CXL SSD or an NVMe SSD for language model workloads.
arXiv ·
The authors built a prototype CXL memory module that pairs SSDs with a DRAM cache and adds prefetching to hide SSD latency. They tested it on vector search datasets too large for memory.
IEEE Computer Architecture Letters ·