Week endingFriday, September 4, 2026Covers August 29 to September 4, 2026 · 9 items
A quieter week for filings, with the conversation about where memory sits relative to compute carrying on from Hot Chips. Samsung laid out its CUBE strategy at the SEMICON Taiwan summit, covering HBM5, a design that stacks HBM on the processor, and a NAND product for large models. Micron and SK hynix each published essays arguing that agentic AI turns memory into a system level limit.
Researchers posted work on DRAM RowHammer defenses in real time systems, disaggregated memory over CXL and SSD resident vector search. Eyes on Flash moved the Flash Foundations series, its software pages and its blog archive onto the rebuilt site.
In a keynote before SEMICON Taiwan, a Samsung memory executive presented a 3D strategy covering HBM5, zHBM, which stacks memory directly on the processor, and zNAND-O, a stacked NAND product for large models. This is a press report; the company page was not found.
The Korea Herald ·
Reported by The Korea Herald; the company has not confirmed it yet.
A Micron blog post argues that agents keep context, call tools and work across many steps, so HBM, DRAM and NAND have to be designed as one coordinated hierarchy rather than as separate parts.
Micron ·
An SK hynix newsroom essay says gains now depend on placing memory closer to compute, pointing to HBM, high bandwidth flash, CXL and processing in memory. It notes the views are the author's own.
SK hynix ·
The paper studies the per row activation counter defense standardized for DDR5 and shows an attacker task can push a victim past its worst case execution time. The authors derive an analytical bound that accounts for the delay.
arXiv ·
The framework rewrites an unmodified concurrent index so it can use remote memory, and the authors report it scales on real RDMA and CXL hardware for trees, hash tables and skip lists.
arXiv ·
The UBASE paper covers a quantization aware kernel and a storage engine that supports memory resident, hybrid and SSD resident deployments, trading memory for latency under operator control.
arXiv ·