3 facts filed under 3D structure and process: 1 read in the original source and 2 reported by a second source. Each was checked against the source’s own words, so its figures appear there, and each names where it comes from. The idea is taught in Part 4, 3D NAND Stacking.
Primary sources
Tanaka and colleagues’ ISSCC paper reports that a 768Gb 3b/cell 3D-FG NAND flash array is successfully developed.
Secondary sources
CuA moved page buffers and wordline drivers under the array, letting the polysilicon wordlines be segmented with local drivers.
CMOS under array puts page buffers and wordline drivers beneath the array, which allows cutting bitlines and wordlines into segments; local drivers shorten the high-resistance polysilicon wordlines.
Sources
Primary is the original paper, standard or datasheet. Secondary is a review, a vendor summary or a news report. Measured is my own test data.
Show all 2 sources, 1 primary
- Secondary3D Flash MemoriesSpringer, 2016
- Primary7.7 A 768Gb 3b/cell 3D-Floating-Gate NAND Flash MemoryISSCC, 2016