Charge Trap Adoption Across Vendors

Secondary sources

• Samsung first V-NAND reported 84% less coupling interference and 33% tighter natural Vt distributions than 1X nm floating-gate NAND, tPROG under 0.5 ms (about 1/3 of MLC FG).

  Published resultFigures: 84%; 33%; <0.5 msCharge-Trapping Non-Volatile Memories

• The V-NAND tunnel layer is barrier-engineered SiON with a thin Al2O3, and the gate is TiN and tungsten.

  Published resultCharge-Trapping Non-Volatile Memories

• In planar arrays Micron found nitride and nanodot storage layers share charge laterally, so stress-induced-leakage immunity was not realizable.

  Published resultCharge-Trapping Non-Volatile Memories

• Charge-trap erase saturates about 5 V higher than floating gate; detrapping the nitride needs fields above 15 MV/cm.

  Published resultFigures: 5 V; 15 MV/cmCharge-Trapping Non-Volatile Memories

• Charge-trap retention paths: thermal emission, trap-assisted tunneling, lateral diffusion and fast initial loss; after cycling at high temperature retention is worse than floating gate.

  Published resultSemiconductor Memories and Systems

• TCAD of cylindrical SONOS shows the tunnel field rises and the blocking field falls with curvature.

  Published resultCharge-Trapping Non-Volatile Memories

• Samsung’s first V-NAND improved natural Vt distributions by about 33% and cut coupling interference by 84% compared with 1X nm floating-gate NAND.

  Published resultFigures: 84%; 33%Charge-Trapping Non-Volatile Memories

• Samsung’s first V-NAND had an average page programming time under 0.5ms, one-third of conventional MLC floating-gate NAND.

  Published resultFigures: <0.5msCharge-Trapping Non-Volatile Memories

• In Micron’s planar charge-trap arrays, the nanocrystal and nitride storage layers suffered quick charge redistribution, and the expected SILC immunity was not realizable.

  Published resultCharge-Trapping Non-Volatile Memories

• In Micron’s silicon-rich-nitride planar charge-trap array, charge was lost laterally along the continuous SiN layer.

  Published resultCharge-Trapping Non-Volatile Memories

• The erase saturation of 3D MANOS-type charge-trap NAND is about 5V higher than floating-gate NAND, and detrapping electrons from nitride needs fields above 15MV/cm.

  Published resultFigures: 5V; 15MV/cmCharge-Trapping Non-Volatile Memories

• Micron scaled a conductive floating-gate planar cell with a high-K and metal gate to 20nm, with a large P/E window (printed +/-8V), program and erase slope of about 1, and good endurance and retention.

  Published resultFigures: 8V; slope 1Charge-Trapping Non-Volatile Memories

• The planar floating-gate cell has a very thin floating gate of around 10nm and a high-k block dielectric as the interpoly dielectric.

  Published resultNand Flash Memory Devices

• V-NAND suffers a fast initial charge loss that offsets the program verify level and broadens the distribution after verify.

  Published resultCharge-Trapping Non-Volatile Memories

• The biconcave charge-trap layer of TCAT suppresses lateral charge migration in the trapping layer, which improves retention.

  Published resultCharge-Trapping Non-Volatile Memories

• At high temperature, thermionic emission drastically accelerates charge loss, so a bake above 150C may not predict retention at storage temperatures.

  Published resultCharge-Trapping Non-Volatile Memories

• A channel diameter under 40nm gives a field enhancement factor above 1.6, so a 7V pass voltage is already equivalent to 11V in the planar case.

  Published resultFigures: 1.6; 7V to 11VCharge-Trapping Non-Volatile Memories

• Scaling the channel hole of pipe-shaped BiCS to 66nm drastically improves the erasing speed.

  Published resultCharge-Trapping Non-Volatile Memories

• In a gate-all-around channel, curvature enhances the tunnel-oxide electric field while the top blocking-oxide field is reduced.

  Published resultCharge-Trapping Non-Volatile Memories

• The V-NAND gate stack: a barrier-engineered oxynitride tunnel dielectric, a thin (under 3nm) Al2O3 on the blocking oxide mixed with a TiN barrier, then a tungsten gate fill.

  Published resultCharge-Trapping Non-Volatile Memories

• V-NAND uses a barrier-engineered oxynitride tunnel dielectric to improve the P/E window of the SONOS charge-trapping device.

  Published resultCharge-Trapping Non-Volatile Memories

• In 3D charge-trap NAND the benefit of a better P/E cycling window is canceled by the post-cycling data retention, which needs substantial improvement to compete with floating-gate NAND.

  Published resultCharge-Trapping Non-Volatile Memories

• The field enhancement factor (FE) will be more than 1.6 times, so a 7 V pass gate voltage is equivalent to 11 V in the planar case.

  Published resultFigures: 1.6; 7 V to 11 VCharge-Trapping Non-Volatile Memories

• In pipe-shaped BiCS a 90nm channel hole could not erase below 0V, while a 66nm hole erased below -3V at a -22V erase bias.

  Published resultFigures: 90nm; 66nm; 0V; -3V; -22VCharge-Trapping Non-Volatile Memories

• The curvature of a round charge-trap cell raises the field in the tunnel oxide and lowers it in the blocking oxide, which is why a smaller hole erases faster.

  Published resultCharge-Trapping Non-Volatile Memories