9 facts filed under Reliability mechanisms: all 9 are reported by a second source. Each was checked against the source’s own words, so its figures appear there, and each names where it comes from. The idea is taught in Part 4, 3D NAND Stacking.
Secondary sources
After a read on a string with programmed cells the wordlines fall from several volts to 0V, the string cuts off, and the floating channel couples down to about -5V; planar never sees this because its p-well supplies holes.
One vertical-gate test chip erased with about 13 V on source and bitline sides and about 6 V on the select gates.
Erase hole injection shifts the select gates own thresholds; a trap-free select gate was proposed.
After a read on a string with programmed cells the wordline falls from about 8V to 0V, the string shuts off, and the floating pillar body couples down to a negative potential such as -5V.
In 2D NAND the channel surface connects directly to the P-well, which supplies an unlimited amount of holes, so the negative body never occurs.
Select transistors that use the cell’s trapping dielectric can suffer unwanted charge injection; for example, hole injection during erase may lower the select transistor’s VTH.
A charge-trapping-free gate dielectric was proposed for the select transistors to avoid the negative bias needed to hold them off.
In 3D vertical-gate NAND, erase applies a large voltage on the common source line and main bitline, while an intermediate voltage of about 6V goes on the string and ground select lines.
In 3D vertical-gate NAND erase, the select transistors are biased to pass the 13V erase voltage from the source lines to the channel.
Sources
Primary is the original paper, standard or datasheet. Secondary is a review, a vendor summary or a news report. Measured is my own test data.
Show all 2 sources
- SecondarySemiconductor Memories and SystemsWoodhead Publishing (Elsevier), 2022
- Secondary3D Flash MemoriesSpringer, 2016