6 facts filed under Host interfaces and protocols: 5 read in the original source and 1 reported by a second source. Each was checked against the source’s own words, so its figures appear there, and each names where it comes from. The idea is taught in Part 1, Standards & Interfaces.
Primary sources
Packet efficiency = payload / (payload + overhead); with 12 B header and no ECRC overhead is 20 B: 128 B MPS 86%, 256 B MPS 92%, 512 B MPS 96%.
PCIe Gen 3 signals at 8.0 GT/s per lane with 128b/130b encoding, so an x4 link carries about 3.9 GB/s per direction (7.9 GB/s full duplex) before packet overhead.
TLP overhead is 20 to 30 bytes depending on Gen2 or Gen3 speed, 32-bit or 64-bit addressing, and optional ECRC.
Gen4 runs at 16GT/s per lane, about 8GB/s on x4 (16GT/s x 4 lanes / 8).
After packet and traffic overhead, Gen3 delivers an overall efficiency of 7.8Gb/s per direction per lane.
Secondary sources
Tom’s Hardware says PCIe 6.0 doubles host interface bandwidth to around 30.25GB/s for a x4 link.
Sources
Primary is the original paper, standard or datasheet. Secondary is a review, a vendor summary or a news report. Measured is my own test data.
Show all 4 sources, 3 primary
- PrimaryUnderstanding Performance of PCI Express Systems (WP350)AMD Xilinx, 2014
- SecondaryThe current state of PCIe 6.0 SSDs and controllersTom's Hardware
- PrimaryPCI-SIG FAQ - PCI Express 4.0PCI-SIG
- PrimaryPCI-SIG FAQ - PCI Express 5.0PCI-SIG