Timing Degradation with Wear / Eyes on Flash

3 facts filed under Reliability mechanisms: 1 read in the original source and 2 reported by a second source. Each was checked against the source’s own words, so its figures appear there, and each names where it comes from. The idea is taught in Part 3, From Cell to Die.

Primary sources

Program latency falls, not rises, with P/E wear in planar flash.
Published resultFigures: SLC about 50% faster over life; MLC 10-15% fasterCharacterizing Flash Memory:Anomalies, Observations, and Applications

Secondary sources

The erase exits with a fail if the maximum number of erase pulses (ZMAX, typically 4) is reached.
Published resultFigures: up to 4 pulses; about 23 V; about 1,025 usInside NAND Flash Memories
One published planar erase optionally programs every wordline first, with no verify, stepping from 12V to 17V in 1V steps over about 150 μs.
Published resultFigures: 12 to 17 V in 1 V steps; about 150 usInside NAND Flash Memories

Sources

Primary is the original paper, standard or datasheet. Secondary is a review, a vendor summary or a news report. Measured is my own test data.

Show all 2 sources, 1 primary

PrimaryCharacterizing Flash Memory:Anomalies, Observations, and ApplicationsMICRO, 2009
SecondaryInside NAND Flash MemoriesSpringer, 2010